[ARTY A7- multiple VHDL Code combining in to one Vivado design...]

Hi I am using Vivado 2020.2 and trying to master combing multiple  VHDL  files  into on Vivado  Design.

Each Design has been tested and works in isolation. Each has it own XDF file driving their own  logic inputs / outputs.

One is a Pulse Processor synchronizing to a external 1O MHz CLOCK( WITH THE external  10 MHz coming in  on a I/O input pin, and various timing signals coming out on the PMODs  JA,JB JC and JD. 

The second design is a UART and some "CASTING" between Std Logic Vectors and integers. 

Each design have their own I/O, and the only shared input is the 100MHz clock. 

Now I want to combine in Vivado ONE design. I know I need  to generate the top file with the individual designs below, but the finer specifics and necessary detail is not not apparent on any of the training/ or targeted searches.  I would expect this is "102" level training . 

Can any one  point to any appropriate videos links . Any advise appreciated . 

Regards. Peter. 

[I have fallen into the Xilinx SDK discontinue trap in Version Vivado 2019.2 on...]

HI-  Thanks for your comments. Sorry for delay.  We have decided to go back to version 2017.3 with SDK, but as expected just plan old  VHDL will not port  back- no big deal- just need to re create and cut and paste in, and should  run ok. No explanation way - just  will not open, even  though  there is no IP- just plain VHDL. 

The main push is to get SDK running on 2017.3 and get on with the Job( if IP UART effort  is warranted…/ a benefit .)

Ironically I had to go to a faster laptop since synthesis (with IP) took hours compared to minutes on multi core- another  reason to keep it simple. 

Have a UART of sorts running. but will need to tidy up if I need it … base on..
UART in VHDL and Verilog for an FPGA (nandland.com)

https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html
 Thanks Russell  !
 
Thanks for the comments loading the older versions and taking less disk space. 

Comments greatly appreciated.
P.

[I have fallen into the Xilinx SDK discontinue trap in Version Vivado 2019.2 on...]

Hi All- I have fallen into the Xilinx SDK  discontinue trap in version Vivado 2019.2. I am on a "roll with" SKD Microblaze. I  have Vivado 2020.2 that does not include SDK. If I down load Vivado 2019.1 - this is the last  operating SDK version- Can I expect  my 2020.2  VHDL to run on 2019.1 version- given my VHDL is very simple bit bashing logic lines- and no IP. I am in the process of attempting a UART but in the SDK ( part of training we paid for  ... but will be used in a lab prototype  as soon as possible ... my management expect it to be routine...). I will have to remove 2022.2 version to fit 2019.1 (last SDK?)version on my lap top.  If there  are going to be hiccups  I would like to know before.  

Alternative shall I digest.. the detailed Vitis .. 

https://projects.digilentinc.com/whitney-knitter/hello-microblaze-on-arty-a7-70d9e1

  

My immediate object is to get some parameters in to my VHDL via a Rx UART receiving integers. No doubt there are some tutorial I am not yet aware of. 

Or  the best to digest Vitis or pursue SDK in  Vivado 2019.1 version? 

 Any advice appreciated.. 

 

[ARTY A7 - Bringing in an external 10 MHz clock to differential Inputs ?]

Hi  Zygot,

thank you for your response and concise response. My concern was it possible and I was missing something . You answered  my concern, the ARTY A7   can not input a 10MHz Ref . You have provide me with a back ground task of selecting a suitable board able to route a Ref into the clocking back bone / MRCC.  I had a look for a comparison matrix of  board capability, but nothing  obvious on the  DIGILENT web site, so will examine the different board types in detail.  

My immediate requirement can be met using a less elegant alternative approach.

Thank you "Xilinx Series 7 SelectIO reference manual" recommendation - I now have and will digest. 

Thank you  for your assistance,

Regards,

Peter. 

[ARTY A7 - Bringing in an external 10 MHz clock to differential Inputs ?]

Hi FPGA experts 

Regarding - ARTY A7 - Bringing in an external 10 MHz clock to differential Inputs ? A XDC problem? 

An external 10 MHz clock is required  to be brought in on a differential   input. The PMOD A,B,C & D inputs are not differential . Can the clock be brought in on the ...

##ChipKit Single Ended Analog Inputs
##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5). 
##      These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19].

#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0]# Ground??
#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] ##,- Clock

Is this beyond the ARTY A7 board?

Is the capability not extant on the ARTY XDC file ?

Look forward to comments,

regards,

Peter.