ivansavy

The solution is to call XSpi_IntrGlobalDisable(&XSpiInstance) after XSpi_Start(&XSpiInstance).

921600 baud is the highest value that most terminal applications will run at, and certainly if you don't use hardware flow control. FTDI has a terminal application for its USB-UART bridge devices and that only works up to 921600. I believes that this is the limit of the VCP driver capability that Windows wants ot use by default for USB serial devices. Of course you can do higher baud rates up to the limit of the bridge device which is 3 Mbaud or 12 Mbaud for H devices. For FTDI devices you need to use a different driver, write your own software application, and use hardware flow control. I've don't this but it's tricky. For a device like the FT232H 8 Mbaud is more practical.

I don't know how it works on MicriBlaze, but for a ZYNQ device you can set the UART baud rate in the board design ZYNQ subsystem block. I doubt that the Vitis console supports baud rates of 921600 as the SDK doesn't, but you can always use a different application for UART communications with your FPGA.

While high baud rates via UART connections seems to be desirable there are a lot of issues to address complicating real world application.

Hi @Mathias
The instructions are long mostly because they are written to be fairly verbose and (ideally) clear.
Vitis should not be that big to install; or at least when I use the self-extracting web installer and only leave board options that I need checked, the final disk installation size of both Vivado and Vitis 2021.1 for me is just shy of 70 GB. Makes me yearn for the less than 15 GB size that 2015.4 was to be sure, but that's neither here nor there.
I asked another co-worker to make a DDR demo and they're hoping to get it completed in the next couple of weeks (in between all of their other tasks and making sure the documentation/tutorial aspect is clean).
Let me know if you have any questions.
Thanks,
JColvin

Hi @Mathias,
If you are only wanting simple example that has the DDR memory being tested, you can follow this guide which walks through setting up DDR memory and MIG on the Arty S7 board in Vivado and exporting it into Vitis: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi. When choosing an application project in Vitis, there is a premade Memory Test which then does a test write and read back of data to the DDR.
As for a more pragmatic design that doesn't rely on the processor (or one that does) Digilent does not currently have one that I know of, though I will ask for one.
Thanks,
JColvin

Hi @Willard,
The 12 MHz clock is coming from IC10 which is a 12.000 MHz oscillator that also provides the 12 MHz for the FT2322 chip. This particular IC is on the "intentionally left blank" page of the schematic, but you can see the actual IC10 on the underside of the Arty S7 between Pmod JA and Pmod JB. There isn't anything fancy about the connection; if you hold up the board at the right angle, you can see the trace running from IC10 through a couple of resistors and then into F14 on the FPGA itself.
The 100 MHz oscillator that is recommended to be used for the MIG to run DDR based designs is IC3 on the underside of the board between BTN0 and the 6-pin SPI header (J7). That one is visible on page 5 of the Arty S7 schematic, https://digilent.com/reference/_media/reference/programmable-logic/arty-s7/arty_s7_sch-rev_e.pdf.
Let me know if you have any questions.
Thanks,
JColvin

Including the xil_io.h header removes the error and allows me to successfully run the application. I assumed that my custom IP header contained all the necessary operations, but I traced them and there was no mention of the read/write operations. Looking at my other applications, they all include files which somehow trace to xil_io.h.