moncefou

so i created this project , to display the video from camera OV7670 through VGA on my Zedboard , only using the PL part , the synthesis runs good but i when i try to generate the bitstream i get these errors that i can't seem to understand : error 1 : [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pclk_IBUF] > pclk_IBUF_inst (IBUF.O) is locked to IOB_X0Y43 and pclk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y7 error 2 : [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. error 3 : [Common 17-69] Command failed: Placer could not place all instances here is a link where you should find everything you need if you you want to take a look : www.github.com/moncefou/camera_vga_zedboard