dylcobfp

Hi @JColvin, thank you again for the indepth reply After further investigation we have come to the conclusion that this is not a hardware problem, but rather attributed to the fact that we were placing the mode bits of the flash into continuous Quad IO Read mode to save having to write out the instruction. This caused confusion in the part when the PROG_B went low and the reset sequence began, since the FPGA was expecting the bitstream but the flash was expecting a Quad IO Read We have since resolved the problem and confirmed that it works as expected Thank you

Hello, I need a full schematic of the Arty S7 eval board with the Spansion 128Mb flash on it please The one provided at https://digilent.com/reference/_media/reference/programmable-logic/arty-s7/arty_s7_sch-rev_e.pdf doesn't show the full pinout of the Spansion flash; I'd mainly like to focus on the config bank and the interface to the spansion flash. My current board I based off the design of the Arty S7 for the configuration and flash, however my hard reset (PROG_B) requires 2 pulses to reset the part and I believe that is due to the flash. The Arty only needs one, so I would like a more in depth look at how the flash is laid out to see if there are any differences between the two - I think my solution for this is to wire INIT_B to the RESET# pin of the flash, but I want to see if that is necessary