If you populate a signed 16-bit std_logic_vector with a signed 14-bit ADC value the low two lsbs will be zero and unimportant. If you scale the ADC word to calibrate the span then those lsbs are no longer 'unimportant'. If you sample at 100 MHz but really are only interested in a 6.25 MHz bandwidth then you can decimate those 100 MHz 14-bit samples and get 16-bit samples at a 6.25 Mhz rate. The assumption that a 14-bit ADC is providing 14-bits of dynamic range is not a good one... so regardless of your system design those lsbs are something to understand, especially if you are processing the sample data. That, as they say, is an exercise for the student. There's a lot going on with analog to digital conversion. It's not a trivial subject for either practical implementation or theoretical musing.
[edit] As to what, exactly the low n-lsbs of any particular ADC code output represents is a matter worthy of inquiry by all students ( i.e. users ) of such circuitry or components. Indeed, for some applications replacing a few of them with random data for improved performance has been a tried and true technique for a long long time.
