lukelouyu

Add "/r/n" in sprintf((char*)command, "GET https://api.thingspeak.com/channels/"ThingSpeak_Channel_Num"/fields/1.json?results=1" );
 
 

Hi @lukelouyu,
I guess I am a bit confused; if you are able to get the pH and EC sensor working as expected with the xadc demo that you linked (which seems to be originally designed for the Zedboard for an older version of Vivado based on the screenshots used) and getting expected voltages after doing some conversions, I'm not certain what issue you are running into; just not being able to then generate the bitstream after adding more Pmods?
I'm not certain what problem you are seeing with the Peripheral I/O pins on the Zynq block reconfiguration screenshot; from what I can see it is the same as the Digilent block configuration that I have for the Zybo Z7-20 on Vivado 2019.2. One screenshot in the Lab3 document shows disabling Timer0 for the APU, but that is already done by default in the Digilent board files for the Zybo Z7-20. I'm guessing they needed to do it in the tutorial because the tutorial creators were using a different set of board files for the Zedboard and didn't have the Zynq IP pre-configured as needed.
I don't have all of the Pmods with me while working from home to test anything, but I did the following steps to get a bitstream and successfully reporting data received by the xadc (which Pmod JA) is attached to on a serial terminal in Vivado 2019.2
Add Zynq IP to new empty block design and run block automation with board preset Double click on Zynq IP to add a second PL Fabric clock (FCLK_CLK1) at 100 MHz for the Pmod ESP32 From the board tab, add in the different Pmods to their connectors (ALS JB, AQS JC, HYGRO JD, ESP32 JE) but not clicking run connection automation. Add in XADC wizard IP. Double click on the IP to reconfigure the defaults to enable Channel Sequencer and have vauxp6, 7, 14, and 15 enabled and vp/vn disabled. Make Vauxp# and Vauxn# on the XADC wizard IP external. Run Connection Automation. Make sure to have three clock sources (master, slave, and bridge if I recall the names correctly) for both the GPIO and UART AXI interfaces on the Pmod ESP32 be set to the 100 MHz clock in the pop-up where you select which things you want to automate. I left all of the other connections to be default, but you can specify for them to use the default 50 MHz fabric clock. Validate the design, acknowledge the messages on negative DQS skews, and create a wrapper. In the sources tab, add a constraints file with the following details:
set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { vauxp14_0 }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p           
set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { vauxp7_0 }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P             
set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { vauxp15_0 }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P            
set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { vauxp6_0 }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P             
set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { vauxn14_0 }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N        
set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { vauxn7_0 }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N             
set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { vauxn15_0 }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N            
set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { vauxn6_0 }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N Generate a bitstream and export the xsa including the bitstream I kept getting various errors on the Vitis side of things with the xadc so I haven't gotten to debug those, but if you are able to reliably use the xadc code you posted, adding in other Pmods to the associated block design should in theory be more straightforward. I'll keep looking into it tomorrow.
Thanks,
JColvin