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stefano134

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Posts posted by stefano134

  1. here are the times of the board
    i see that it has a problem in the delays.
    i tried of course to follow the tutorial of the board but it's not possible to follow them, since with the new files of the board they changed the ui_clk, and even changing the ui_clk the problems remain.
    by now i've tried more than 30 different configurations and none of them works. is it possible that it's so complicated to make a simple block diagram with a DDR3 memory and an ethernet port? it would be enough for me just one working configuration.

    DDR3_i.png

    DDR3_o.png

  2. Hi,
    i am in possession of a digilent genesys 2 board and i am experiencing a big problem on the use of DDR3 SDRAM memory and ethernet port in vivado 2019.2. 
    every time i try to insert in the block diagram the DDR3 SDRAM memory and the ethernet port, even if i can generate the bitstream without errors or critical warnings taking it to vitis and programming the board (even with a simple hello word program to print on the uart port) it doesn't work and doesn't give any sign of working. if i remove the ethernet or the sdram ddr3 everything works. i've been trying for a month and i have no results. i would like to know if there is a way to solve the problem or maybe i have a problem with the board and i have to replace it. i attach the images of the block design.

     

    Vivado_SDRAM.jpg

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