I'm trying to compile a design using USB104A7 board. The issue is with the DDR3L memory. It fails with the following issue.
Even after implementing the workaround suggested by Xilinx the error is the same.
[DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are MainDesign_i/clk_wiz_0/inst/clk_out1.
Clk1 - 166.667Mhz connected to sys_clk_i
clk2 - 200Mhz connected to clk_ref_i
Is there a working design that uses the DDR3L ram properly on this board. The OOB design feeds the clock directly from the on board crystal without a clocking wizard. Even following that design and adding a separate clocking wizard leads to the same issue.
Seems this comes from the hardware clock pin allocation. Any ideas how to resolve this.
usb104_a7.tcl
