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Kyle_ISL

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    Kyle_ISL
    Kyle_ISL reacted to Niță Eduard in Removing debug logic of pcam-5c reference design   
    Hello @Kyle_ISL,
    Firstly, you can check the video resolution by double-clicking the Video Timing Controller and going over to Default/Constants. There you can see the Video Format.
    For more information on the Video Timing Controller, AXI-Stream to Video Out and the RGB2DVI ips you can check out the user guides here:
    https://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_2/pg016_v_tc.pdf
    https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf
    https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf
    Best wishes,
    Eduard
  2. Like
    Kyle_ISL
    Kyle_ISL reacted to thinkthinkthink in Removing debug logic of pcam-5c reference design   
    Sorry but I couldn't replicate you problems, it worked first try for me following the exact same steps as you did.
     
    But I can recommend some things you can try to hopefully get the project working properly. 
    First you can try resetting the output products by right-clicking the block design file and then clicking "Reset Output Products...".

    Then go to Tools -> Settings... -> IP, press the Clear Cache button and then click OK.


    Now go to the Design Runs tab, right-click on impl_1 and select Reset Runs. Do the same thing for synth_1 as well.

    After that click on Generate Bitstream and wait a bit for a new bitstream to be completed. If somehow you get some critical warnings telling you that the MIPI_D_PHY_RX_0 IP was packaged with a different board_part you can just ignore those by pressing OK and then clicking on Generate Bitstream again.
    Now you should export the new hardware handoff and launch the SDK again (if the SDK is already open you don't have to launch it again).
    Right-click on system_wrapper_hw_platform_0  and select Change Hardware Platform Specification to update it to the new hardware handoff.

    After that you should clean the entire workspace and then build it all again.

    Finally, you can program the FPGA and run the application again.
    You will hopefully see something like this in your tera term console:

    Please do let us know if you've encountered other problems or if, after following all these steps, you still couldn't manage to get the application working properly.
  3. Like
    Kyle_ISL
    Kyle_ISL reacted to haider in Removing debug logic of pcam-5c reference design   
    Hello,
     
    I'm using zybo z7 2010,  Pcam 5c with vivado 2019.1 for Zybo Z7 -20 Pcam 5C Demo 2019.1 release. I the following steps.
    1. open project
    2. change device to zybo z7 7010 
    3. update all IPs
    4. create HDL
    5. synthesis and impliment.
    I'm getting no error till here but following critical warnings after open implementation.
    [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
     
    6. generate bit
    7. export to hardware (include bitstream)
    8. lanch SDK
    after this I followed the exact steps given on README file on github.
    9. program fpga 
    10. and run as debug
    I'm getting no error but still not able to get the image on the screen or the menu on the terminal.
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