White Horse Software

Wanted to follow up and say thank you, inserting OBUFDS fixed the issue. Bitgen complete! Now on to further challenges...

I can muddle through reading Verilog so this is appreciated. I'm at hobby level so I can afford to choose language based on personal preference. I tried getting into Verilog a while back but ended up favoring VHDL... that is, until the day the mysterious "perfect HDL language" materializes from forum discussions into reality.

Okay, now I understand better. I was indeed thinking, like you said, that the constraints file would be all that is needed. I'll give this a shot. Thanks also for the UG472 ref.

Thanks for the response. This same error is happening in a more substantial project, with other HDMI ports in use and actual (useful) circuit designs - I'm doing it all, no IP, partly as a hobby project. It simulates and even synthesizes with no issues. So my hope was to cut through the noise and recreate in a minimum-viable way for presenting the problem. > Your HDL source and constraints must agree and the port names must match in both places. Don't they? Sorry I'm in a rush at the moment, but glancing at the .vhdl and the .xdc, things like "hdmi_tx_clk_n" do in fact match up. Would you mind helping me better understand?

Using Vivado 2020.1, with the Digilent-provided .xdc constraints and a simple .vhdl using HDMI TMDS ports. The project will not generate a bitstream because it fails with the error: "[DRC IOSTDTYPE-1] IOStandard Type: I/O port hdmi_tx_clk_n is Single-Ended but has an IOStandard of TMDS_33 which can only support Differential". In fact this error shows up for any of the HDMI ports I use. Does anything special need to be done to configure these ports? I don't see anything in the reference documentation. Please note this is not a question about how to set up .vhdl for actually using the HDMI ports properly. I'm simply pointing out I don't see how to even configure the ports for TMDS. The .xdc and .vhdl files are attached. Arty-Z7-20-Master.xdc test.vhdl