Low HS2 2-Wire JTAG throughput due to gaps in TCLK in FPGA Posted September 16, 2021 Hello, I'm using DJTG Apis to communicate over 2-Wire JTAG. Major implementation makes use of the below API. DjtgPutTmsTdiBits(HIF hif, BYTE * rgbSnd, BYTE * rgbRcv, DWORD cbitpairs, BOOL fOverlap) Could you please comment on the following observations. TCLK time period/frequency varies a lot. There are gaps in between TCLK chunks and it reduces the throughput. Any resolution or help on this is highly appreciated. Thanks, Akhil
Low HS2 2-Wire JTAG throughput due to gaps in TCLK
in FPGA
Posted
Hello,
I'm using DJTG Apis to communicate over 2-Wire JTAG. Major implementation makes use of the below API.
DjtgPutTmsTdiBits(HIF hif, BYTE * rgbSnd, BYTE * rgbRcv, DWORD cbitpairs, BOOL fOverlap)
Could you please comment on the following observations.
Any resolution or help on this is highly appreciated.
Thanks, Akhil