bob_ee

thanks for the datasheet link, it helps. I do see the chip spec is 2 LSB's w/external reference for a 12 bit code as you wrote. With the Zybo's VAUX14 p/n input shorted I am seeing a maximum of 5 counts. Currently, I am using the PMOD JE as the clock input as that connector was the furthest away from the XADC's PMOD JA analog input. This seems to be the next step up from the Zybo in the Digilent product line. It has an option ADC board with SMA connectors. Any idea of its ADC performance? https://digilent.com/shop/eclypse-z7-zynq-7000-soc-development-board-with-syzygy-compatible-expansion/

Hello Digilent, I have purchased several Zybo Z7-20 FPGA board for a application using the XADC to sampel external voltages. The question I have is what is the expected XADC noise using a Zybo-Z7-20 board using the external analog input? Can you tell me what to expect for noise with this 12bit XADC if the analog input is terminated? My application uses an external 10Mhz clock to be applied to the Zybo, is there a PMOD connector/pin that I can use for the external clock that has lowest cross talk to the sensitive analog inputs? Thanks, Bob