Sorry but I couldn't replicate you problems, it worked first try for me following the exact same steps as you did.
But I can recommend some things you can try to hopefully get the project working properly.
First you can try resetting the output products by right-clicking the block design file and then clicking "Reset Output Products...".
Then go to Tools -> Settings... -> IP, press the Clear Cache button and then click OK.
Now go to the Design Runs tab, right-click on impl_1 and select Reset Runs. Do the same thing for synth_1 as well.
After that click on Generate Bitstream and wait a bit for a new bitstream to be completed. If somehow you get some critical warnings telling you that the MIPI_D_PHY_RX_0 IP was packaged with a different board_part you can just ignore those by pressing OK and then clicking on Generate Bitstream again.
Now you should export the new hardware handoff and launch the SDK again (if the SDK is already open you don't have to launch it again).
Right-click on system_wrapper_hw_platform_0 and select Change Hardware Platform Specification to update it to the new hardware handoff.
After that you should clean the entire workspace and then build it all again.
Finally, you can program the FPGA and run the application again.
You will hopefully see something like this in your tera term console:
Please do let us know if you've encountered other problems or if, after following all these steps, you still couldn't manage to get the application working properly.
