[Executables selected for download on to the following processors doesn't exist or incorrectly specified. Do you wish to ignore and proceed? 1. microblaze_0]

On 3/30/2022 at 8:24 AM, elodg said:

That settles it, your code does not fit the instruction memory. Function printf is rather large, due to floating point support. You can use xil_printf, which does not have that and should fit.

Use the Address Editor in Vivado to increase instruction memory.

This solved the problem, thank you so much for the suggestion!

Curtis

[Executables selected for download on to the following processors doesn't exist or incorrectly specified. Do you wish to ignore and proceed? 1. microblaze_0]

On 3/28/2022 at 5:13 AM, elodg said:

Hello world fits comfortably and you could not have possibly added too much with extra lines. Most probably you have a build error, so the elf file does not get created, so there is nothing to download to the processor. Check the console and build log.

If the code did not fit you would see a link error in the build log. In this case, check the Microblaze config of the hardware project, which specifies how much BRAM is to be used for instruction and data memory.

@elodg,

This is pointing in the right direction.

As I mentioned, the Hello World code is in addition to the axi_gpio code. The extra printf statements found the point where the code size was exceeded and the compilation would fail. I attached the C code file which compiles. However, when I un-comment the //printf("\nHello1\n\r"); statement at line 111 and subsequent statements, the code breaks (i.e., the elf file is not created).

So I think the solution is to increase the instruction and data memory sizes. So... how is this done?

Thank you in advance for your help.

Curtis

Here is the overflow message when I add in the extra printf. The bram overflows by 24 bytes:

c:/xilinx/vitis/2020.1/gnu/microblaze/nt/x86_64-oesdk-mingw32/usr/bin/microblaze-xilinx-elf/../../libexec/microblaze-xilinx-elf/gcc/microblaze-xilinx-elf/9.2.0/real-ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 24 bytes

collect2.exe: error: ld returned 1 exit status
 

helloworld.c

[Executables selected for download on to the following processors doesn't exist or incorrectly specified. Do you wish to ignore and proceed? 1. microblaze_0]

I checked other links in the Digilent forum and couldn't find a solution or a problem with these symptoms. I'm running Vivado 2020.1 and Vitis 2020.1 on a Digilent Nexys A7 100T.

What I found is that there seems to be a limit as to how large the c code file in Vitis can be.

Here is the scenario as to how I discovered this:

1. In Vivado, I created a block design with a microBlaze and four axi_gpio(s)
2. I wrote C code in Vitis to initialize and read / write to the axi_gpio(s)
3. I included "Hello World" to verify that the COM port was working. It did.
4. When I added extra lines to the C code, I found that too many lines of code caused the "Executables selected for download on to the following processors doesn't exist or incorrectly specified. Do you wish to ignore and proceed? 1. microblaze_0"
5. I clicked 'Proceed' (as suggested in one of the other threads) and the program didn't run.
6. I tried cleaning and rebuilding the program and this didn't help either.
7. I removed the extra lines of code (which were printf statements), and then the program worked.

Question:

1. Do I need to make a memory module larger in the block design to accommodate the larger C code file? If yes, which memory and how?
2. Or is there another solution? 

Thank you in advance for any suggestions on how to solve this problem.

Curtis

 

[executables selected for download on to the following processors doesn't exist or incorrectly specified. Do you wish to ignore them and proceed? 1.ps7_cortex9_0]

I'm having the same issue. What I found is that there seems to be a limit as to how large the c code file in Vitis can be.

Here is the scenario as to how I discovered this:

1. In Vivado, I created a block design with a microBlaze and four axi_gpio(s)
2. I wrote C code in Vitis to initialize and read / write to the axi_gpio(s)
3. I included "Hello World" to verify that the COM port was working. It did.
4. When I added extra lines to the C code, I found that too many lines of code caused the "Executables selected for download on to the following processors doesn't exist or incorrectly specified. Do you wish to ignore and proceed? 1. microblaze_0"
5. I clicked 'Proceed' (as suggested above) and the program didn't run.
6. I removed the extra lines of code (which were printf statements), and then the program worked.

Question:

1. Do I need to make a memory module larger in the block design to accommodate the larger C code file? If yes, which memory and how?

This might not answer your question, but perhaps it will help with your troubleshooting.

Hope this is helpful,

Curtis

 

[demo example of ETHERNET for the NEXYS A7]

On 5/11/2021 at 5:59 PM, AndrewHolzer said:

Hello @CurtisNotestine,

What version of Vivado are you using? Xilinx no longer includes, and has no plans for replacing the Ethernet PHY MII to Reduced MII (MII2RMII) in versions 2019.2 or later. The current work around is to obtain a copy of the IP provided in Vivado 2019.1 or earlier. You can include it in 2019.2 onwards by including it like you would a regular IP repository. This thread has all that information.

Best regards,
AndrewHolzer
 

Andrew, thank you for your reply.

I am using Vivado 2020.1. I'll try your suggestion to use 2019.1 or earlier.

Curtis

[demo example of ETHERNET for the NEXYS A7]

On 4/16/2021 at 2:12 PM, JColvin said:

Hi @hiro_ike,

I looked for this EDK demo project that is mentioned, but have not been able to find it on any of the Nexys Resource Centers, so I'll make sure that line gets removed from the various reference manuals.

There is an old guide for getting a Microblaze server running on the Nexys 4 DDR (it's the same board as the Nexys A7, but without the newer branding) available here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start.

Of note though is that later versions of Vivado (2019.2 and later if I recall correctly) no longer include the MII2RMII IP core and Xilinx does not have any replacement options for it, though you can potentially copy over the source files from earlier versions of Vivado into later versions. Both of these things are noted in this Xilinx forum thread.

Thanks,
JColvin

I tried running the "old guide" on a Nexys A7 and there is a problem with step 3.1 : The IP "Ethernet PHY MII to Reduced MII" is not a menu selection

--------------------------------------

3.1) We will now add all of the necessary IP blocks to our project. There are 4 cores we will add:

* Memory Interface Generator

* Ethernet PHY MII to Reduced MII  <<< ------ DOES NOT EXIST IN THE IP MENU

* AXI Uartlite * AXI EthernetLite

* AXI Timer

--------------------------------------

What is the workaround for this? (I tried adding some of the other ethernet IP from the menu and they did not work.)

Is there a tutorial (that works) to demonstrate the NEXYS A7 Ethernet IP?

    - I have spent many hours trying to get this to work.

    - I tried adapting this YouTube tutorial without success: https://www.youtube.com/watch?v=QhTYsysSkB0&t=1246s

My thanks in advance for any suggestions.

Curtis