rt54321
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Topics posted by rt54321
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Question: HLS project: GPIO to Master AXI only works with 1 out of 8 input ports
By rt54321, in Digilent Microcontroller Boards (Retired)
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- 1 answer
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Question: Basic verilog question - hardware driver for an AD7606 and the "always" block
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- 4 answers
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Question: Arty Z7 - can't debug anymore, "Cannot access DDR: the controller is held in reset"
By rt54321, in Digilent Microcontroller Boards (Retired)
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- 1 answer
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Question: Arty Z7 - GPIO interrupts and edge sensitivity
By rt54321, in Digilent Microcontroller Boards (Retired)
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- 0 votes
- 3 answers
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Question: Spliting single wires off of a bus in Vivado
By rt54321, in Digilent Microcontroller Boards (Retired)
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- 0 votes
- 3 answers
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Question: Preferred AXI bus type for a real time application
By rt54321, in Digilent Microcontroller Boards (Retired)
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- 0 votes
- 1 answer
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Question: Arty Z7 board using DP0-DP13 and DP26-DP41 pins: warnings received
By rt54321, in Digilent Microcontroller Boards (Retired)
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- 0 votes
- 1 answer
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Question: Arty Z7 - interrupting only on a single GPIO pin in DP0-DP13
By rt54321, in Digilent Microcontroller Boards (Retired)
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- 0 votes
- 1 answer
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Question: Can't find Zynq processing system in "Add IP" (Vivado 2020.2)
By rt54321, in Digilent Microcontroller Boards (Retired)
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- 0 votes
- 1 answer
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Question: Cpp examples for the Arty Z7
By rt54321, in Digilent Microcontroller Boards (Retired)
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- 0 votes
- 6 answers