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RCB

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  1. Like
    RCB got a reaction from NN_SystemS in Zybo Z7 compatibility with zynq XC7Z030   
    Hey!
    Zybo Z7010 is a popular device with very good support here in the forum. I started with Zybo Z7020 over 7010 predominantly because of additional capabilities that I would like to be available for future projects. I have not faced any problems with the board because Digilent has the board support tools for z7020 and the hw/embedded programming experience is similar to the 7010. 
    For hardware design, specific builds target specific boards. It will be very apparent if you are juggling between different boards with Vivado tool. Internal code might be good for building on different devices but if the logic would be compatible for implementation across devices cannot be guaranteed. 
    But Z7010 is a good board to start with. If the whole project is not entirely compatible with your future boards, it at least guides you through logical errors. 
  2. Like
    RCB reacted to zygot in Phase detection of high-frequency signals on Zybo | High sampling ADCs or phase detection pmods?   
    I love hearing about projects done for personal edification. The best engineers like doing engineering because they are curious and love the challenge.
    I don't know of any add-on boards for doing what you want to do using analog circuitry.  But perhaps I could give you an idea or two to ponder without spoiling the adventure. Perhaps there are multiple paths to explore.
    Let's say that you have two 5 MHz sine signals with a fixed phase offset between them. Thinking about them, as two separate signals suggests a straight-forward time domain analysis for phase detection using direct analog to digital conversion and some mathematical magic. But what if you choose to think about them as the product of a sine-wave generator driving a variable impedance load? One representing voltage and the other current at the load. If you think about them in that context, the thought of considering power as it relates to magnitude and phase offset might lead to an interesting approach. As long as you don't have to deal with instantaneous phase offset that 1 MHz Fs isn't looking so inadequate. Can the XADC and some analog manipulation get you phase detection to within +/- 1 degree? I doubt it, but I doubt that the brute-force approach and a pair of 100 MHz "14-bit" ADCs will either. But you can come up with a rough estimation of what it would take. Instead of expecting to hit the target on the first cut I'd suggest starting out with lower objectives and seeing how different approaches go. This is why, when doing experiments because you want to learn, the journey really can be more valuable that finding answers. Usually, along the way you find more questions to answer. Sometimes, these are more interesting than the original problem. Almost certainly the result of constructing experiments to solve problems makes your conceptualization of what's going on in the hardware less naive.
    That's just one thought. I'm sure that you can come up with others. 
    There's always a brute-force approach to solving puzzles but sometimes the way that you think about them can lead to an elegant solution using low cost hardware. The point is that the obvious way to approach problems can involve considerable hardware complexity and cost but often there are ways to get around the expensive requirements and still get good enough results to meet your requirements. That's the joy and beauty of embedded design; doing in logic or with limited computational power what a computer does with MATLAB or expensive custom libraries.
    I don't want to discourage you from taking the ADC route as there is a lot to learn about converters and fixed point math using logic. But, we all have budgets to consider. I'm assuming that 5-10 MHz is a fungible criteria. You can almost always scale down the initial specifications to fit a low hardware budget and still come up with an implementation to prove a solution concept. Two audio frequency sine waves would certainly require cheaper hardware. 
    If you want to try building you own add-on circuitry to convert analog measurements to digital data the De0 Nano and Express PCB are easy to use to do almost anything. The De0 Nano has two 40-pin headers for expansion and while not the cheapest way to do you own PCB designs Express PCB, once you get used to its peculiarities, is pretty painless. It just doesn't work well for really high speed connectors and really small parts. You can get some decent ADCs from distributors that work in the 5-10 MHZ range, or perhaps used components to take an alternate route.
     
     
  3. Like
    RCB reacted to zygot in Phase detection of high-frequency signals on Zybo | High sampling ADCs or phase detection pmods?   
    I would certainly agree with you that the 1 MHz XADC, or equivalent, found in modern FPGA deices is inadequate in terms of Fs.
    Unfortunately, there aren't any low cost ( under $200 ) FPGA boards that support ADC or DAC conversion in the 100 MHz and higher Fs range. The Digilent ZMOD1410 dual ADC alone costs more that $200, but is the best low cost ADC module that you are likely to find. The question is what SYZYGY compatible FPGA platform do you want to use. Digilent offers two of them and Opal Kelly a couple as well.
    Unless you are specifically required to implement the entire project as an embedded solution you don't need a ZYNQ based FPGA board. I would suggest that the non-ARM based FPGA platforms are the preferred choice, depending on your HDL skills. Certainly I'd go with something like the XME7320 and a ZMOD 1410. But, this isn't cheap. Terasic's DDC dual ADDC/DAC board on an Intel platform is a decent alternative and could be used with a number of HSMC equipped FPGA platforms. For low Fs applications I'd recommend staying away from the cheaper Terasic ADC boards because they aren't setup for dealing with low speed signalling. 
    Since you mention unspecified additional calculations to be performed I'm guessing that direct signal conversion to digital is an imperative. Given the lack of low cost educational quality hardware available you might consider an FPGA board that isn't limited by 12-pin PMOD interfaces and designing you own ADC add-on board. That would certainly be an impressive implementation, but be careful as the circuitry between your ADC input pins and your signals can easily subvert accurate phase measurements. Seems like an expensive project requirement for a student funded exercise.... If this isn't an educational exercise then I'd be asking about the accuracy/resolution of the phase measurements as this could dictate hardware choices. Designing a solution to a problem that has poorly defined specifications is often a fool's enterprise.
    [edit] I'm assuming a few things here; mostly that this is a student project. I can think of a few potential alternate ways to do this in the analog domain. Of course this depends on your measurement specifications. But it would simplify your signalling interface work and expense. For a student project you generally have to show some understanding of coursework preparation.
    [edit2] I forgot all about FPGA instruments like the AD2 and RedPitya. In the latter case this is an open system that allows for real custom FPGA application development. It also happens to be ZYNQ based, if that's what you want. There are affordable versions with 2 channels of ADCs that might be suitable, though sample depth is limited. You might not require a lot of samples per cycle if you are smart about how you do you detection. Be prepared for a significant amount of software effort. If you can figure out how to integrate the hardware and software frameworks into your project this is probably the most cost effective platform available... at least to my knowledge. You'll need to be proficient in Linux, Verilog and System Verilog to complete a project in any sort of reasonable time frame.
  4. Like
    RCB got a reaction from petriggg in FFT output result using Xilinx FFT core (v9.0)   
    Hey @petriggg
    I am still debugging some blocks and hence decided not to document with bugs. 
  5. Like
    RCB reacted to petriggg in FFT output result using Xilinx FFT core (v9.0)   
    Can you post what you did? Thank you.
    And, please, show your blockdesign (or part of it with FFT), FFT IP parameters.
  6. Like
    RCB reacted to D@n in FFT output result using Xilinx FFT core (v9.0)   
    @RCB,
    Why are you converting things to sign magnitude form, vs just leaving them in twos complement again?
    I'm not certain what's going on.  Were this my own project, I'd use an FFT I'd be able to "see" inside of so that I might debug the problem.  Specifically, I'd look for overflow problems within the FFT--at least that's the only thing I can think of that might cause the bug you are referencing above.  It doesn't make sense, though, that you'd have overflow with one FFT and not with an identical FFT that only differed in output ordering.  You might wish to compare the .xml files of the two FFT's to see if they are truly the same as you believe.  You might also wish to try dropping the amplitude by a factor of 4x or perhaps even 64x to see if that makes a difference.  It might be that you have the scaling schedule messed up and that things are overflowing within.  It might also be that you aren't looking at all of the output bits with your bit-cut selection above--I can't tell by just looking at it from here.
    Dan
    P.S.  I don't work for Digilent, and do not get paid for answering forum posts.
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