Hello,
I'm trying to modify the pcam-5c design for the Zybo board (Vivado 2017.4).
The design takes up a lot of logic for debug especially in MIPI_CSI2_Rx.vhd.
I tried removing this logic by un-checking the "Debug Module" box of the "MIPI CSI-2 Receiver" core inside the supplied block design.
I saved the design and re-run synthesis - which failed with the following message :
Re-checking the "Debug Module" box are re-synthesizing didn't solve the problem.
The only thing that fixed the problem is copying the \src\bd\system\ip\system_MIPI_CSI_2_RX_0_0 folder from a mirror ( untouched ) design.
2 questions:
1. How did un-checking the "Debug Module" box cause the design to break in such irreversible way?
2. How can I reliably remove the ILA debug logic ?