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rakeshm55

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Posts posted by rakeshm55

  1. Hi,

    I am trying out examples for DMA transfer from PL to PS.  As a starting point I try to do it using Xilinx example 

    My current setup is 

    1. Vivado 2018.3

    2. Board Arty Z7 - 20

    Example I am trying to run is in

    https://support.xilinx.com/s/article/57561?language=en_US

    After creating the project using Vivado 2015.1 I opened the project in Vivado 2018.3. As I understand original  project/design files  targets a different board Zc702

    Now I want to port the example project to Arty-Z7. I changed the board to Arty Z7 from Vivado flow navigator to Arty Z7.

    But I do not see any update for Zynq processing system IP in blobk design It has different clock freq, bank voltages DDR setting etc.

    So my question is

    1. How to port a zynq design in one board to a newer board??  i case of  FPGA a projects I could easily do this once the zynq subsystem is in place I find it too complex

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