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Stefano Antoniazzi

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Posts posted by Stefano Antoniazzi

  1. I'm using the USB-JTAG HS3 dongle as JTAG interface to our proprietary systems.

    I implemented JTAG transactions for reading and writing registers on top of the HS3 Adept API.

    This works fine but I noticed that there is always a time gap between transactions I can not reduce.

    More precisely, I can reduce it using large blocks in batch mode but this is not suitable for many individual register read/write ops.

    In fact, the actual data speed looks more than 10x slower than the JTAG frequency. At 15 MHz JTAG I can only perform about 7000 transactions (each one takes about 100 TCK clock cycles).

    I can not believe it is just SW overhead. Is there any reason for that? Is there a way to reduce the gaps?

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