[Differential outputs on Arty-A7]

On 6/9/2020 at 2:32 AM, asmi said:

TMDS uses current driver, so it can't work without termination.

Connected resistors, as per your comment. Outputs now look fine.

Thank you

[Differential outputs on Arty-A7]

9 hours ago, zygot said:

You can figure this out for yourself by going back to the first step of your project. This was reading the Series 7 Select IO User's Manual. Pay attention to the sections on TMDS33 IOSTANDARD, particularly study the termination diagrams. 

Are you referring to UG471? If so, I looked through the sections pertaining to TMDS_33. Just going back through it, the most pertinent section appears to be on P95:
   TMDS inputs require a 50ohm pull-up and no diff term resistor
   Bank voltage is 3V3 and TMDS is available on HR banks 
   TMDS_33 IOSTANDARD supports OBUFDS 

The first point, above, isn't relevant as I'm configuring outputs. The second and third points are satisfied by the design.

There are termination diagrams in the appendices, are you referring to these? 
 

10 hours ago, zygot said:

Are you driving your sys_clk_p and sys_clk_n on clock capable pins? 

Something which also crossed my mind when I first looked at this, but I don't think this is relevant for outputs? e.g. If you look at the clocking resources guide, it explicitly mentions clock inputs should be routed via clock capable pins. It's a bit vague, as it mentions 'clock capable I/O' in some places, but I think that clocks exported from the FPGA should be brought out via an ODDR + (OBUF or OBUFDS) and do not need to be connected to clock capable pins.
 

[Differential outputs on Arty-A7]

Hi, I am experimenting with differential outputs on the Arty A7. For this, I am using the 100MHz clock and have instantiated an OBUFDS --

 SYS_CLK_OBUFDS : OBUFDS
    generic map(
        IOSTANDARD => "TMDS_33"
    )
    port map(
        I => CLK100MHZ,
        O => sys_clk_out_p,
        OB => sys_clk_out_n
    ); 

The .xdc file has the following --

## Pmod Header JB
set_property -dict { PACKAGE_PIN E15   IOSTANDARD TMDS_33 } [get_ports { sys_clk_out_p }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
set_property -dict { PACKAGE_PIN E16   IOSTANDARD TMDS_33 } [get_ports { sys_clk_out_n }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]

Synthesis & implementation are fine and I can generate a bitstream, but I see no output on these pins (just 0v).

FYI, if I use a single-ended output (via OBUF) as shown below, it works fine --

SYS_CLK_OBUF : OBUF
    generic map(
        IOSTANDARD => "LVCMOS33"
    )
    port map(
        I => CLK100MHZ,
        O => sys_clk_out
    ); 

With the .xdc file constraint --

## Pmod Header JD
set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { sys_clk_out }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]

Any idea what I am missing? 

Thanks.