module pmod_step_driver( input rst, input dir, input clk, input en, output reg [3:0] signal ); reg [3:0] r_signal = 4'b0011; always@(posedge clk) if (rst == 1) r_signal <= 4'b0011; else if (en == 0) r_signal <= r_signal; else if (dir == 1) r_signal <= {signal[2:0], signal[3]}; else r_signal <= {signal[0], signal[3:1]}; always @(*) if (en == 0 || rst == 1) signal = 'b0; else signal = r_signal; endmodule