[FPGA] Generate sources [FPGA] Generate Bitstream cd corev_apu/fpga && make BOARD=genesys2 XILINX_PART=xc7k325tffg900-2 XILINX_BOARD=digilentinc.com:genesys2:part0:1.1 CLK_PERIOD_NS=20 make[1]: Entering directory '/home/darshak/cva6/corev_apu/fpga' mkdir -p work-fpga Generating xlnx_axi_clock_converter.xci make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter' rm -rf ip/* mkdir -p ip rm -rf xlnx_axi_clock_converter.* rm -rf component.xml rm -rf vivado*.jou rm -rf vivado*.log rm -rf vivado*.str rm -rf xgui rm -rf .Xil make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter' make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter' vivado -mode batch -source tcl/run.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source tcl/run.tcl # set partNumber $::env(XILINX_PART) # set boardName $::env(XILINX_BOARD) # set ipName xlnx_axi_clock_converter # create_project $ipName . -force -part $partNumber # set_property board_part $boardName [current_project] # create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.1/data/ip'. # set_property -dict [list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {5}] [get_ips $ipName] # generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'xlnx_axi_clock_converter'... # generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'xlnx_axi_clock_converter'... WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc' INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'xlnx_axi_clock_converter'... WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'xlnx_axi_clock_converter'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'xlnx_axi_clock_converter'... # create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] # launch_run -jobs 8 ${ipName}_synth_1 [Tue Oct 10 08:36:07 2023] Launched xlnx_axi_clock_converter_synth_1... Run output will be captured here: /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/runme.log # wait_on_run ${ipName}_synth_1 [Tue Oct 10 08:36:08 2023] Waiting for xlnx_axi_clock_converter_synth_1 to finish... *** Running vivado with args -log xlnx_axi_clock_converter.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_clock_converter.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source xlnx_axi_clock_converter.tcl -notrace Command: synth_design -top xlnx_axi_clock_converter -part xc7k325tffg900-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 1617759 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 2141.363 ; gain = 16.906 ; free physical = 15532 ; free virtual = 37510 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'xlnx_axi_clock_converter' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/synth/xlnx_axi_clock_converter.v:58] INFO: [Synth 8-6157] synthesizing module 'axi_clock_converter_v2_1_20_axi_clock_converter' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/hdl/axi_clock_converter_v2_1_vl_rfs.v:654] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_S_AXI_ACLK_RATIO bound to: 1 - type: integer Parameter C_M_AXI_ACLK_RATIO bound to: 2 - type: integer Parameter C_AXI_IS_ACLK_ASYNC bound to: 1 - type: integer Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer Parameter P_AXI4 bound to: 0 - type: integer Parameter P_AXI3 bound to: 1 - type: integer Parameter P_AXILITE bound to: 2 - type: integer Parameter P_LIGHT_WT bound to: 0 - type: integer Parameter P_FULLY_REG bound to: 1 - type: integer Parameter P_LUTRAM_ASYNC bound to: 12 - type: integer Parameter P_SI_LT_MI bound to: 1'b1 Parameter P_ROUNDING_OFFSET bound to: 0 - type: integer Parameter P_ACLK_RATIO bound to: 2 - type: integer Parameter C_AWUSER_RIGHT bound to: 0 - type: integer Parameter C_AWUSER_WIDTH bound to: 0 - type: integer Parameter C_AWQOS_RIGHT bound to: 0 - type: integer Parameter C_AWQOS_WIDTH bound to: 4 - type: integer Parameter C_AWREGION_RIGHT bound to: 4 - type: integer Parameter C_AWREGION_WIDTH bound to: 4 - type: integer Parameter C_AWPROT_RIGHT bound to: 8 - type: integer Parameter C_AWPROT_WIDTH bound to: 3 - type: integer Parameter C_AWCACHE_RIGHT bound to: 11 - type: integer Parameter C_AWCACHE_WIDTH bound to: 4 - type: integer Parameter C_AWLOCK_RIGHT bound to: 15 - type: integer Parameter C_AWLOCK_WIDTH bound to: 1 - type: integer Parameter C_AWBURST_RIGHT bound to: 16 - type: integer Parameter C_AWBURST_WIDTH bound to: 2 - type: integer Parameter C_AWSIZE_RIGHT bound to: 18 - type: integer Parameter C_AWSIZE_WIDTH bound to: 3 - type: integer Parameter C_AWLEN_RIGHT bound to: 21 - type: integer Parameter C_AWLEN_WIDTH bound to: 8 - type: integer Parameter C_AWADDR_RIGHT bound to: 29 - type: integer Parameter C_AWADDR_WIDTH bound to: 64 - type: integer Parameter C_AWID_RIGHT bound to: 93 - type: integer Parameter C_AWID_WIDTH bound to: 5 - type: integer Parameter C_AW_WIDTH bound to: 98 - type: integer Parameter C_FIFO_AW_WIDTH bound to: 98 - type: integer Parameter C_WUSER_RIGHT bound to: 0 - type: integer Parameter C_WUSER_WIDTH bound to: 0 - type: integer Parameter C_WLAST_RIGHT bound to: 0 - type: integer Parameter C_WLAST_WIDTH bound to: 1 - type: integer Parameter C_WSTRB_RIGHT bound to: 1 - type: integer Parameter C_WSTRB_WIDTH bound to: 8 - type: integer Parameter C_WDATA_RIGHT bound to: 9 - type: integer Parameter C_WDATA_WIDTH bound to: 64 - type: integer Parameter C_WID_RIGHT bound to: 73 - type: integer Parameter C_WID_WIDTH bound to: 0 - type: integer Parameter C_W_WIDTH bound to: 73 - type: integer Parameter C_FIFO_W_WIDTH bound to: 73 - type: integer Parameter C_BUSER_RIGHT bound to: 0 - type: integer Parameter C_BUSER_WIDTH bound to: 0 - type: integer Parameter C_BRESP_RIGHT bound to: 0 - type: integer Parameter C_BRESP_WIDTH bound to: 2 - type: integer Parameter C_BID_RIGHT bound to: 2 - type: integer Parameter C_BID_WIDTH bound to: 5 - type: integer Parameter C_B_WIDTH bound to: 7 - type: integer Parameter C_FIFO_B_WIDTH bound to: 7 - type: integer Parameter C_ARUSER_RIGHT bound to: 0 - type: integer Parameter C_ARUSER_WIDTH bound to: 0 - type: integer Parameter C_ARQOS_RIGHT bound to: 0 - type: integer Parameter C_ARQOS_WIDTH bound to: 4 - type: integer Parameter C_ARREGION_RIGHT bound to: 4 - type: integer Parameter C_ARREGION_WIDTH bound to: 4 - type: integer Parameter C_ARPROT_RIGHT bound to: 8 - type: integer Parameter C_ARPROT_WIDTH bound to: 3 - type: integer Parameter C_ARCACHE_RIGHT bound to: 11 - type: integer Parameter C_ARCACHE_WIDTH bound to: 4 - type: integer Parameter C_ARLOCK_RIGHT bound to: 15 - type: integer Parameter C_ARLOCK_WIDTH bound to: 1 - type: integer Parameter C_ARBURST_RIGHT bound to: 16 - type: integer Parameter C_ARBURST_WIDTH bound to: 2 - type: integer Parameter C_ARSIZE_RIGHT bound to: 18 - type: integer Parameter C_ARSIZE_WIDTH bound to: 3 - type: integer Parameter C_ARLEN_RIGHT bound to: 21 - type: integer Parameter C_ARLEN_WIDTH bound to: 8 - type: integer Parameter C_ARADDR_RIGHT bound to: 29 - type: integer Parameter C_ARADDR_WIDTH bound to: 64 - type: integer Parameter C_ARID_RIGHT bound to: 93 - type: integer Parameter C_ARID_WIDTH bound to: 5 - type: integer Parameter C_AR_WIDTH bound to: 98 - type: integer Parameter C_FIFO_AR_WIDTH bound to: 98 - type: integer Parameter C_RUSER_RIGHT bound to: 0 - type: integer Parameter C_RUSER_WIDTH bound to: 0 - type: integer Parameter C_RLAST_RIGHT bound to: 0 - type: integer Parameter C_RLAST_WIDTH bound to: 1 - type: integer Parameter C_RRESP_RIGHT bound to: 1 - type: integer Parameter C_RRESP_WIDTH bound to: 2 - type: integer Parameter C_RDATA_RIGHT bound to: 3 - type: integer Parameter C_RDATA_WIDTH bound to: 64 - type: integer Parameter C_RID_RIGHT bound to: 67 - type: integer Parameter C_RID_WIDTH bound to: 5 - type: integer Parameter C_R_WIDTH bound to: 72 - type: integer Parameter C_FIFO_R_WIDTH bound to: 72 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (1#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (2#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single__parameterized1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single__parameterized1' (2#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (7#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6155] done synthesizing module 'axi_clock_converter_v2_1_20_axi_clock_converter' (22#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/hdl/axi_clock_converter_v2_1_vl_rfs.v:654] INFO: [Synth 8-6155] done synthesizing module 'xlnx_axi_clock_converter' (23#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/synth/xlnx_axi_clock_converter.v:58] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:20 ; elapsed = 00:00:44 . Memory (MB): peak = 2279.270 ; gain = 154.812 ; free physical = 15578 ; free virtual = 37557 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:45 . Memory (MB): peak = 2294.113 ; gain = 169.656 ; free physical = 15577 ; free virtual = 37556 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:45 . Memory (MB): peak = 2294.113 ; gain = 169.656 ; free physical = 15577 ; free virtual = 37556 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2300.051 ; gain = 0.000 ; free physical = 15569 ; free virtual = 37547 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc] for cell 'inst' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/dont_touch.xdc] Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/xlnx_axi_clock_converter_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/xlnx_axi_clock_converter_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/xlnx_axi_clock_converter_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/xlnx_axi_clock_converter_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2437.895 ; gain = 0.000 ; free physical = 15479 ; free virtual = 37458 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2437.895 ; gain = 0.000 ; free physical = 15479 ; free virtual = 37458 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:30 ; elapsed = 00:00:55 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15551 ; free virtual = 37530 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k325tffg900-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:30 ; elapsed = 00:00:55 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15551 ; free virtual = 37530 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for inst. (constraint file /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/dont_touch.xdc, line 9). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3 . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1 . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2 . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:55 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15551 ; free virtual = 37530 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:57 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15540 ; free virtual = 37520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 10 +---XORs : 2 Input 4 Bit XORs := 10 2 Input 1 Bit XORs := 110 +---Registers : 98 Bit Registers := 4 73 Bit Registers := 2 72 Bit Registers := 2 7 Bit Registers := 2 5 Bit Registers := 10 4 Bit Registers := 83 2 Bit Registers := 20 1 Bit Registers := 88 +---Muxes : 2 Input 2 Bit Muxes := 20 5 Input 2 Bit Muxes := 5 3 Input 1 Bit Muxes := 5 2 Input 1 Bit Muxes := 15 4 Input 1 Bit Muxes := 10 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 840 (col length:140) BRAMs: 890 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:59 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15528 ; free virtual = 37512 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Distributed RAM: Preliminary Mapping Report (see note below) +---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ |inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 98 | RAM32M x 17 | |inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 73 | RAM32M x 13 | |inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 7 | RAM32M x 2 | |inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 98 | RAM32M x 17 | |inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 72 | RAM32M x 12 | +---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15410 ; free virtual = 37394 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:42 ; elapsed = 00:01:09 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15401 ; free virtual = 37385 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:43 ; elapsed = 00:01:11 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15400 ; free virtual = 37384 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:47 ; elapsed = 00:01:15 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15399 ; free virtual = 37384 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:47 ; elapsed = 00:01:15 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15399 ; free virtual = 37384 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:47 ; elapsed = 00:01:15 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15400 ; free virtual = 37384 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:47 ; elapsed = 00:01:15 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15400 ; free virtual = 37384 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:47 ; elapsed = 00:01:16 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15400 ; free virtual = 37384 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:47 ; elapsed = 00:01:16 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15400 ; free virtual = 37384 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |LUT1 | 76| |2 |LUT2 | 66| |3 |LUT3 | 30| |4 |LUT4 | 65| |5 |LUT5 | 10| |6 |LUT6 | 25| |7 |RAM32M | 61| |8 |FDCE | 130| |9 |FDPE | 115| |10 |FDRE | 961| +------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:47 ; elapsed = 00:01:16 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15400 ; free virtual = 37384 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:43 ; elapsed = 00:01:12 . Memory (MB): peak = 2437.895 ; gain = 169.656 ; free physical = 15453 ; free virtual = 37437 Synthesis Optimization Complete : Time (s): cpu = 00:00:47 ; elapsed = 00:01:16 . Memory (MB): peak = 2437.895 ; gain = 313.438 ; free physical = 15453 ; free virtual = 37437 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2437.895 ; gain = 0.000 ; free physical = 15526 ; free virtual = 37510 INFO: [Netlist 29-17] Analyzing 61 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2437.895 ; gain = 0.000 ; free physical = 15466 ; free virtual = 37450 INFO: [Project 1-111] Unisim Transformation Summary: A total of 61 instances were transformed. RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 61 instances INFO: [Common 17-83] Releasing license: Synthesis 28 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:01 ; elapsed = 00:01:27 . Memory (MB): peak = 2437.895 ; gain = 321.441 ; free physical = 15608 ; free virtual = 37592 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/xlnx_axi_clock_converter.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_clock_converter, cache-ID = 27a85cd7e3665ee2 INFO: [Coretcl 2-1174] Renamed 101 cell refs. INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/xlnx_axi_clock_converter.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_clock_converter_utilization_synth.rpt -pb xlnx_axi_clock_converter_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:37:56 2023... [Tue Oct 10 08:38:07 2023] xlnx_axi_clock_converter_synth_1 finished wait_on_run: Time (s): cpu = 00:01:24 ; elapsed = 00:01:59 . Memory (MB): peak = 2165.902 ; gain = 0.000 ; free physical = 16493 ; free virtual = 38475 INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:38:07 2023... #vivado -mode batch -source tcl/run.tcl make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter' mkdir -p work-fpga Generating xlnx_axi_dwidth_converter.xci make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter' rm -rf ip/* mkdir -p ip rm -rf xlnx_axi_dwidth_converter.* rm -rf component.xml rm -rf vivado*.jou rm -rf vivado*.log rm -rf vivado*.str rm -rf xgui rm -rf .Xil make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter' make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter' vivado -mode batch -source tcl/run.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source tcl/run.tcl # set partNumber $::env(XILINX_PART) # set boardName $::env(XILINX_BOARD) # set ipName xlnx_axi_dwidth_converter # create_project $ipName . -force -part $partNumber # set_property board_part $boardName [current_project] # create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -module_name $ipName INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.1/data/ip'. # set_property -dict [list CONFIG.SI_DATA_WIDTH {64} CONFIG.SI_ID_WIDTH {5} CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName] # generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'xlnx_axi_dwidth_converter'... # generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'xlnx_axi_dwidth_converter'... WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter_ooc.xdc' INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'xlnx_axi_dwidth_converter'... WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'xlnx_axi_dwidth_converter'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'xlnx_axi_dwidth_converter'... # create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] # launch_run -jobs 8 ${ipName}_synth_1 [Tue Oct 10 08:38:34 2023] Launched xlnx_axi_dwidth_converter_synth_1... Run output will be captured here: /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.runs/xlnx_axi_dwidth_converter_synth_1/runme.log # wait_on_run ${ipName}_synth_1 [Tue Oct 10 08:38:34 2023] Waiting for xlnx_axi_dwidth_converter_synth_1 to finish... *** Running vivado with args -log xlnx_axi_dwidth_converter.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source xlnx_axi_dwidth_converter.tcl -notrace Command: synth_design -top xlnx_axi_dwidth_converter -part xc7k325tffg900-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 1619247 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:23 . Memory (MB): peak = 2142.359 ; gain = 17.906 ; free physical = 15543 ; free virtual = 37521 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'xlnx_axi_dwidth_converter' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/synth/xlnx_axi_dwidth_converter.v:58] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_top' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:14462] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_S_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_SUPPORTS_ID bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer Parameter C_FIFO_MODE bound to: 0 - type: integer Parameter C_S_AXI_ACLK_RATIO bound to: 1 - type: integer Parameter C_M_AXI_ACLK_RATIO bound to: 2 - type: integer Parameter C_AXI_IS_ACLK_ASYNC bound to: 0 - type: integer Parameter C_MAX_SPLIT_BEATS bound to: 256 - type: integer Parameter C_PACKING_LEVEL bound to: 1 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_RATIO bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter P_AXI4 bound to: 0 - type: integer Parameter P_AXI3 bound to: 1 - type: integer Parameter P_AXILITE bound to: 2 - type: integer Parameter P_CONVERSION bound to: 2 - type: integer Parameter P_MAX_SPLIT_BEATS bound to: 256 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_axi_downsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2380] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_S_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_SUPPORTS_ID bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer Parameter C_MAX_SPLIT_BEATS bound to: 256 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_RATIO bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter P_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter P_AXI4 bound to: 0 - type: integer Parameter P_AXI3 bound to: 1 - type: integer Parameter P_AXILITE bound to: 2 - type: integer Parameter P_MAX_SPLIT_BEATS bound to: 256 - type: integer Parameter P_MAX_SPLIT_BEATS_LOG bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_b_downsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1251] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_RESP_OKAY bound to: 2'b00 Parameter C_RESP_EXOKAY bound to: 2'b01 Parameter C_RESP_SLVERROR bound to: 2'b10 Parameter C_RESP_DECERR bound to: 2'b11 INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_b_downsizer' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1251] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_a_downsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_SUPPORTS_ID bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_CHANNEL bound to: 0 - type: integer Parameter C_MAX_SPLIT_BEATS bound to: 256 - type: integer Parameter C_MAX_SPLIT_BEATS_LOG bound to: 8 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter C_S_AXI_NATIVE_SIZE bound to: 3'b011 Parameter C_M_AXI_NATIVE_SIZE bound to: 3'b010 Parameter C_DOUBLE_LEN bound to: 40'b0000000000000000000000000000000011111111 Parameter C_FIX_BURST bound to: 2'b00 Parameter C_INCR_BURST bound to: 2'b01 Parameter C_WRAP_BURST bound to: 2'b10 Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_20_axic_fifo' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_data_fifo_v2_1_vl_rfs.v:64] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_FIFO_WIDTH bound to: 9 - type: integer Parameter C_FIFO_TYPE bound to: lut - type: string INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_20_fifo_gen' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_data_fifo_v2_1_vl_rfs.v:168] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_COMMON_CLOCK bound to: 1 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_FIFO_WIDTH bound to: 9 - type: integer Parameter C_FIFO_TYPE bound to: lut - type: string Parameter C_MEMORY_TYPE bound to: 2 - type: integer Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (2#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_20_fifo_gen' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_data_fifo_v2_1_vl_rfs.v:168] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_20_axic_fifo' (21#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_data_fifo_v2_1_vl_rfs.v:64] INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_20_axic_fifo__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_data_fifo_v2_1_vl_rfs.v:64] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_FIFO_WIDTH bound to: 26 - type: integer Parameter C_FIFO_TYPE bound to: lut - type: string INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_20_fifo_gen__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_data_fifo_v2_1_vl_rfs.v:168] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_COMMON_CLOCK bound to: 1 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_FIFO_WIDTH bound to: 26 - type: integer Parameter C_FIFO_TYPE bound to: lut - type: string Parameter C_MEMORY_TYPE bound to: 2 - type: integer Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_20_fifo_gen__parameterized0' (21#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_data_fifo_v2_1_vl_rfs.v:168] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_20_axic_fifo__parameterized0' (21#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_data_fifo_v2_1_vl_rfs.v:64] INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_a_downsizer' (22#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_w_downsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2016] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter C_DOUBLE_LEN bound to: 24'b000000000000000011111111 INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_w_downsizer' (23#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2016] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_a_downsizer__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_SUPPORTS_ID bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_CHANNEL bound to: 1 - type: integer Parameter C_MAX_SPLIT_BEATS bound to: 256 - type: integer Parameter C_MAX_SPLIT_BEATS_LOG bound to: 8 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter C_S_AXI_NATIVE_SIZE bound to: 3'b011 Parameter C_M_AXI_NATIVE_SIZE bound to: 3'b010 Parameter C_DOUBLE_LEN bound to: 40'b0000000000000000000000000000000011111111 Parameter C_FIX_BURST bound to: 2'b00 Parameter C_INCR_BURST bound to: 2'b01 Parameter C_WRAP_BURST bound to: 2'b10 Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_a_downsizer__parameterized0' (23#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_r_downsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1533] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter C_RESP_OKAY bound to: 2'b00 Parameter C_RESP_EXOKAY bound to: 2'b01 Parameter C_RESP_SLVERROR bound to: 2'b10 Parameter C_RESP_DECERR bound to: 2'b11 Parameter C_DOUBLE_LEN bound to: 24'b000000000000000011111111 INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_r_downsizer' (24#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1533] INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_axi_downsizer' (25#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2380] INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_top' (26#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:14462] INFO: [Synth 8-6155] done synthesizing module 'xlnx_axi_dwidth_converter' (27#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/synth/xlnx_axi_dwidth_converter.v:58] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:20 ; elapsed = 00:00:43 . Memory (MB): peak = 2294.234 ; gain = 169.781 ; free physical = 15568 ; free virtual = 37547 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:44 . Memory (MB): peak = 2303.141 ; gain = 178.688 ; free physical = 15567 ; free virtual = 37546 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:44 . Memory (MB): peak = 2303.141 ; gain = 178.688 ; free physical = 15567 ; free virtual = 37546 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2309.078 ; gain = 0.000 ; free physical = 15558 ; free virtual = 37537 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter_ooc.xdc] for cell 'inst' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.runs/xlnx_axi_dwidth_converter_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.runs/xlnx_axi_dwidth_converter_synth_1/dont_touch.xdc] Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2454.922 ; gain = 0.000 ; free physical = 15467 ; free virtual = 37446 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2454.922 ; gain = 0.000 ; free physical = 15467 ; free virtual = 37446 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:30 ; elapsed = 00:00:54 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15543 ; free virtual = 37523 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k325tffg900-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:30 ; elapsed = 00:00:54 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15543 ; free virtual = 37523 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for inst. (constraint file /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.runs/xlnx_axi_dwidth_converter_synth_1/dont_touch.xdc, line 9). Applied set_property DONT_TOUCH = true for inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst /\USE_WRITE.write_addr_inst /\USE_B_CHANNEL.cmd_b_queue /inst/fifo_gen_inst/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst /\USE_WRITE.write_addr_inst /cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst /\USE_READ.read_addr_inst /cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:54 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15543 ; free virtual = 37523 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:56 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15534 ; free virtual = 37514 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 2 2 Input 8 Bit Adders := 7 3 Input 8 Bit Adders := 2 2 Input 6 Bit Adders := 2 2 Input 5 Bit Adders := 6 2 Input 3 Bit Adders := 4 +---XORs : 2 Input 1 Bit XORs := 60 +---Registers : 32 Bit Registers := 10 26 Bit Registers := 4 11 Bit Registers := 2 9 Bit Registers := 2 8 Bit Registers := 13 7 Bit Registers := 2 6 Bit Registers := 2 5 Bit Registers := 18 4 Bit Registers := 9 3 Bit Registers := 10 2 Bit Registers := 14 1 Bit Registers := 62 +---Muxes : 8 Input 32 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 11 Bit Muxes := 2 2 Input 8 Bit Muxes := 11 8 Input 7 Bit Muxes := 2 8 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 6 8 Input 3 Bit Muxes := 4 2 Input 2 Bit Muxes := 26 5 Input 2 Bit Muxes := 3 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 27 4 Input 1 Bit Muxes := 7 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 840 (col length:140) BRAMs: 890 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:01:02 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15508 ; free virtual = 37493 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Distributed RAM: Preliminary Mapping Report (see note below) +------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+ |inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 9 | RAM32M x 2 | |inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 | |inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 | +------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:44 ; elapsed = 00:01:10 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15393 ; free virtual = 37378 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:50 ; elapsed = 00:01:16 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15331 ; free virtual = 37316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+ |inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 9 | RAM32M x 2 | |inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 | +------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:50 ; elapsed = 00:01:17 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15332 ; free virtual = 37317 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:54 ; elapsed = 00:01:21 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15332 ; free virtual = 37317 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:54 ; elapsed = 00:01:21 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15332 ; free virtual = 37317 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:54 ; elapsed = 00:01:21 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15332 ; free virtual = 37317 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:54 ; elapsed = 00:01:21 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15332 ; free virtual = 37317 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:54 ; elapsed = 00:01:21 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15332 ; free virtual = 37317 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:54 ; elapsed = 00:01:21 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15332 ; free virtual = 37317 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |CARRY4 | 18| |2 |LUT1 | 50| |3 |LUT2 | 81| |4 |LUT3 | 111| |5 |LUT4 | 145| |6 |LUT5 | 113| |7 |LUT6 | 278| |8 |RAM32M | 12| |9 |FDCE | 69| |10 |FDPE | 33| |11 |FDRE | 635| |12 |FDSE | 5| +------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:54 ; elapsed = 00:01:21 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15332 ; free virtual = 37317 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:51 ; elapsed = 00:01:18 . Memory (MB): peak = 2454.922 ; gain = 178.688 ; free physical = 15384 ; free virtual = 37369 Synthesis Optimization Complete : Time (s): cpu = 00:00:55 ; elapsed = 00:01:22 . Memory (MB): peak = 2454.922 ; gain = 330.469 ; free physical = 15384 ; free virtual = 37369 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2454.922 ; gain = 0.000 ; free physical = 15458 ; free virtual = 37443 INFO: [Netlist 29-17] Analyzing 30 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2454.922 ; gain = 0.000 ; free physical = 15398 ; free virtual = 37383 INFO: [Project 1-111] Unisim Transformation Summary: A total of 12 instances were transformed. RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 12 instances INFO: [Common 17-83] Releasing license: Synthesis 40 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:09 ; elapsed = 00:01:33 . Memory (MB): peak = 2454.922 ; gain = 338.473 ; free physical = 15577 ; free virtual = 37563 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.runs/xlnx_axi_dwidth_converter_synth_1/xlnx_axi_dwidth_converter.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_dwidth_converter, cache-ID = b3ebd7cb61fc9ba9 INFO: [Coretcl 2-1174] Renamed 58 cell refs. INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.runs/xlnx_axi_dwidth_converter_synth_1/xlnx_axi_dwidth_converter.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_dwidth_converter_utilization_synth.rpt -pb xlnx_axi_dwidth_converter_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:40:28 2023... [Tue Oct 10 08:40:38 2023] xlnx_axi_dwidth_converter_synth_1 finished wait_on_run: Time (s): cpu = 00:01:30 ; elapsed = 00:02:04 . Memory (MB): peak = 2164.867 ; gain = 0.000 ; free physical = 16489 ; free virtual = 38472 INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:40:38 2023... #vivado -mode batch -source tcl/run.tcl make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter' mkdir -p work-fpga Generating xlnx_axi_dwidth_converter_dm_master.xci make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master' rm -rf ip/* mkdir -p ip rm -rf xlnx_axi_dwidth_converter_dm_master.* rm -rf component.xml rm -rf vivado*.jou rm -rf vivado*.log rm -rf vivado*.str rm -rf xgui rm -rf .Xil make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master' make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master' vivado -mode batch -source tcl/run.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source tcl/run.tcl # set partNumber $::env(XILINX_PART) # set boardName $::env(XILINX_BOARD) # set ipName xlnx_axi_dwidth_converter_dm_master # create_project $ipName . -force -part $partNumber # set_property board_part $boardName [current_project] # create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -module_name $ipName INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.1/data/ip'. WARNING: [IP_Flow 19-4832] The IP name 'xlnx_axi_dwidth_converter_dm_master' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues. # set_property -dict [list CONFIG.SI_DATA_WIDTH {32} CONFIG.SI_ID_WIDTH {4} CONFIG.MI_DATA_WIDTH {64}] [get_ips $ipName] # generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'xlnx_axi_dwidth_converter_dm_master'... # generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'xlnx_axi_dwidth_converter_dm_master'... WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master_ooc.xdc' INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'xlnx_axi_dwidth_converter_dm_master'... WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'xlnx_axi_dwidth_converter_dm_master'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'xlnx_axi_dwidth_converter_dm_master'... # create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] # launch_run -jobs 8 ${ipName}_synth_1 [Tue Oct 10 08:41:06 2023] Launched xlnx_axi_dwidth_converter_dm_master_synth_1... Run output will be captured here: /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/runme.log # wait_on_run ${ipName}_synth_1 [Tue Oct 10 08:41:06 2023] Waiting for xlnx_axi_dwidth_converter_dm_master_synth_1 to finish... *** Running vivado with args -log xlnx_axi_dwidth_converter_dm_master.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_master.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source xlnx_axi_dwidth_converter_dm_master.tcl -notrace Command: synth_design -top xlnx_axi_dwidth_converter_dm_master -part xc7k325tffg900-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 1620379 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 2141.828 ; gain = 19.906 ; free physical = 15540 ; free virtual = 37520 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'xlnx_axi_dwidth_converter_dm_master' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/synth/xlnx_axi_dwidth_converter_dm_master.v:58] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_top' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:14462] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_S_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_SUPPORTS_ID bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer Parameter C_FIFO_MODE bound to: 0 - type: integer Parameter C_S_AXI_ACLK_RATIO bound to: 1 - type: integer Parameter C_M_AXI_ACLK_RATIO bound to: 2 - type: integer Parameter C_AXI_IS_ACLK_ASYNC bound to: 0 - type: integer Parameter C_MAX_SPLIT_BEATS bound to: 16 - type: integer Parameter C_PACKING_LEVEL bound to: 1 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_RATIO bound to: 0 - type: integer Parameter C_RATIO_LOG bound to: 0 - type: integer Parameter P_AXI4 bound to: 0 - type: integer Parameter P_AXI3 bound to: 1 - type: integer Parameter P_AXILITE bound to: 2 - type: integer Parameter P_CONVERSION bound to: 2 - type: integer Parameter P_MAX_SPLIT_BEATS bound to: 16 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_axi_upsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:7038] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_S_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_SUPPORTS_ID bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer Parameter C_FIFO_MODE bound to: 0 - type: integer Parameter C_S_AXI_ACLK_RATIO bound to: 1 - type: integer Parameter C_M_AXI_ACLK_RATIO bound to: 2 - type: integer Parameter C_AXI_IS_ACLK_ASYNC bound to: 0 - type: integer Parameter C_PACKING_LEVEL bound to: 1 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_RATIO bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter P_BYPASS bound to: 0 - type: integer Parameter P_LIGHTWT bound to: 7 - type: integer Parameter P_FWD_REV bound to: 1 - type: integer Parameter P_CONV_LIGHT_WT bound to: 0 - type: integer Parameter P_AXI4 bound to: 0 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter P_SI_LT_MI bound to: 1'b1 Parameter P_ACLK_RATIO bound to: 2 - type: integer Parameter P_NO_FIFO bound to: 0 - type: integer Parameter P_PKTFIFO bound to: 1 - type: integer Parameter P_PKTFIFO_CLK bound to: 2 - type: integer Parameter P_DATAFIFO bound to: 3 - type: integer Parameter P_DATAFIFO_CLK bound to: 4 - type: integer Parameter P_CLK_CONV bound to: 1'b0 Parameter C_M_AXI_AW_REGISTER bound to: 0 - type: integer Parameter C_M_AXI_W_REGISTER bound to: 1 - type: integer Parameter C_M_AXI_AR_REGISTER bound to: 0 - type: integer Parameter C_S_AXI_R_REGISTER bound to: 0 - type: integer Parameter C_M_AXI_R_REGISTER bound to: 1 - type: integer Parameter P_RID_QUEUE bound to: 1 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_w_upsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:5563] Parameter C_FAMILY bound to: rtl - type: string Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_REGISTER bound to: 1 - type: integer Parameter C_PACKING_LEVEL bound to: 1 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_RATIO bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter C_NEVER_PACK bound to: 0 - type: integer Parameter C_DEFAULT_PACK bound to: 1 - type: integer Parameter C_ALWAYS_PACK bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_w_upsizer' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:5563] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_a_upsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:3603] Parameter C_FAMILY bound to: rtl - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_SUPPORTS_ID bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_REGISTER bound to: 0 - type: integer Parameter C_AXI_CHANNEL bound to: 0 - type: integer Parameter C_PACKING_LEVEL bound to: 1 - type: integer Parameter C_FIFO_MODE bound to: 0 - type: integer Parameter C_ID_QUEUE bound to: 1 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_S_AXI_NATIVE_SIZE bound to: 3'b010 Parameter C_M_AXI_NATIVE_SIZE bound to: 3'b011 Parameter C_DOUBLE_LEN bound to: 24'b000000000000000011111111 Parameter C_FIX_BURST bound to: 2'b00 Parameter C_INCR_BURST bound to: 2'b01 Parameter C_WRAP_BURST bound to: 2'b10 Parameter C_NEVER_PACK bound to: 0 - type: integer Parameter C_DEFAULT_PACK bound to: 1 - type: integer Parameter C_ALWAYS_PACK bound to: 2 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_BURST_BYTES_LOG bound to: 6 - type: integer Parameter C_SI_UNUSED_LOG bound to: 30 - type: integer Parameter C_MI_UNUSED_LOG bound to: 29 - type: integer INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_command_fifo' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/generic_baseblocks_v2_1_vl_rfs.v:655] Parameter C_FAMILY bound to: rtl - type: string Parameter C_ENABLE_S_VALID_CARRY bound to: 0 - type: integer Parameter C_ENABLE_REGISTERED_OUTPUT bound to: 1 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_FIFO_WIDTH bound to: 4 - type: integer INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_command_fifo' (2#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/generic_baseblocks_v2_1_vl_rfs.v:655] INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_command_fifo__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/generic_baseblocks_v2_1_vl_rfs.v:655] Parameter C_FAMILY bound to: rtl - type: string Parameter C_ENABLE_S_VALID_CARRY bound to: 1 - type: integer Parameter C_ENABLE_REGISTERED_OUTPUT bound to: 1 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_FIFO_WIDTH bound to: 30 - type: integer INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_command_fifo__parameterized0' (2#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/generic_baseblocks_v2_1_vl_rfs.v:655] INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_a_upsizer' (3#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:3603] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_r_upsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:4653] Parameter C_FAMILY bound to: rtl - type: string Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_S_AXI_REGISTER bound to: 0 - type: integer Parameter C_PACKING_LEVEL bound to: 1 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_RATIO bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter C_NEVER_PACK bound to: 0 - type: integer Parameter C_DEFAULT_PACK bound to: 1 - type: integer Parameter C_ALWAYS_PACK bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_r_upsizer' (4#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:4653] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_21_axi_register_slice' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:3726] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_REG_CONFIG_AW bound to: 7 - type: integer Parameter C_REG_CONFIG_W bound to: 1 - type: integer Parameter C_REG_CONFIG_B bound to: 7 - type: integer Parameter C_REG_CONFIG_AR bound to: 7 - type: integer Parameter C_REG_CONFIG_R bound to: 1 - type: integer Parameter C_RESERVE_MODE bound to: 0 - type: integer Parameter C_NUM_SLR_CROSSINGS bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_AW bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_W bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_B bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_AR bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_R bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_AW bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_W bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_B bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_AR bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_R bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_AW bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_W bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_B bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_AR bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_R bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer Parameter P_FORWARD bound to: 0 - type: integer Parameter P_RESPONSE bound to: 1 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWID_INDEX bound to: 53 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 54 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 58 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 62 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 62 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARID_INDEX bound to: 53 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 54 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 58 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 62 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 62 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 64 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 64 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 8 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 72 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_WID_INDEX bound to: 73 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 73 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 73 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 1 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 3 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 3 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 64 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 64 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 66 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_RID_INDEX bound to: 67 - type: integer Parameter G_AXI_RID_WIDTH bound to: 1 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 68 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 68 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:60] Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AWPAYLOAD_WIDTH bound to: 62 - type: integer Parameter C_WPAYLOAD_WIDTH bound to: 73 - type: integer Parameter C_BPAYLOAD_WIDTH bound to: 3 - type: integer Parameter C_ARPAYLOAD_WIDTH bound to: 62 - type: integer Parameter C_RPAYLOAD_WIDTH bound to: 68 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWID_INDEX bound to: 53 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 54 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 58 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 62 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 62 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARID_INDEX bound to: 53 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 54 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 58 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 62 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 62 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 64 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 64 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 8 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 72 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_WID_INDEX bound to: 73 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 73 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 73 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 1 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 3 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 3 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 64 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 64 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 66 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_RID_INDEX bound to: 67 - type: integer Parameter G_AXI_RID_WIDTH bound to: 1 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 68 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 68 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (5#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:60] INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:474] Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AWPAYLOAD_WIDTH bound to: 62 - type: integer Parameter C_WPAYLOAD_WIDTH bound to: 73 - type: integer Parameter C_BPAYLOAD_WIDTH bound to: 3 - type: integer Parameter C_ARPAYLOAD_WIDTH bound to: 62 - type: integer Parameter C_RPAYLOAD_WIDTH bound to: 68 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWID_INDEX bound to: 53 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 54 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 58 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 62 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 62 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARID_INDEX bound to: 53 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 54 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 58 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 62 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 62 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 64 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 64 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 8 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 72 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_WID_INDEX bound to: 73 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 73 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 73 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 1 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 3 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 3 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 64 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 64 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 66 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_RID_INDEX bound to: 67 - type: integer Parameter G_AXI_RID_WIDTH bound to: 1 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 68 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 68 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (6#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:474] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_DATA_WIDTH bound to: 62 - type: integer Parameter C_REG_CONFIG bound to: 7 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice' (7#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_DATA_WIDTH bound to: 73 - type: integer Parameter C_REG_CONFIG bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized0' (7#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized1' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_DATA_WIDTH bound to: 3 - type: integer Parameter C_REG_CONFIG bound to: 7 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized1' (7#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized2' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_DATA_WIDTH bound to: 68 - type: integer Parameter C_REG_CONFIG bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized2' (7#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_21_axi_register_slice' (8#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:3726] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_21_axi_register_slice' is unconnected for instance 'mi_register_slice_inst' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:8475] WARNING: [Synth 8-7023] instance 'mi_register_slice_inst' of module 'axi_register_slice_v2_1_21_axi_register_slice' has 93 connections declared, but only 92 given [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:8475] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_a_upsizer__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:3603] Parameter C_FAMILY bound to: rtl - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_SUPPORTS_ID bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_REGISTER bound to: 0 - type: integer Parameter C_AXI_CHANNEL bound to: 1 - type: integer Parameter C_PACKING_LEVEL bound to: 1 - type: integer Parameter C_FIFO_MODE bound to: 0 - type: integer Parameter C_ID_QUEUE bound to: 1 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_S_AXI_NATIVE_SIZE bound to: 3'b010 Parameter C_M_AXI_NATIVE_SIZE bound to: 3'b011 Parameter C_DOUBLE_LEN bound to: 24'b000000000000000011111111 Parameter C_FIX_BURST bound to: 2'b00 Parameter C_INCR_BURST bound to: 2'b01 Parameter C_WRAP_BURST bound to: 2'b10 Parameter C_NEVER_PACK bound to: 0 - type: integer Parameter C_DEFAULT_PACK bound to: 1 - type: integer Parameter C_ALWAYS_PACK bound to: 2 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_BURST_BYTES_LOG bound to: 6 - type: integer Parameter C_SI_UNUSED_LOG bound to: 30 - type: integer Parameter C_MI_UNUSED_LOG bound to: 29 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_a_upsizer__parameterized0' (8#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:3603] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_21_axi_register_slice__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:3726] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_REG_CONFIG_AW bound to: 7 - type: integer Parameter C_REG_CONFIG_W bound to: 1 - type: integer Parameter C_REG_CONFIG_B bound to: 7 - type: integer Parameter C_REG_CONFIG_AR bound to: 7 - type: integer Parameter C_REG_CONFIG_R bound to: 1 - type: integer Parameter C_RESERVE_MODE bound to: 0 - type: integer Parameter C_NUM_SLR_CROSSINGS bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_AW bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_W bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_B bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_AR bound to: 0 - type: integer Parameter C_PIPELINES_MASTER_R bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_AW bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_W bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_B bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_AR bound to: 0 - type: integer Parameter C_PIPELINES_SLAVE_R bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_AW bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_W bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_B bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_AR bound to: 0 - type: integer Parameter C_PIPELINES_MIDDLE_R bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer Parameter P_FORWARD bound to: 0 - type: integer Parameter P_RESPONSE bound to: 1 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWID_INDEX bound to: 53 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 57 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 61 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 65 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 65 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARID_INDEX bound to: 53 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 57 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 61 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 65 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 65 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_WID_INDEX bound to: 37 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 4 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 6 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 6 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_RID_INDEX bound to: 35 - type: integer Parameter G_AXI_RID_WIDTH bound to: 4 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 39 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 39 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:60] Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AWPAYLOAD_WIDTH bound to: 65 - type: integer Parameter C_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter C_BPAYLOAD_WIDTH bound to: 6 - type: integer Parameter C_ARPAYLOAD_WIDTH bound to: 65 - type: integer Parameter C_RPAYLOAD_WIDTH bound to: 39 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWID_INDEX bound to: 53 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 57 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 61 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 65 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 65 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARID_INDEX bound to: 53 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 57 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 61 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 65 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 65 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_WID_INDEX bound to: 37 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 4 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 6 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 6 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_RID_INDEX bound to: 35 - type: integer Parameter G_AXI_RID_WIDTH bound to: 4 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 39 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 39 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (8#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:60] INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:474] Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_REGION_SIGNALS bound to: 1 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AWPAYLOAD_WIDTH bound to: 65 - type: integer Parameter C_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter C_BPAYLOAD_WIDTH bound to: 6 - type: integer Parameter C_ARPAYLOAD_WIDTH bound to: 65 - type: integer Parameter C_RPAYLOAD_WIDTH bound to: 39 - type: integer Parameter G_AXI_AWADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_AWADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_AWPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_AWPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_AWSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_AWBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_AWBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_AWCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_AWCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_AWLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_AWLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_AWLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_AWID_INDEX bound to: 53 - type: integer Parameter G_AXI_AWID_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWQOS_INDEX bound to: 57 - type: integer Parameter G_AXI_AWQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWREGION_INDEX bound to: 61 - type: integer Parameter G_AXI_AWREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_AWUSER_INDEX bound to: 65 - type: integer Parameter G_AXI_AWUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_AWPAYLOAD_WIDTH bound to: 65 - type: integer Parameter G_AXI_ARADDR_INDEX bound to: 0 - type: integer Parameter G_AXI_ARADDR_WIDTH bound to: 32 - type: integer Parameter G_AXI_ARPROT_INDEX bound to: 32 - type: integer Parameter G_AXI_ARPROT_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARSIZE_INDEX bound to: 35 - type: integer Parameter G_AXI_ARSIZE_WIDTH bound to: 3 - type: integer Parameter G_AXI_ARBURST_INDEX bound to: 38 - type: integer Parameter G_AXI_ARBURST_WIDTH bound to: 2 - type: integer Parameter G_AXI_ARCACHE_INDEX bound to: 40 - type: integer Parameter G_AXI_ARCACHE_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARLEN_INDEX bound to: 44 - type: integer Parameter G_AXI_ARLEN_WIDTH bound to: 8 - type: integer Parameter G_AXI_ARLOCK_INDEX bound to: 52 - type: integer Parameter G_AXI_ARLOCK_WIDTH bound to: 1 - type: integer Parameter G_AXI_ARID_INDEX bound to: 53 - type: integer Parameter G_AXI_ARID_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARQOS_INDEX bound to: 57 - type: integer Parameter G_AXI_ARQOS_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARREGION_INDEX bound to: 61 - type: integer Parameter G_AXI_ARREGION_WIDTH bound to: 4 - type: integer Parameter G_AXI_ARUSER_INDEX bound to: 65 - type: integer Parameter G_AXI_ARUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_ARPAYLOAD_WIDTH bound to: 65 - type: integer Parameter G_AXI_WDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_WDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_WSTRB_INDEX bound to: 32 - type: integer Parameter G_AXI_WSTRB_WIDTH bound to: 4 - type: integer Parameter G_AXI_WLAST_INDEX bound to: 36 - type: integer Parameter G_AXI_WLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_WID_INDEX bound to: 37 - type: integer Parameter G_AXI_WID_WIDTH bound to: 0 - type: integer Parameter G_AXI_WUSER_INDEX bound to: 37 - type: integer Parameter G_AXI_WUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_WPAYLOAD_WIDTH bound to: 37 - type: integer Parameter G_AXI_BRESP_INDEX bound to: 0 - type: integer Parameter G_AXI_BRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_BID_INDEX bound to: 2 - type: integer Parameter G_AXI_BID_WIDTH bound to: 4 - type: integer Parameter G_AXI_BUSER_INDEX bound to: 6 - type: integer Parameter G_AXI_BUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_BPAYLOAD_WIDTH bound to: 6 - type: integer Parameter G_AXI_RDATA_INDEX bound to: 0 - type: integer Parameter G_AXI_RDATA_WIDTH bound to: 32 - type: integer Parameter G_AXI_RRESP_INDEX bound to: 32 - type: integer Parameter G_AXI_RRESP_WIDTH bound to: 2 - type: integer Parameter G_AXI_RLAST_INDEX bound to: 34 - type: integer Parameter G_AXI_RLAST_WIDTH bound to: 1 - type: integer Parameter G_AXI_RID_INDEX bound to: 35 - type: integer Parameter G_AXI_RID_WIDTH bound to: 4 - type: integer Parameter G_AXI_RUSER_INDEX bound to: 39 - type: integer Parameter G_AXI_RUSER_WIDTH bound to: 0 - type: integer Parameter G_AXI_RPAYLOAD_WIDTH bound to: 39 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (8#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:474] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized3' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_DATA_WIDTH bound to: 65 - type: integer Parameter C_REG_CONFIG bound to: 7 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized3' (8#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized4' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_DATA_WIDTH bound to: 37 - type: integer Parameter C_REG_CONFIG bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized4' (8#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized5' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_DATA_WIDTH bound to: 6 - type: integer Parameter C_REG_CONFIG bound to: 7 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized5' (8#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized6' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_DATA_WIDTH bound to: 39 - type: integer Parameter C_REG_CONFIG bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_21_axic_register_slice__parameterized6' (8#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_21_axi_register_slice__parameterized0' (8#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:3726] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_21_axi_register_slice' is unconnected for instance 'si_register_slice_inst' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:7379] WARNING: [Synth 8-7023] instance 'si_register_slice_inst' of module 'axi_register_slice_v2_1_21_axi_register_slice' has 93 connections declared, but only 92 given [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:7379] INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_axi_upsizer' (9#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:7038] INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_top' (10#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:14462] INFO: [Synth 8-6155] done synthesizing module 'xlnx_axi_dwidth_converter_dm_master' (11#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/synth/xlnx_axi_dwidth_converter_dm_master.v:58] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:20 ; elapsed = 00:00:43 . Memory (MB): peak = 2298.672 ; gain = 176.750 ; free physical = 15572 ; free virtual = 37553 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:44 . Memory (MB): peak = 2316.484 ; gain = 194.562 ; free physical = 15571 ; free virtual = 37552 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:44 . Memory (MB): peak = 2316.484 ; gain = 194.562 ; free physical = 15571 ; free virtual = 37552 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2316.484 ; gain = 0.000 ; free physical = 15564 ; free virtual = 37545 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master_ooc.xdc] for cell 'inst' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2454.328 ; gain = 0.000 ; free physical = 15469 ; free virtual = 37450 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2454.328 ; gain = 0.000 ; free physical = 15469 ; free virtual = 37450 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:30 ; elapsed = 00:00:54 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15545 ; free virtual = 37526 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k325tffg900-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:30 ; elapsed = 00:00:54 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15545 ; free virtual = 37526 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for inst. (constraint file /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:54 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15545 ; free virtual = 37526 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:55 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15537 ; free virtual = 37519 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 8 Bit Adders := 4 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 4 2 Input 4 Bit Adders := 2 2 Input 3 Bit Adders := 4 +---Registers : 73 Bit Registers := 2 68 Bit Registers := 2 65 Bit Registers := 2 64 Bit Registers := 1 62 Bit Registers := 2 39 Bit Registers := 2 37 Bit Registers := 2 30 Bit Registers := 2 8 Bit Registers := 18 6 Bit Registers := 1 5 Bit Registers := 4 4 Bit Registers := 2 3 Bit Registers := 5 2 Bit Registers := 11 1 Bit Registers := 59 +---Muxes : 2 Input 73 Bit Muxes := 2 2 Input 68 Bit Muxes := 2 2 Input 39 Bit Muxes := 2 2 Input 37 Bit Muxes := 2 2 Input 32 Bit Muxes := 9 2 Input 8 Bit Muxes := 22 8 Input 8 Bit Muxes := 4 2 Input 3 Bit Muxes := 11 8 Input 3 Bit Muxes := 6 2 Input 2 Bit Muxes := 9 2 Input 1 Bit Muxes := 61 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 840 (col length:140) BRAMs: 890 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:01:02 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15513 ; free virtual = 37499 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:44 ; elapsed = 00:01:10 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15395 ; free virtual = 37382 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:45 ; elapsed = 00:01:11 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15393 ; free virtual = 37380 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:46 ; elapsed = 00:01:12 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15390 ; free virtual = 37377 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:49 ; elapsed = 00:01:15 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15390 ; free virtual = 37377 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:49 ; elapsed = 00:01:15 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15390 ; free virtual = 37377 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:49 ; elapsed = 00:01:16 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15390 ; free virtual = 37377 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:49 ; elapsed = 00:01:16 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15390 ; free virtual = 37377 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:49 ; elapsed = 00:01:16 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15390 ; free virtual = 37377 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:49 ; elapsed = 00:01:16 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15390 ; free virtual = 37377 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Dynamic Shift Register Report: +------------+-------------------------------+--------+------------+--------+---------+--------+--------+--------+ |Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | +------------+-------------------------------+--------+------------+--------+---------+--------+--------+--------+ |dsrl | USE_RTL_FIFO.data_srl_reg[31] | 4 | 4 | 0 | 4 | 0 | 0 | 0 | |dsrl__1 | USE_RTL_FIFO.data_srl_reg[31] | 30 | 30 | 0 | 30 | 0 | 0 | 0 | |dsrl__4 | USE_RTL_FIFO.data_srl_reg[31] | 30 | 30 | 0 | 30 | 0 | 0 | 0 | +------------+-------------------------------+--------+------------+--------+---------+--------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT1 | 5| |2 |LUT2 | 23| |3 |LUT3 | 116| |4 |LUT4 | 45| |5 |LUT5 | 146| |6 |LUT6 | 216| |7 |SRLC32E | 64| |8 |FDRE | 613| |9 |FDSE | 4| +------+--------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:49 ; elapsed = 00:01:16 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15390 ; free virtual = 37377 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:46 ; elapsed = 00:01:12 . Memory (MB): peak = 2454.328 ; gain = 194.562 ; free physical = 15441 ; free virtual = 37428 Synthesis Optimization Complete : Time (s): cpu = 00:00:50 ; elapsed = 00:01:16 . Memory (MB): peak = 2454.328 ; gain = 332.406 ; free physical = 15441 ; free virtual = 37428 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2454.328 ; gain = 0.000 ; free physical = 15512 ; free virtual = 37498 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2454.328 ; gain = 0.000 ; free physical = 15455 ; free virtual = 37442 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 58 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:03 ; elapsed = 00:01:27 . Memory (MB): peak = 2454.328 ; gain = 340.410 ; free physical = 15594 ; free virtual = 37580 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/xlnx_axi_dwidth_converter_dm_master.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_dwidth_converter_dm_master, cache-ID = 69d3e7e8796f985c INFO: [Coretcl 2-1174] Renamed 15 cell refs. INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/xlnx_axi_dwidth_converter_dm_master.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_dwidth_converter_dm_master_utilization_synth.rpt -pb xlnx_axi_dwidth_converter_dm_master_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:42:52 2023... [Tue Oct 10 08:43:03 2023] xlnx_axi_dwidth_converter_dm_master_synth_1 finished wait_on_run: Time (s): cpu = 00:01:24 ; elapsed = 00:01:57 . Memory (MB): peak = 2164.402 ; gain = 0.000 ; free physical = 16490 ; free virtual = 38474 INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:43:03 2023... #vivado -mode batch -source tcl/run.tcl make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master' mkdir -p work-fpga Generating xlnx_axi_dwidth_converter_dm_slave.xci make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave' rm -rf ip/* mkdir -p ip rm -rf xlnx_axi_dwidth_converter_dm_slave.* rm -rf component.xml rm -rf vivado*.jou rm -rf vivado*.log rm -rf vivado*.str rm -rf xgui rm -rf .Xil make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave' make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave' vivado -mode batch -source tcl/run.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source tcl/run.tcl # set partNumber $::env(XILINX_PART) # set boardName $::env(XILINX_BOARD) # set ipName xlnx_axi_dwidth_converter_dm_slave # create_project $ipName . -force -part $partNumber # set_property board_part $boardName [current_project] # create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -module_name $ipName INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.1/data/ip'. WARNING: [IP_Flow 19-4832] The IP name 'xlnx_axi_dwidth_converter_dm_slave' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues. # set_property -dict [list CONFIG.SI_DATA_WIDTH {64} CONFIG.SI_ID_WIDTH {5} CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName] # generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'xlnx_axi_dwidth_converter_dm_slave'... # generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'xlnx_axi_dwidth_converter_dm_slave'... WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_ooc.xdc' INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'xlnx_axi_dwidth_converter_dm_slave'... WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'xlnx_axi_dwidth_converter_dm_slave'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'xlnx_axi_dwidth_converter_dm_slave'... # create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] # launch_run -jobs 8 ${ipName}_synth_1 [Tue Oct 10 08:43:30 2023] Launched xlnx_axi_dwidth_converter_dm_slave_synth_1... Run output will be captured here: /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/runme.log # wait_on_run ${ipName}_synth_1 [Tue Oct 10 08:43:30 2023] Waiting for xlnx_axi_dwidth_converter_dm_slave_synth_1 to finish... *** Running vivado with args -log xlnx_axi_dwidth_converter_dm_slave.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_slave.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source xlnx_axi_dwidth_converter_dm_slave.tcl -notrace Command: synth_design -top xlnx_axi_dwidth_converter_dm_slave -part xc7k325tffg900-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 1621494 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:22 . Memory (MB): peak = 2142.328 ; gain = 17.906 ; free physical = 15543 ; free virtual = 37522 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'xlnx_axi_dwidth_converter_dm_slave' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/synth/xlnx_axi_dwidth_converter_dm_slave.v:58] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_top' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:14462] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_S_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_SUPPORTS_ID bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer Parameter C_FIFO_MODE bound to: 0 - type: integer Parameter C_S_AXI_ACLK_RATIO bound to: 1 - type: integer Parameter C_M_AXI_ACLK_RATIO bound to: 2 - type: integer Parameter C_AXI_IS_ACLK_ASYNC bound to: 0 - type: integer Parameter C_MAX_SPLIT_BEATS bound to: 256 - type: integer Parameter C_PACKING_LEVEL bound to: 1 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_RATIO bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter P_AXI4 bound to: 0 - type: integer Parameter P_AXI3 bound to: 1 - type: integer Parameter P_AXILITE bound to: 2 - type: integer Parameter P_CONVERSION bound to: 2 - type: integer Parameter P_MAX_SPLIT_BEATS bound to: 256 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_axi_downsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2380] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_S_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_SUPPORTS_ID bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer Parameter C_MAX_SPLIT_BEATS bound to: 256 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_RATIO bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter P_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter P_AXI4 bound to: 0 - type: integer Parameter P_AXI3 bound to: 1 - type: integer Parameter P_AXILITE bound to: 2 - type: integer Parameter P_MAX_SPLIT_BEATS bound to: 256 - type: integer Parameter P_MAX_SPLIT_BEATS_LOG bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_b_downsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1251] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_RESP_OKAY bound to: 2'b00 Parameter C_RESP_EXOKAY bound to: 2'b01 Parameter C_RESP_SLVERROR bound to: 2'b10 Parameter C_RESP_DECERR bound to: 2'b11 INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_b_downsizer' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1251] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_a_downsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_SUPPORTS_ID bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_CHANNEL bound to: 0 - type: integer Parameter C_MAX_SPLIT_BEATS bound to: 256 - type: integer Parameter C_MAX_SPLIT_BEATS_LOG bound to: 8 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter C_S_AXI_NATIVE_SIZE bound to: 3'b011 Parameter C_M_AXI_NATIVE_SIZE bound to: 3'b010 Parameter C_DOUBLE_LEN bound to: 40'b0000000000000000000000000000000011111111 Parameter C_FIX_BURST bound to: 2'b00 Parameter C_INCR_BURST bound to: 2'b01 Parameter C_WRAP_BURST bound to: 2'b10 Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_20_axic_fifo' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:64] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_FIFO_WIDTH bound to: 9 - type: integer Parameter C_FIFO_TYPE bound to: lut - type: string INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_20_fifo_gen' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:168] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_COMMON_CLOCK bound to: 1 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_FIFO_WIDTH bound to: 9 - type: integer Parameter C_FIFO_TYPE bound to: lut - type: string Parameter C_MEMORY_TYPE bound to: 2 - type: integer Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (2#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_20_fifo_gen' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:168] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_20_axic_fifo' (21#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:64] INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_20_axic_fifo__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:64] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_FIFO_WIDTH bound to: 26 - type: integer Parameter C_FIFO_TYPE bound to: lut - type: string INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_20_fifo_gen__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:168] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_COMMON_CLOCK bound to: 1 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 3 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_FIFO_WIDTH bound to: 26 - type: integer Parameter C_FIFO_TYPE bound to: lut - type: string Parameter C_MEMORY_TYPE bound to: 2 - type: integer Parameter C_IMPLEMENTATION_TYPE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_20_fifo_gen__parameterized0' (21#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:168] INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_20_axic_fifo__parameterized0' (21#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:64] INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_a_downsizer' (22#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_w_downsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2016] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter C_DOUBLE_LEN bound to: 24'b000000000000000011111111 INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_w_downsizer' (23#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2016] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_a_downsizer__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_PROTOCOL bound to: 0 - type: integer Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_SUPPORTS_ID bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_AXI_CHANNEL bound to: 1 - type: integer Parameter C_MAX_SPLIT_BEATS bound to: 256 - type: integer Parameter C_MAX_SPLIT_BEATS_LOG bound to: 8 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter C_S_AXI_NATIVE_SIZE bound to: 3'b011 Parameter C_M_AXI_NATIVE_SIZE bound to: 3'b010 Parameter C_DOUBLE_LEN bound to: 40'b0000000000000000000000000000000011111111 Parameter C_FIX_BURST bound to: 2'b00 Parameter C_INCR_BURST bound to: 2'b01 Parameter C_WRAP_BURST bound to: 2'b10 Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_a_downsizer__parameterized0' (23#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64] INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_21_r_downsizer' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1533] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 2 - type: integer Parameter C_RATIO_LOG bound to: 1 - type: integer Parameter C_RESP_OKAY bound to: 2'b00 Parameter C_RESP_EXOKAY bound to: 2'b01 Parameter C_RESP_SLVERROR bound to: 2'b10 Parameter C_RESP_DECERR bound to: 2'b11 Parameter C_DOUBLE_LEN bound to: 24'b000000000000000011111111 INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_r_downsizer' (24#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1533] INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_axi_downsizer' (25#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2380] INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_21_top' (26#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:14462] INFO: [Synth 8-6155] done synthesizing module 'xlnx_axi_dwidth_converter_dm_slave' (27#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/synth/xlnx_axi_dwidth_converter_dm_slave.v:58] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:21 ; elapsed = 00:00:43 . Memory (MB): peak = 2294.203 ; gain = 169.781 ; free physical = 15569 ; free virtual = 37549 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:44 . Memory (MB): peak = 2309.047 ; gain = 184.625 ; free physical = 15568 ; free virtual = 37548 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:44 . Memory (MB): peak = 2309.047 ; gain = 184.625 ; free physical = 15568 ; free virtual = 37548 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2314.984 ; gain = 0.000 ; free physical = 15560 ; free virtual = 37540 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_ooc.xdc] for cell 'inst' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/dont_touch.xdc] Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2453.828 ; gain = 0.000 ; free physical = 15469 ; free virtual = 37448 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2453.828 ; gain = 0.000 ; free physical = 15469 ; free virtual = 37449 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:31 ; elapsed = 00:00:55 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15547 ; free virtual = 37527 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k325tffg900-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:31 ; elapsed = 00:00:55 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15547 ; free virtual = 37527 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for inst. (constraint file /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/dont_touch.xdc, line 9). Applied set_property DONT_TOUCH = true for inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst /\USE_WRITE.write_addr_inst /\USE_B_CHANNEL.cmd_b_queue /inst/fifo_gen_inst/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst /\USE_WRITE.write_addr_inst /cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst /\USE_READ.read_addr_inst /cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:31 ; elapsed = 00:00:56 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15547 ; free virtual = 37527 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:32 ; elapsed = 00:00:57 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15537 ; free virtual = 37518 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 2 2 Input 8 Bit Adders := 7 3 Input 8 Bit Adders := 2 2 Input 6 Bit Adders := 2 2 Input 5 Bit Adders := 6 2 Input 3 Bit Adders := 4 +---XORs : 2 Input 1 Bit XORs := 60 +---Registers : 32 Bit Registers := 10 26 Bit Registers := 4 11 Bit Registers := 2 9 Bit Registers := 2 8 Bit Registers := 13 7 Bit Registers := 2 6 Bit Registers := 2 5 Bit Registers := 18 4 Bit Registers := 9 3 Bit Registers := 10 2 Bit Registers := 14 1 Bit Registers := 62 +---Muxes : 8 Input 32 Bit Muxes := 2 2 Input 32 Bit Muxes := 7 2 Input 11 Bit Muxes := 2 2 Input 8 Bit Muxes := 11 8 Input 7 Bit Muxes := 2 8 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 6 8 Input 3 Bit Muxes := 4 2 Input 2 Bit Muxes := 26 5 Input 2 Bit Muxes := 3 3 Input 1 Bit Muxes := 3 2 Input 1 Bit Muxes := 27 4 Input 1 Bit Muxes := 7 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 840 (col length:140) BRAMs: 890 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:01:03 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15511 ; free virtual = 37496 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Distributed RAM: Preliminary Mapping Report (see note below) +------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+ |inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 9 | RAM32M x 2 | |inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 | |inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 | +------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:45 ; elapsed = 00:01:12 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15394 ; free virtual = 37380 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:51 ; elapsed = 00:01:18 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15334 ; free virtual = 37319 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+ |inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 9 | RAM32M x 2 | |inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 | +------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:52 ; elapsed = 00:01:19 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15334 ; free virtual = 37319 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:55 ; elapsed = 00:01:23 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15333 ; free virtual = 37319 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:55 ; elapsed = 00:01:23 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15333 ; free virtual = 37319 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:56 ; elapsed = 00:01:23 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15333 ; free virtual = 37319 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:56 ; elapsed = 00:01:23 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15333 ; free virtual = 37319 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:56 ; elapsed = 00:01:23 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15333 ; free virtual = 37319 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:56 ; elapsed = 00:01:23 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15333 ; free virtual = 37319 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |CARRY4 | 18| |2 |LUT1 | 50| |3 |LUT2 | 81| |4 |LUT3 | 111| |5 |LUT4 | 145| |6 |LUT5 | 113| |7 |LUT6 | 278| |8 |RAM32M | 12| |9 |FDCE | 69| |10 |FDPE | 33| |11 |FDRE | 635| |12 |FDSE | 5| +------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:56 ; elapsed = 00:01:23 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15333 ; free virtual = 37319 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:52 ; elapsed = 00:01:19 . Memory (MB): peak = 2453.828 ; gain = 184.625 ; free physical = 15385 ; free virtual = 37370 Synthesis Optimization Complete : Time (s): cpu = 00:00:56 ; elapsed = 00:01:23 . Memory (MB): peak = 2453.828 ; gain = 329.406 ; free physical = 15385 ; free virtual = 37370 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2453.828 ; gain = 0.000 ; free physical = 15458 ; free virtual = 37443 INFO: [Netlist 29-17] Analyzing 30 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2453.828 ; gain = 0.000 ; free physical = 15398 ; free virtual = 37384 INFO: [Project 1-111] Unisim Transformation Summary: A total of 12 instances were transformed. RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 12 instances INFO: [Common 17-83] Releasing license: Synthesis 40 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:10 ; elapsed = 00:01:35 . Memory (MB): peak = 2453.828 ; gain = 337.410 ; free physical = 15578 ; free virtual = 37564 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/xlnx_axi_dwidth_converter_dm_slave.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_dwidth_converter_dm_slave, cache-ID = b3ebd7cb61fc9ba9 INFO: [Coretcl 2-1174] Renamed 58 cell refs. INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/xlnx_axi_dwidth_converter_dm_slave.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_dwidth_converter_dm_slave_utilization_synth.rpt -pb xlnx_axi_dwidth_converter_dm_slave_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:45:26 2023... [Tue Oct 10 08:45:37 2023] xlnx_axi_dwidth_converter_dm_slave_synth_1 finished wait_on_run: Time (s): cpu = 00:01:32 ; elapsed = 00:02:07 . Memory (MB): peak = 2164.434 ; gain = 0.000 ; free physical = 16492 ; free virtual = 38476 INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:45:37 2023... #vivado -mode batch -source tcl/run.tcl make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave' mkdir -p work-fpga Generating xlnx_axi_quad_spi.xci make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi' rm -rf ip/* mkdir -p ip rm -rf xlnx_axi_quad_spi.* rm -rf component.xml rm -rf vivado*.jou rm -rf vivado*.log rm -rf vivado*.str rm -rf xgui rm -rf .Xil make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi' make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi' vivado -mode batch -source tcl/run.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source tcl/run.tcl # set partNumber $::env(XILINX_PART) # set boardName $::env(XILINX_BOARD) # set ipName xlnx_axi_quad_spi # create_project $ipName . -part $partNumber # set_property board_part $boardName [current_project] # create_ip -name axi_quad_spi -vendor xilinx.com -library ip -module_name $ipName INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.1/data/ip'. # set_property -dict [list CONFIG.C_USE_STARTUP {0} CONFIG.C_SCK_RATIO {4} CONFIG.C_FIFO_DEPTH {256} CONFIG.C_TYPE_OF_AXI4_INTERFACE {1} CONFIG.C_S_AXI4_ID_WIDTH {0}] [get_ips $ipName] # generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'xlnx_axi_quad_spi'... # generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'xlnx_axi_quad_spi'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'xlnx_axi_quad_spi'... INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'xlnx_axi_quad_spi'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'xlnx_axi_quad_spi'... # create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] # launch_run -jobs 8 ${ipName}_synth_1 [Tue Oct 10 08:46:04 2023] Launched xlnx_axi_quad_spi_synth_1... Run output will be captured here: /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.runs/xlnx_axi_quad_spi_synth_1/runme.log # wait_on_run ${ipName}_synth_1 [Tue Oct 10 08:46:04 2023] Waiting for xlnx_axi_quad_spi_synth_1 to finish... *** Running vivado with args -log xlnx_axi_quad_spi.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_quad_spi.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source xlnx_axi_quad_spi.tcl -notrace Command: synth_design -top xlnx_axi_quad_spi -part xc7k325tffg900-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 1622638 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:23 . Memory (MB): peak = 2142.359 ; gain = 17.906 ; free physical = 15549 ; free virtual = 37528 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'xlnx_axi_quad_spi' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/synth/xlnx_axi_quad_spi.vhd:111] Parameter Async_Clk bound to: 0 - type: integer Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_SELECT_XPM bound to: 1 - type: integer Parameter C_SUB_FAMILY bound to: kintex7 - type: string Parameter C_INSTANCE bound to: axi_quad_spi_inst - type: string Parameter C_SPI_MEM_ADDR_BITS bound to: 24 - type: integer Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 1 - type: integer Parameter C_XIP_MODE bound to: 0 - type: integer Parameter C_UC_FAMILY bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 256 - type: integer Parameter C_SCK_RATIO bound to: 4 - type: integer Parameter C_DUAL_QUAD_MODE bound to: 0 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 8 - type: integer Parameter C_NEW_SEQ_EN bound to: 1 - type: integer Parameter C_SPI_MODE bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_USE_STARTUP_EXT bound to: 0 - type: integer Parameter C_SPI_MEMORY bound to: 1 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ADDR_WIDTH bound to: 24 - type: integer Parameter C_S_AXI4_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ID_WIDTH bound to: 1 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_S_AXI4_BASEADDR bound to: 32'b11111111111111111111111111111111 Parameter C_S_AXI4_HIGHADDR bound to: 32'b00000000000000000000000000000000 Parameter C_LSB_STUP bound to: 0 - type: integer INFO: [Synth 8-3491] module 'axi_quad_spi' declared at '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36462' bound to instance 'U0' of component 'axi_quad_spi' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/synth/xlnx_axi_quad_spi.vhd:316] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36700] Parameter Async_Clk bound to: 0 - type: integer Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_SELECT_XPM bound to: 1 - type: integer Parameter C_SUB_FAMILY bound to: kintex7 - type: string Parameter C_INSTANCE bound to: axi_quad_spi_inst - type: string Parameter C_SPI_MEM_ADDR_BITS bound to: 24 - type: integer Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 1 - type: integer Parameter C_XIP_MODE bound to: 0 - type: integer Parameter C_UC_FAMILY bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 256 - type: integer Parameter C_SCK_RATIO bound to: 4 - type: integer Parameter C_DUAL_QUAD_MODE bound to: 0 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 8 - type: integer Parameter C_NEW_SEQ_EN bound to: 1 - type: integer Parameter C_SPI_MODE bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_USE_STARTUP_EXT bound to: 0 - type: integer Parameter C_SPI_MEMORY bound to: 1 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ADDR_WIDTH bound to: 24 - type: integer Parameter C_S_AXI4_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ID_WIDTH bound to: 1 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_S_AXI4_BASEADDR bound to: -1 - type: integer Parameter C_S_AXI4_HIGHADDR bound to: 0 - type: integer Parameter C_LSB_STUP bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_top' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34961] Parameter Async_Clk bound to: 0 - type: integer Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_SELECT_XPM bound to: 1 - type: integer Parameter C_SUB_FAMILY bound to: kintex7 - type: string Parameter C_INSTANCE bound to: axi_quad_spi_inst - type: string Parameter C_SPI_MEM_ADDR_BITS bound to: 24 - type: integer Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 1 - type: integer Parameter C_XIP_MODE bound to: 0 - type: integer Parameter C_UC_FAMILY bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 256 - type: integer Parameter C_SCK_RATIO bound to: 4 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 8 - type: integer Parameter C_SPI_MODE bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_SPI_MEMORY bound to: 1 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ADDR_WIDTH bound to: 24 - type: integer Parameter C_S_AXI4_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ID_WIDTH bound to: 1 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_S_AXI4_BASEADDR bound to: -1 - type: integer Parameter C_S_AXI4_HIGHADDR bound to: 0 - type: integer Parameter C_LSB_STUP bound to: 0 - type: integer Parameter C_DUAL_MODE bound to: 0 - type: integer Parameter C_NEW_SEQ_EN bound to: 1 - type: integer Parameter C_STARTUP_EXT bound to: 0 - type: integer Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'IO0_I_REG' to cell 'FD' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:35430] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'IO1_I_REG' to cell 'FD' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:35441] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'IO2_I_REG' to cell 'FD' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:35452] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'IO3_I_REG' to cell 'FD' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:35464] INFO: [Synth 8-638] synthesizing module 'axi_qspi_enhanced_mode' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:33935] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_SUB_FAMILY bound to: kintex7 - type: string Parameter C_AXI4_CLK_PS bound to: 10000 - type: integer Parameter C_EXT_SPI_CLK_PS bound to: 10000 - type: integer Parameter C_FIFO_DEPTH bound to: 256 - type: integer Parameter C_SCK_RATIO bound to: 4 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 8 - type: integer Parameter C_SPI_MODE bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_SPI_MEMORY bound to: 1 - type: integer Parameter C_S_AXI4_ADDR_WIDTH bound to: 24 - type: integer Parameter C_S_AXI4_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI4_ID_WIDTH bound to: 1 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101110000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111000 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000001000 Parameter C_S_AXI_SPI_MIN_SIZE bound to: 32'b00000000000000000000000001111100 Parameter C_SPI_MEM_ADDR_BITS bound to: 24 - type: integer INFO: [Synth 8-638] synthesizing module 'qspi_address_decoder' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:14202] Parameter C_BUS_AWIDTH bound to: 7 - type: integer Parameter C_S_AXI4_MIN_SIZE bound to: 124 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000101110000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001111000 Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000100000000000000000000000000000000100000000000000000000000000000001000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 1 - type: integer Parameter C_AW bound to: 7 - type: integer Parameter C_BAR bound to: 7'b0000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized0' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized1' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized1' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized2' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized2' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized3' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized3' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized4' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized4' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized5' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized5' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized6' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized6' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized7' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b0111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized7' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized8' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized8' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized9' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized9' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized10' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized10' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized11' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized11' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized12' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized12' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized13' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized13' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized14' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized14' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized15' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 4 - type: integer Parameter C_AW bound to: 4 - type: integer Parameter C_BAR bound to: 4'b1111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized15' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized16' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 2 - type: integer Parameter C_AW bound to: 7 - type: integer Parameter C_BAR bound to: 7'b1000000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized16' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized17' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized17' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized18' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b001 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized18' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized19' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b010 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized19' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized20' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b011 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized20' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized21' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized21' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized22' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b101 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized22' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized23' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b110 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized23' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized24' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 3 - type: integer Parameter C_AW bound to: 3 - type: integer Parameter C_BAR bound to: 3'b111 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized24' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized25' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] Parameter C_AB bound to: 2 - type: integer Parameter C_AW bound to: 7 - type: integer Parameter C_BAR bound to: 7'b1100000 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_20_pselect_f__parameterized25' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476] INFO: [Synth 8-256] done synthesizing module 'qspi_address_decoder' (2#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:14202] INFO: [Synth 8-256] done synthesizing module 'axi_qspi_enhanced_mode' (3#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:33935] INFO: [Synth 8-638] synthesizing module 'qspi_core_interface' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:19205] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_SUB_FAMILY bound to: kintex7 - type: string Parameter C_SELECT_XPM bound to: 1 - type: integer Parameter C_UC_FAMILY bound to: 0 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter Async_Clk bound to: 0 - type: integer Parameter C_NUM_CE_SIGNALS bound to: 32 - type: integer Parameter C_FIFO_DEPTH bound to: 256 - type: integer Parameter C_SCK_RATIO bound to: 4 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 8 - type: integer Parameter C_SPI_MODE bound to: 0 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_SPI_MEMORY bound to: 1 - type: integer Parameter C_SHARED_STARTUP bound to: 0 - type: integer Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 1 - type: integer Parameter C_FIFO_EXIST bound to: 1 - type: integer Parameter C_SPI_NUM_BITS_REG bound to: 8 - type: integer Parameter C_OCCUPANCY_NUM_BITS bound to: 8 - type: integer Parameter C_IP_INTR_MODE_ARRAY bound to: 448'b0000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 Parameter C_SPICR_REG_WIDTH bound to: 10 - type: integer Parameter C_SPISR_REG_WIDTH bound to: 11 - type: integer Parameter C_LSB_STUP bound to: 0 - type: integer Parameter C_DUAL_MODE bound to: 0 - type: integer Parameter C_NEW_SEQ_EN bound to: 1 - type: integer Parameter C_STARTUP_EXT bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'reset_sync_module' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:2426] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RESET_SYNC_AX2S_1' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:2455] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RESET_SYNC_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:2463] INFO: [Synth 8-256] done synthesizing module 'reset_sync_module' (4#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:2426] INFO: [Synth 8-638] synthesizing module 'cross_clk_sync_fifo_1' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:14941] Parameter C_FAMILY bound to: kintex7 - type: string Parameter Async_Clk bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 256 - type: integer Parameter C_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 8 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CMD_ERR_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15224] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CMD_ERR_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15232] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPISEL_D1_REG_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15243] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPISEL_D1_REG_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15251] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPISEL_PULSE_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15277] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPISEL_PULSE_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15285] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPISEL_PULSE_S2AX_3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15293] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'MST_N_SLV_MODE_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15306] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'MST_N_SLV_MODE_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15314] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SLV_MODF_STRB_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15339] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SLV_MODF_STRB_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15347] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SLV_MODF_STRB_S2AX_3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15355] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'MODF_STROBE_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15380] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'MODF_STROBE_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15388] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'MODF_STROBE_S2AX_3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15396] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RX_FIFO_EMPTY_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15409] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RX_FIFO_EMPTY_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15417] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'TX_FIFO_EMPTY_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15429] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'TX_FIFO_EMPTY_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15437] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'TX_EMPT_4_SPISR_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15449] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'TX_EMPT_4_SPISR_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15457] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'TX_FIFO_FULL_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15468] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'TX_FIFO_FULL_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15476] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPIXFER_DONE_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15487] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPIXFER_DONE_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15495] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RX_FIFO_RST_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15520] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RX_FIFO_RST_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15528] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RX_FIFO_FULL_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15542] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RX_FIFO_FULL_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15550] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SYNC_SPIXFER_DONE_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15573] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SYNC_SPIXFER_DONE_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15581] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SYNC_SPIXFER_DONE_S2AX_3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15589] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'DTR_UNDERRUN_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15599] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'DTR_UNDERRUN_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15607] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_0_LOOP_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15617] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_0_LOOP_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15625] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_1_SPE_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15636] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_1_SPE_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15644] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_2_MST_N_SLV_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15655] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_2_MST_N_SLV_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15663] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_3_CPOL_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15674] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_3_CPOL_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15682] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_4_CPHA_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15693] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_4_CPHA_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15701] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_5_TXFIFO_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15712] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_5_TXFIFO_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15720] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_6_RXFIFO_RST_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15731] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_6_RXFIFO_RST_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15739] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPICR_7_SS_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15750] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPICR_7_SS_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15758] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPICR_8_TR_INHIBIT_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15769] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPICR_8_TR_INHIBIT_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15777] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_9_LSB_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15788] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_9_LSB_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15796] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_BITS_7_8_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15812] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_BITS_7_8_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15820] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_BITS_7_8_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15812] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPICR_BITS_7_8_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15820] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SR_3_MODF_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15833] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SR_3_MODF_AX2S_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15841] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPISSR_AX2S_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15858] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPISSR_SYNC_AXI_2_SPI_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15866] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'DRR_OVERRUN_S2AX_1_CDC' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15891] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'DRR_OVERRUN_S2AX_2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15899] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'DRR_OVERRUN_S2AX_3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15907] INFO: [Synth 8-256] done synthesizing module 'cross_clk_sync_fifo_1' (5#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:14941] Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter READ_DATA_WIDTH bound to: 8 - type: integer Parameter READ_MODE bound to: fwft - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 1f1f - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH bound to: 8 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer INFO: [Synth 8-3491] module 'xpm_fifo_async' declared at '/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2037' bound to instance 'RX_FIFO_II' of component 'xpm_fifo_async' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:21041] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2037] Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 8 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter USE_ADV_FEATURES bound to: 1f1f - type: string Parameter READ_MODE bound to: fwft - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter READ_DATA_WIDTH bound to: 8 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter EN_ADV_FEATURE_ASYNC bound to: 16'b0001111100011111 Parameter P_FIFO_MEMORY_TYPE bound to: 0 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 1 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 8 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter USE_ADV_FEATURES bound to: 1f1f - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter READ_DATA_WIDTH bound to: 8 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 0 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter invalid bound to: 0 - type: integer Parameter stage1_valid bound to: 2 - type: integer Parameter stage2_valid bound to: 1 - type: integer Parameter both_stages_valid bound to: 3 - type: integer Parameter FIFO_MEM_TYPE bound to: 0 - type: integer Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 2048 - type: integer Parameter WR_WIDTH_LOG bound to: 3 - type: integer Parameter WR_DEPTH_LOG bound to: 8 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b0 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 8 - type: integer Parameter PE_THRESH_ADJ bound to: 8 - type: integer Parameter PF_THRESH_MIN bound to: 7 - type: integer Parameter PF_THRESH_MAX bound to: 251 - type: integer Parameter PE_THRESH_MIN bound to: 5 - type: integer Parameter PE_THRESH_MAX bound to: 251 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 2 - type: integer Parameter WIDTH_RATIO bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0001111100011111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b1 Parameter EN_WACK bound to: 1'b1 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b1 Parameter EN_DVLD bound to: 1'b1 INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1750] Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter RESET_VALUE bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn' (6#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1750] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized0' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1750] Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter RESET_VALUE bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized0' (6#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1750] INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] Parameter MEMORY_TYPE bound to: 1 - type: integer Parameter MEMORY_SIZE bound to: 2048 - type: integer Parameter MEMORY_PRIMITIVE bound to: 0 - type: integer Parameter CLOCKING_MODE bound to: 1 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter MEMORY_INIT_FILE bound to: none - type: string Parameter MEMORY_INIT_PARAM bound to: (null) - type: string Parameter USE_MEM_INIT_MMI bound to: 0 - type: integer Parameter USE_MEM_INIT bound to: 0 - type: integer Parameter MEMORY_OPTIMIZATION bound to: true - type: string Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter AUTO_SLEEP_TIME bound to: 0 - type: integer Parameter MESSAGE_CONTROL bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter USE_EMBEDDED_CONSTRAINT bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WRITE_PROTECT bound to: 1 - type: integer Parameter WRITE_DATA_WIDTH_A bound to: 8 - type: integer Parameter READ_DATA_WIDTH_A bound to: 8 - type: integer Parameter BYTE_WRITE_WIDTH_A bound to: 8 - type: integer Parameter ADDR_WIDTH_A bound to: 8 - type: integer Parameter READ_RESET_VALUE_A bound to: 0 - type: string Parameter READ_LATENCY_A bound to: 2 - type: integer Parameter WRITE_MODE_A bound to: 2 - type: integer Parameter RST_MODE_A bound to: SYNC - type: string Parameter WRITE_DATA_WIDTH_B bound to: 8 - type: integer Parameter READ_DATA_WIDTH_B bound to: 8 - type: integer Parameter BYTE_WRITE_WIDTH_B bound to: 8 - type: integer Parameter ADDR_WIDTH_B bound to: 8 - type: integer Parameter READ_RESET_VALUE_B bound to: 0 - type: string Parameter READ_LATENCY_B bound to: 2 - type: integer Parameter WRITE_MODE_B bound to: 2 - type: integer Parameter RST_MODE_B bound to: SYNC - type: string Parameter P_MEMORY_PRIMITIVE bound to: auto - type: string Parameter P_MIN_WIDTH_DATA_A bound to: 8 - type: integer Parameter P_MIN_WIDTH_DATA_B bound to: 8 - type: integer Parameter P_MIN_WIDTH_DATA bound to: 8 - type: integer Parameter P_MIN_WIDTH_DATA_ECC bound to: 8 - type: integer Parameter P_MAX_DEPTH_DATA bound to: 256 - type: integer Parameter P_ECC_MODE bound to: no_ecc - type: string Parameter P_MEMORY_OPT bound to: yes - type: string Parameter P_WIDTH_COL_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_COL_WRITE_B bound to: 8 - type: integer Parameter P_NUM_COLS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_COLS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_A bound to: 1 - type: integer Parameter P_NUM_ROWS_WRITE_B bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_A bound to: 1 - type: integer Parameter P_NUM_ROWS_READ_B bound to: 1 - type: integer Parameter P_WIDTH_ADDR_WRITE_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_WRITE_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_A bound to: 8 - type: integer Parameter P_WIDTH_ADDR_READ_B bound to: 8 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_WRITE_B bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_A bound to: 0 - type: integer Parameter P_WIDTH_ADDR_LSB_READ_B bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_A bound to: 0 - type: integer Parameter P_ENABLE_BYTE_WRITE_B bound to: 0 - type: integer Parameter P_SDP_WRITE_MODE bound to: yes - type: string Parameter rsta_loop_iter bound to: 8 - type: integer Parameter rstb_loop_iter bound to: 8 - type: integer Parameter NUM_CHAR_LOC bound to: 0 - type: integer Parameter MAX_NUM_CHAR bound to: 0 - type: integer Parameter P_MIN_WIDTH_DATA_SHFT bound to: 8 - type: integer Parameter P_MIN_WIDTH_DATA_LDW bound to: 4 - type: integer INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:488] INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (7#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 2 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (8#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1776] Parameter REG_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec' (9#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1776] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized0' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 4 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 9 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized0' (9#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized0' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1776] Parameter REG_WIDTH bound to: 9 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized0' (9#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1776] INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] Parameter DEST_SYNC_FF bound to: 2 - type: integer Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter REG_OUTPUT bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter SIM_LOSSLESS_GRAY_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter WIDTH bound to: 9 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized1' (9#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_bit' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1798] Parameter RST_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_bit' (10#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1798] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1189] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1235] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1246] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1750] Parameter COUNTER_WIDTH bound to: 2 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized1' (10#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1750] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1514] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] Parameter DEST_SYNC_FF bound to: 2 - type: integer Parameter INIT bound to: 32'sb00000000000000000000000000000000 Parameter INIT_SYNC_FF bound to: 1 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter DEF_VAL bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (11#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst' (12#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1514] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1750] Parameter COUNTER_WIDTH bound to: 9 - type: integer Parameter RESET_VALUE bound to: 0 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (12#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1750] INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized3' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1750] Parameter COUNTER_WIDTH bound to: 8 - type: integer Parameter RESET_VALUE bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized3' (12#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1750] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (13#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async' (14#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2037] INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 1 - type: integer Parameter C_FLOP_INPUT bound to: 0 - type: integer Parameter C_VECTOR_WIDTH bound to: 1 - type: integer Parameter C_MTBF_STAGES bound to: 2 - type: integer Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:514] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:545] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:554] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:564] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:574] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:584] INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (15#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-638] synthesizing module 'counter_f' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:669] Parameter C_NUM_BITS bound to: 8 - type: integer Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'counter_f' (16#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:669] INFO: [Synth 8-638] synthesizing module 'async_fifo_fg' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_fifo_v1_0_rfs.vhd:255] Parameter C_ALLOW_2N_DEPTH bound to: 1 - type: integer Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_DATA_WIDTH bound to: 8 - type: integer Parameter C_ENABLE_RLOCS bound to: 0 - type: integer Parameter C_FIFO_DEPTH bound to: 256 - type: integer Parameter C_HAS_ALMOST_EMPTY bound to: 1 - type: integer Parameter C_HAS_ALMOST_FULL bound to: 1 - type: integer Parameter C_HAS_RD_ACK bound to: 1 - type: integer Parameter C_HAS_RD_COUNT bound to: 1 - type: integer Parameter C_HAS_RD_ERR bound to: 0 - type: integer Parameter C_HAS_WR_ACK bound to: 1 - type: integer Parameter C_HAS_WR_COUNT bound to: 1 - type: integer Parameter C_HAS_WR_ERR bound to: 0 - type: integer Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer Parameter C_RD_ACK_LOW bound to: 0 - type: integer Parameter C_RD_COUNT_WIDTH bound to: 9 - type: integer Parameter C_RD_ERR_LOW bound to: 0 - type: integer Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer Parameter C_PRELOAD_REGS bound to: 1 - type: integer Parameter C_PRELOAD_LATENCY bound to: 0 - type: integer Parameter C_USE_BLOCKMEM bound to: 0 - type: integer Parameter C_WR_ACK_LOW bound to: 0 - type: integer Parameter C_WR_COUNT_WIDTH bound to: 9 - type: integer Parameter C_WR_ERR_LOW bound to: 0 - type: integer Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer Parameter C_XPM_FIFO bound to: 1 - type: integer Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter WRITE_DATA_WIDTH bound to: 8 - type: integer Parameter READ_MODE bound to: fwft - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_DATA_WIDTH bound to: 8 - type: integer Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer INFO: [Synth 8-3491] module 'xpm_fifo_async' declared at '/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2037' bound to instance 'xpm_fifo_async_inst' of component 'xpm_fifo_async' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_fifo_v1_0_rfs.vhd:1932] INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2037] Parameter FIFO_MEMORY_TYPE bound to: auto - type: string Parameter ECC_MODE bound to: no_ecc - type: string Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 8 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_MODE bound to: fwft - type: string Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter READ_DATA_WIDTH bound to: 8 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_SYNC_STAGES bound to: 2 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter EN_ADV_FEATURE_ASYNC bound to: 16'b0001111100011111 Parameter P_FIFO_MEMORY_TYPE bound to: 0 - type: integer Parameter P_COMMON_CLOCK bound to: 0 - type: integer Parameter P_ECC_MODE bound to: 0 - type: integer Parameter P_READ_MODE bound to: 1 - type: integer Parameter P_WAKEUP_TIME bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized0' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] Parameter COMMON_CLOCK bound to: 0 - type: integer Parameter RELATED_CLOCKS bound to: 0 - type: integer Parameter FIFO_MEMORY_TYPE bound to: 0 - type: integer Parameter ECC_MODE bound to: 0 - type: integer Parameter SIM_ASSERT_CHK bound to: 0 - type: integer Parameter CASCADE_HEIGHT bound to: 0 - type: integer Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer Parameter WRITE_DATA_WIDTH bound to: 8 - type: integer Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_FULL_THRESH bound to: 10 - type: integer Parameter USE_ADV_FEATURES bound to: 1F1F - type: string Parameter READ_MODE bound to: 1 - type: integer Parameter FIFO_READ_LATENCY bound to: 0 - type: integer Parameter READ_DATA_WIDTH bound to: 8 - type: integer Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer Parameter DOUT_RESET_VALUE bound to: 0 - type: string Parameter CDC_DEST_SYNC_FF bound to: 2 - type: integer Parameter FULL_RESET_VALUE bound to: 1 - type: integer Parameter REMOVE_WR_RD_PROT_LOGIC bound to: 0 - type: integer Parameter WAKEUP_TIME bound to: 0 - type: integer Parameter VERSION bound to: 0 - type: integer Parameter invalid bound to: 0 - type: integer Parameter stage1_valid bound to: 2 - type: integer Parameter stage2_valid bound to: 1 - type: integer Parameter both_stages_valid bound to: 3 - type: integer Parameter FIFO_MEM_TYPE bound to: 0 - type: integer Parameter RD_MODE bound to: 1 - type: integer Parameter ENABLE_ECC bound to: 0 - type: integer Parameter FIFO_READ_DEPTH bound to: 256 - type: integer Parameter FIFO_SIZE bound to: 2048 - type: integer Parameter WR_WIDTH_LOG bound to: 3 - type: integer Parameter WR_DEPTH_LOG bound to: 8 - type: integer Parameter WR_PNTR_WIDTH bound to: 8 - type: integer Parameter RD_PNTR_WIDTH bound to: 8 - type: integer Parameter FULL_RST_VAL bound to: 1'b1 Parameter WR_RD_RATIO bound to: 0 - type: integer Parameter PF_THRESH_ADJ bound to: 8 - type: integer Parameter PE_THRESH_ADJ bound to: 8 - type: integer Parameter PF_THRESH_MIN bound to: 7 - type: integer Parameter PF_THRESH_MAX bound to: 251 - type: integer Parameter PE_THRESH_MIN bound to: 5 - type: integer Parameter PE_THRESH_MAX bound to: 251 - type: integer Parameter WR_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_DC_WIDTH_EXT bound to: 9 - type: integer Parameter RD_LATENCY bound to: 2 - type: integer Parameter WIDTH_RATIO bound to: 1 - type: integer Parameter EN_ADV_FEATURE bound to: 16'b0001111100011111 Parameter EN_OF bound to: 1'b1 Parameter EN_PF bound to: 1'b1 Parameter EN_WDC bound to: 1'b1 Parameter EN_AF bound to: 1'b1 Parameter EN_WACK bound to: 1'b1 Parameter FG_EQ_ASYM_DOUT bound to: 1'b0 Parameter EN_UF bound to: 1'b1 Parameter EN_PE bound to: 1'b1 Parameter EN_RDC bound to: 1'b1 Parameter EN_AE bound to: 1'b1 Parameter EN_DVLD bound to: 1'b1 INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1189] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1235] INFO: [Synth 8-226] default block is never used [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1246] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized0' (16#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56] INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized1' (16#1) [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2037] INFO: [Synth 8-256] done synthesizing module 'async_fifo_fg' (17#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_fifo_v1_0_rfs.vhd:255] INFO: [Synth 8-638] synthesizing module 'qspi_fifo_ifmodule' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:13465] Parameter C_NUM_TRANSFER_BITS bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'qspi_fifo_ifmodule' (18#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:13465] INFO: [Synth 8-638] synthesizing module 'qspi_occupancy_reg' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:3647] Parameter C_OCCUPANCY_NUM_BITS bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'qspi_occupancy_reg' (19#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:3647] INFO: [Synth 8-638] synthesizing module 'qspi_mode_0_module' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:8775] Parameter C_SCK_RATIO bound to: 4 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_NUM_TRANSFER_BITS bound to: 8 - type: integer Parameter C_USE_STARTUP bound to: 0 - type: integer Parameter C_SPICR_REG_WIDTH bound to: 10 - type: integer Parameter C_SUB_FAMILY bound to: kintex7 - type: string Parameter C_FIFO_EXIST bound to: 1 - type: integer Parameter C_DUAL_MODE bound to: 0 - type: integer Parameter C_STARTUP_EXT bound to: 0 - type: integer Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'MST_TRANS_INHIBIT_D1_I' to cell 'FD' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9350] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPI_TRISTATE_CONTROL_II' to cell 'FD' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9378] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPI_TRISTATE_CONTROL_III' to cell 'FD' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9390] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPI_TRISTATE_CONTROL_IV' to cell 'FD' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9402] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPI_TRISTATE_CONTROL_V' to cell 'FD' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9426] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'SPISEL_REG' to cell 'FD' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9505] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SCK_I_REG' to cell 'FD' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9588] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SCK_O_EQ_4_FDRE_INST' to cell 'FDRE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:10833] INFO: [Synth 8-256] done synthesizing module 'qspi_mode_0_module' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:8775] INFO: [Synth 8-638] synthesizing module 'qspi_cntrl_reg' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:13820] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_SPI_NUM_BITS_REG bound to: 8 - type: integer Parameter C_SPICR_REG_WIDTH bound to: 10 - type: integer Parameter C_SPI_MODE bound to: 0 - type: integer Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPI_TRISTATE_CONTROL_I' to cell 'FDRE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:14027] Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'SPI_TRISTATE_CONTROL_I' to cell 'FDRE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:14027] INFO: [Synth 8-256] done synthesizing module 'qspi_cntrl_reg' (21#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:13820] INFO: [Synth 8-638] synthesizing module 'qspi_status_slave_sel_reg' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:2658] Parameter C_SPI_NUM_BITS_REG bound to: 8 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_NUM_SS_BITS bound to: 1 - type: integer Parameter C_SPISR_REG_WIDTH bound to: 11 - type: integer INFO: [Synth 8-256] done synthesizing module 'qspi_status_slave_sel_reg' (22#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:2658] INFO: [Synth 8-638] synthesizing module 'soft_reset' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:874] Parameter C_SIPIF_DWIDTH bound to: 32 - type: integer Parameter C_RESET_WIDTH bound to: 16 - type: integer Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005] INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_CE_INVERTED bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 INFO: [Synth 8-256] done synthesizing module 'soft_reset' (23#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:874] INFO: [Synth 8-638] synthesizing module 'interrupt_control' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/interrupt_control_v3_1_vh_rfs.vhd:259] Parameter C_NUM_CE bound to: 16 - type: integer Parameter C_NUM_IPIF_IRPT_SRC bound to: 1 - type: integer Parameter C_IP_INTR_MODE_ARRAY bound to: 448'b0000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011000000000000000000000000000000110000000000000000000000000000001100000000000000000000000000000011 Parameter C_INCLUDE_DEV_PENCODER bound to: 0 - type: bool Parameter C_INCLUDE_DEV_ISC bound to: 0 - type: bool Parameter C_IPIF_DWIDTH bound to: 32 - type: integer INFO: [Synth 8-256] done synthesizing module 'interrupt_control' (24#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/interrupt_control_v3_1_vh_rfs.vhd:259] INFO: [Synth 8-256] done synthesizing module 'qspi_core_interface' (25#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:19205] INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_top' (26#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34961] INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi' (27#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36700] INFO: [Synth 8-256] done synthesizing module 'xlnx_axi_quad_spi' (28#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/synth/xlnx_axi_quad_spi.vhd:111] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:23 ; elapsed = 00:00:46 . Memory (MB): peak = 2310.266 ; gain = 185.812 ; free physical = 15560 ; free virtual = 37540 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:47 . Memory (MB): peak = 2325.109 ; gain = 200.656 ; free physical = 15560 ; free virtual = 37540 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:24 ; elapsed = 00:00:47 . Memory (MB): peak = 2325.109 ; gain = 200.656 ; free physical = 15560 ; free virtual = 37540 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2331.047 ; gain = 0.000 ; free physical = 15553 ; free virtual = 37533 INFO: [Netlist 29-17] Analyzing 107 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_ooc.xdc] for cell 'U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_ooc.xdc] for cell 'U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_board.xdc] for cell 'U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_board.xdc] for cell 'U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xdc] for cell 'U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xdc] for cell 'U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.runs/xlnx_axi_quad_spi_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.runs/xlnx_axi_quad_spi_synth_1/dont_touch.xdc] Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_clocks.xdc] for cell 'U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_clocks.xdc] for cell 'U0' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/xlnx_axi_quad_spi_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/xlnx_axi_quad_spi_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/xlnx_axi_quad_spi_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/xlnx_axi_quad_spi_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2457.891 ; gain = 0.000 ; free physical = 15465 ; free virtual = 37445 INFO: [Project 1-111] Unisim Transformation Summary: A total of 107 instances were transformed. FD => FDRE: 11 instances FDR => FDRE: 79 instances FDRSE => FDRSE (FDRE, LUT4, VCC): 17 instances Constraint Validation Runtime : Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2457.891 ; gain = 0.000 ; free physical = 15465 ; free virtual = 37446 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:33 ; elapsed = 00:00:59 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15541 ; free virtual = 37522 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k325tffg900-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:33 ; elapsed = 00:00:59 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15541 ; free virtual = 37522 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for U0. (constraint file /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.runs/xlnx_axi_quad_spi_synth_1/dont_touch.xdc, line 9). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II . (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst . (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:59 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15541 ; free virtual = 37522 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'axi_full_sm_ps_reg' in module 'axi_qspi_enhanced_mode' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg' in module 'qspi_mode_0_module' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00000001 | 0000 axi_rd | 00000010 | 0010 axi_single_rd | 00000100 | 0001 rd_last | 00001000 | 1010 axi_wr | 00010000 | 0100 axi_single_wr | 00100000 | 0011 wr_resp_1 | 01000000 | 0111 wr_resp_2 | 10000000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'axi_full_sm_ps_reg' using encoding 'one-hot' in module 'axi_qspi_enhanced_mode' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__1' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 00 | 00 iSTATE0 | 01 | 10 iSTATE1 | 10 | 11 iSTATE2 | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__1' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * WRST_IDLE | 00001 | 000 WRST_IN | 00010 | 010 WRST_OUT | 00100 | 111 WRST_EXIT | 01000 | 110 WRST_GO2IDLE | 10000 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst' INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 00 | 00 iSTATE0 | 01 | 10 iSTATE1 | 10 | 11 iSTATE2 | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- invalid | 00 | 00 stage1_valid | 01 | 10 both_stages_valid | 10 | 11 stage2_valid | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 transfer_okay | 01 | 01 temp_transfer_okay | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg' using encoding 'sequential' in module 'qspi_mode_0_module' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:36 ; elapsed = 00:01:02 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15533 ; free virtual = 37515 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 4 Input 9 Bit Adders := 6 2 Input 9 Bit Adders := 4 3 Input 9 Bit Adders := 4 2 Input 8 Bit Adders := 3 4 Input 8 Bit Adders := 10 3 Input 8 Bit Adders := 2 2 Input 5 Bit Adders := 1 4 Input 2 Bit Adders := 2 2 Input 1 Bit Adders := 1 +---XORs : 2 Input 9 Bit XORs := 4 2 Input 8 Bit XORs := 4 2 Input 1 Bit XORs := 90 +---Registers : 32 Bit Registers := 1 14 Bit Registers := 1 9 Bit Registers := 32 8 Bit Registers := 40 5 Bit Registers := 1 4 Bit Registers := 1 2 Bit Registers := 10 1 Bit Registers := 191 +---RAMs : 2K Bit (256 X 8 bit) RAMs := 2 +---Muxes : 2 Input 32 Bit Muxes := 3 3 Input 9 Bit Muxes := 2 2 Input 9 Bit Muxes := 2 2 Input 8 Bit Muxes := 24 8 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 1 6 Input 5 Bit Muxes := 2 2 Input 5 Bit Muxes := 17 2 Input 4 Bit Muxes := 1 2 Input 2 Bit Muxes := 68 4 Input 2 Bit Muxes := 16 11 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 115 8 Input 1 Bit Muxes := 11 6 Input 1 Bit Muxes := 4 5 Input 1 Bit Muxes := 4 4 Input 1 Bit Muxes := 7 3 Input 1 Bit Muxes := 3 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 840 (col length:140) BRAMs: 890 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:40 ; elapsed = 00:01:06 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15511 ; free virtual = 37498 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Block RAM: Preliminary Mapping Report (see note below) +-----------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +-----------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 8(NO_CHANGE) | W | | 256 x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | |xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 8(NO_CHANGE) | W | | 256 x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +-----------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:48 ; elapsed = 00:01:15 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15389 ; free virtual = 37376 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:50 ; elapsed = 00:01:17 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15383 ; free virtual = 37370 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +-----------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +-----------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 8(NO_CHANGE) | W | | 256 x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | |xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 8(NO_CHANGE) | W | | 256 x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +-----------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:50 ; elapsed = 00:01:19 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15381 ; free virtual = 37368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:54 ; elapsed = 00:01:23 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15381 ; free virtual = 37368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:54 ; elapsed = 00:01:23 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15381 ; free virtual = 37368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:54 ; elapsed = 00:01:23 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15381 ; free virtual = 37368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:54 ; elapsed = 00:01:23 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15381 ; free virtual = 37368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:54 ; elapsed = 00:01:23 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15382 ; free virtual = 37369 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:54 ; elapsed = 00:01:23 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15382 ; free virtual = 37369 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |CARRY4 | 22| |2 |LUT1 | 29| |3 |LUT2 | 217| |4 |LUT3 | 85| |5 |LUT4 | 135| |6 |LUT5 | 155| |7 |LUT6 | 228| |8 |RAMB18E1 | 2| |9 |FD | 8| |10 |FDR | 53| |11 |FDRE | 768| |12 |FDSE | 33| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:54 ; elapsed = 00:01:23 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15382 ; free virtual = 37369 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:51 ; elapsed = 00:01:19 . Memory (MB): peak = 2457.891 ; gain = 200.656 ; free physical = 15435 ; free virtual = 37422 Synthesis Optimization Complete : Time (s): cpu = 00:00:55 ; elapsed = 00:01:23 . Memory (MB): peak = 2457.891 ; gain = 333.438 ; free physical = 15435 ; free virtual = 37422 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2457.891 ; gain = 0.000 ; free physical = 15509 ; free virtual = 37496 INFO: [Netlist 29-17] Analyzing 85 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Constraints 18-5572] Instance U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_OF_4_GENERATE.SCK_O_EQ_4_NO_STARTUP_USED.SCK_O_EQ_4_FDRE_INST has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2457.891 ; gain = 0.000 ; free physical = 15447 ; free virtual = 37434 INFO: [Project 1-111] Unisim Transformation Summary: A total of 61 instances were transformed. FD => FDRE: 8 instances FDR => FDRE: 53 instances INFO: [Common 17-83] Releasing license: Synthesis 283 Infos, 9 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:08 ; elapsed = 00:01:34 . Memory (MB): peak = 2457.891 ; gain = 341.441 ; free physical = 15590 ; free virtual = 37577 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.runs/xlnx_axi_quad_spi_synth_1/xlnx_axi_quad_spi.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_quad_spi, cache-ID = 0dcff9e460576170 INFO: [Coretcl 2-1174] Renamed 61 cell refs. WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.runs/xlnx_axi_quad_spi_synth_1/xlnx_axi_quad_spi.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_quad_spi_utilization_synth.rpt -pb xlnx_axi_quad_spi_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:47:59 2023... [Tue Oct 10 08:48:10 2023] xlnx_axi_quad_spi_synth_1 finished wait_on_run: Time (s): cpu = 00:01:30 ; elapsed = 00:02:06 . Memory (MB): peak = 2167.371 ; gain = 0.000 ; free physical = 16489 ; free virtual = 38473 INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:48:10 2023... #vivado -mode batch -source tcl/run.tcl make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi' mkdir -p work-fpga Generating xlnx_axi_gpio.xci make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio' rm -rf ip/* mkdir -p ip rm -rf xlnx_axi_gpio.* rm -rf component.xml rm -rf vivado*.jou rm -rf vivado*.log rm -rf vivado*.str rm -rf xgui rm -rf .Xil make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio' make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio' vivado -mode batch -source tcl/run.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source tcl/run.tcl # set partNumber $::env(XILINX_PART) # set boardName $::env(XILINX_BOARD) # set ipName xlnx_axi_gpio # create_project $ipName . -force -part $partNumber # set_property board_part $boardName [current_project] # create_ip -name axi_gpio -vendor xilinx.com -library ip -module_name $ipName INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.1/data/ip'. # set_property -dict [list CONFIG.C_GPIO_WIDTH {8} CONFIG.C_GPIO2_WIDTH {8} CONFIG.C_IS_DUAL {1} CONFIG.C_ALL_INPUTS_2 {1} CONFIG.C_INTERRUPT_PRESENT {0}] [get_ips $ipName] # generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'xlnx_axi_gpio'... # generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'xlnx_axi_gpio'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'xlnx_axi_gpio'... INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'xlnx_axi_gpio'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'xlnx_axi_gpio'... # create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] # launch_run -jobs 8 ${ipName}_synth_1 [Tue Oct 10 08:48:36 2023] Launched xlnx_axi_gpio_synth_1... Run output will be captured here: /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/runme.log # wait_on_run ${ipName}_synth_1 [Tue Oct 10 08:48:36 2023] Waiting for xlnx_axi_gpio_synth_1 to finish... *** Running vivado with args -log xlnx_axi_gpio.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_gpio.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source xlnx_axi_gpio.tcl -notrace Command: synth_design -top xlnx_axi_gpio -part xc7k325tffg900-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 1623804 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2140.359 ; gain = 18.906 ; free physical = 15516 ; free virtual = 37499 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'xlnx_axi_gpio' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/synth/xlnx_axi_gpio.vhd:87] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_GPIO_WIDTH bound to: 8 - type: integer Parameter C_GPIO2_WIDTH bound to: 8 - type: integer Parameter C_ALL_INPUTS bound to: 0 - type: integer Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer Parameter C_ALL_OUTPUTS bound to: 0 - type: integer Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer Parameter C_DOUT_DEFAULT bound to: 32'b00000000000000000000000000000000 Parameter C_TRI_DEFAULT bound to: 32'b11111111111111111111111111111111 Parameter C_IS_DUAL bound to: 1 - type: integer Parameter C_DOUT_DEFAULT_2 bound to: 32'b00000000000000000000000000000000 Parameter C_TRI_DEFAULT_2 bound to: 32'b11111111111111111111111111111111 INFO: [Synth 8-3491] module 'axi_gpio' declared at '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:1265' bound to instance 'U0' of component 'axi_gpio' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/synth/xlnx_axi_gpio.vhd:175] INFO: [Synth 8-638] synthesizing module 'axi_gpio' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351] Parameter C_FAMILY bound to: kintex7 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_GPIO_WIDTH bound to: 8 - type: integer Parameter C_GPIO2_WIDTH bound to: 8 - type: integer Parameter C_ALL_INPUTS bound to: 0 - type: integer Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer Parameter C_ALL_OUTPUTS bound to: 0 - type: integer Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer Parameter C_DOUT_DEFAULT bound to: 0 - type: integer Parameter C_TRI_DEFAULT bound to: -1 - type: integer Parameter C_IS_DUAL bound to: 1 - type: integer Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111 Parameter C_USE_WSTRB bound to: 0 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 Parameter C_FAMILY bound to: kintex7 - type: string INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer Parameter C_USE_WSTRB bound to: 0 - type: integer Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer Parameter C_FAMILY bound to: kintex7 - type: string INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] Parameter C_BUS_AWIDTH bound to: 9 - type: integer Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-638] synthesizing module 'pselect_f' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 2 - type: integer Parameter C_AW bound to: 2 - type: integer Parameter C_BAR bound to: 2'b00 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'pselect_f' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 2 - type: integer Parameter C_AW bound to: 2 - type: integer Parameter C_BAR bound to: 2'b01 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 2 - type: integer Parameter C_AW bound to: 2 - type: integer Parameter C_BAR bound to: 2'b10 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] Parameter C_AB bound to: 2 - type: integer Parameter C_AW bound to: 2 - type: integer Parameter C_BAR bound to: 2'b11 Parameter C_FAMILY bound to: nofamily - type: string INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (1#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534] INFO: [Synth 8-256] done synthesizing module 'address_decoder' (2#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550] INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (3#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341] INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (4#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948] INFO: [Synth 8-638] synthesizing module 'GPIO_Core' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:178] Parameter C_DW bound to: 32 - type: integer Parameter C_AW bound to: 9 - type: integer Parameter C_GPIO_WIDTH bound to: 8 - type: integer Parameter C_GPIO2_WIDTH bound to: 8 - type: integer Parameter C_MAX_GPIO_WIDTH bound to: 8 - type: integer Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer Parameter C_DOUT_DEFAULT bound to: 0 - type: integer Parameter C_TRI_DEFAULT bound to: -1 - type: integer Parameter C_IS_DUAL bound to: 1 - type: integer Parameter C_ALL_OUTPUTS bound to: 0 - type: integer Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer Parameter C_ALL_INPUTS bound to: 0 - type: integer Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer Parameter C_FAMILY bound to: kintex7 - type: string INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:835] INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter C_CDC_TYPE bound to: 1 - type: integer Parameter C_RESET_STATE bound to: 0 - type: integer Parameter C_SINGLE_BIT bound to: 0 - type: integer Parameter C_FLOP_INPUT bound to: 0 - type: integer Parameter C_VECTOR_WIDTH bound to: 8 - type: integer Parameter C_MTBF_STAGES bound to: 4 - type: integer Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837] INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (5#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-256] done synthesizing module 'GPIO_Core' (6#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:178] INFO: [Synth 8-256] done synthesizing module 'axi_gpio' (7#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351] INFO: [Synth 8-256] done synthesizing module 'xlnx_axi_gpio' (8#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/synth/xlnx_axi_gpio.vhd:87] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2187.297 ; gain = 65.844 ; free physical = 15585 ; free virtual = 37569 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2203.141 ; gain = 81.688 ; free physical = 15582 ; free virtual = 37566 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2203.141 ; gain = 81.688 ; free physical = 15582 ; free virtual = 37566 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2213.047 ; gain = 0.000 ; free physical = 15574 ; free virtual = 37558 INFO: [Netlist 29-17] Analyzing 96 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_ooc.xdc] for cell 'U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_ooc.xdc] for cell 'U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc] for cell 'U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc] for cell 'U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc] for cell 'U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc] for cell 'U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2369.891 ; gain = 0.000 ; free physical = 15489 ; free virtual = 37473 INFO: [Project 1-111] Unisim Transformation Summary: A total of 96 instances were transformed. FDR => FDRE: 96 instances Constraint Validation Runtime : Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2369.891 ; gain = 0.000 ; free physical = 15489 ; free virtual = 37473 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15557 ; free virtual = 37541 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k325tffg900-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15557 ; free virtual = 37541 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for U0. (constraint file /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15557 ; free virtual = 37541 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE2 | 0001 | 00 iSTATE | 0010 | 01 iSTATE0 | 0100 | 10 iSTATE1 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15549 ; free virtual = 37534 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 9 Bit Registers := 1 8 Bit Registers := 6 4 Bit Registers := 1 2 Bit Registers := 3 1 Bit Registers := 18 +---Muxes : 2 Input 9 Bit Muxes := 1 2 Input 8 Bit Muxes := 5 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 5 7 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 2 2 Input 1 Bit Muxes := 28 4 Input 1 Bit Muxes := 3 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 840 (col length:140) BRAMs: 890 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15537 ; free virtual = 37524 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15418 ; free virtual = 37406 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15416 ; free virtual = 37404 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15416 ; free virtual = 37404 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15417 ; free virtual = 37405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15417 ; free virtual = 37405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15417 ; free virtual = 37405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15417 ; free virtual = 37405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15417 ; free virtual = 37405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15417 ; free virtual = 37405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT1 | 2| |2 |LUT2 | 9| |3 |LUT3 | 9| |4 |LUT4 | 4| |5 |LUT5 | 44| |6 |LUT6 | 16| |7 |FDR | 64| |8 |FDRE | 103| |9 |FDSE | 17| +------+-----+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15417 ; free virtual = 37405 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2369.891 ; gain = 81.688 ; free physical = 15470 ; free virtual = 37458 Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2369.891 ; gain = 248.438 ; free physical = 15470 ; free virtual = 37458 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2369.891 ; gain = 0.000 ; free physical = 15463 ; free virtual = 37451 INFO: [Netlist 29-17] Analyzing 64 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2369.891 ; gain = 0.000 ; free physical = 15482 ; free virtual = 37470 INFO: [Project 1-111] Unisim Transformation Summary: A total of 64 instances were transformed. FDR => FDRE: 64 instances INFO: [Common 17-83] Releasing license: Synthesis 91 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2369.891 ; gain = 256.441 ; free physical = 15618 ; free virtual = 37606 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_gpio, cache-ID = 2697c94b63436998 INFO: [Coretcl 2-1174] Renamed 7 cell refs. INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_gpio_utilization_synth.rpt -pb xlnx_axi_gpio_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:49:40 2023... [Tue Oct 10 08:49:51 2023] xlnx_axi_gpio_synth_1 finished wait_on_run: Time (s): cpu = 00:01:01 ; elapsed = 00:01:15 . Memory (MB): peak = 2167.367 ; gain = 0.000 ; free physical = 16492 ; free virtual = 38476 INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:49:51 2023... #vivado -mode batch -source tcl/run.tcl make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio' mkdir -p work-fpga Generating xlnx_clk_gen.xci make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen' rm -rf ip/* mkdir -p ip rm -rf xlnx_clk_gen.* rm -rf component.xml rm -rf vivado*.jou rm -rf vivado*.log rm -rf vivado*.str rm -rf xgui rm -rf .Xil make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen' make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen' vivado -mode batch -source tcl/run.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source tcl/run.tcl # set partNumber $::env(XILINX_PART) # set boardName $::env(XILINX_BOARD) # set ipName xlnx_clk_gen # create_project $ipName . -force -part $partNumber # set_property board_part $boardName [current_project] # create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.1/data/ip'. create_ip: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2180.426 ; gain = 63.918 ; free physical = 16344 ; free virtual = 38328 # set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000} \ # CONFIG.NUM_OUT_CLKS {4} \ # CONFIG.CLKOUT2_USED {true} \ # CONFIG.CLKOUT3_USED {true} \ # CONFIG.CLKOUT4_USED {true} \ # CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} \ # CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} \ # CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {125} \ # CONFIG.CLKOUT3_REQUESTED_PHASE {90.000} \ # CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {50} \ # CONFIG.CLKIN1_JITTER_PS {50.0} \ # ] [get_ips $ipName] # generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'xlnx_clk_gen'... # generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'xlnx_clk_gen'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'xlnx_clk_gen'... INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'xlnx_clk_gen'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'xlnx_clk_gen'... # create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] # launch_run -jobs 8 ${ipName}_synth_1 [Tue Oct 10 08:50:23 2023] Launched xlnx_clk_gen_synth_1... Run output will be captured here: /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.runs/xlnx_clk_gen_synth_1/runme.log # wait_on_run ${ipName}_synth_1 [Tue Oct 10 08:50:23 2023] Waiting for xlnx_clk_gen_synth_1 to finish... *** Running vivado with args -log xlnx_clk_gen.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_clk_gen.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source xlnx_clk_gen.tcl -notrace Command: synth_design -top xlnx_clk_gen -part xc7k325tffg900-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 1624738 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2141.359 ; gain = 16.906 ; free physical = 15334 ; free virtual = 37318 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'xlnx_clk_gen' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.v:73] INFO: [Synth 8-6157] synthesizing module 'xlnx_clk_gen_clk_wiz' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen_clk_wiz.v:71] INFO: [Synth 8-6157] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:32977] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-6155] done synthesizing module 'IBUF' (1#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:32977] INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:39994] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: double Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string Parameter CLKIN1_PERIOD bound to: 5.000000 - type: double Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 20.000000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT2_DIVIDE bound to: 8 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 90.000000 - type: double Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT3_DIVIDE bound to: 20 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT4_CASCADE bound to: FALSE - type: string Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string Parameter COMPENSATION bound to: ZHOLD - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PSEN_INVERTED bound to: 1'b0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.010000 - type: double Parameter REF_JITTER2 bound to: 0.010000 - type: double Parameter SS_EN bound to: FALSE - type: string Parameter SS_MODE bound to: CENTER_HIGH - type: string Parameter SS_MOD_PERIOD bound to: 10000 - type: integer Parameter STARTUP_WAIT bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (2#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:39994] INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1083] INFO: [Synth 8-6155] done synthesizing module 'BUFG' (3#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1083] INFO: [Synth 8-6155] done synthesizing module 'xlnx_clk_gen_clk_wiz' (4#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen_clk_wiz.v:71] INFO: [Synth 8-6155] done synthesizing module 'xlnx_clk_gen' (5#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.v:73] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2180.297 ; gain = 55.844 ; free physical = 15428 ; free virtual = 37413 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2198.109 ; gain = 73.656 ; free physical = 15424 ; free virtual = 37409 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 2198.109 ; gain = 73.656 ; free physical = 15424 ; free virtual = 37409 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2207.016 ; gain = 0.000 ; free physical = 15416 ; free virtual = 37401 INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen_ooc.xdc] for cell 'inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen_ooc.xdc] for cell 'inst' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen_board.xdc] for cell 'inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen_board.xdc] for cell 'inst' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc] for cell 'inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc] for cell 'inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/xlnx_clk_gen_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/xlnx_clk_gen_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Timing 38-2] Deriving generated clocks Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.runs/xlnx_clk_gen_synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.runs/xlnx_clk_gen_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2279.953 ; gain = 0.000 ; free physical = 15332 ; free virtual = 37316 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2279.953 ; gain = 0.000 ; free physical = 15332 ; free virtual = 37316 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 2279.953 ; gain = 155.500 ; free physical = 15398 ; free virtual = 37383 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k325tffg900-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:18 . Memory (MB): peak = 2279.953 ; gain = 155.500 ; free physical = 15398 ; free virtual = 37383 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for inst. (constraint file /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.runs/xlnx_clk_gen_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:19 . Memory (MB): peak = 2279.953 ; gain = 155.500 ; free physical = 15398 ; free virtual = 37383 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:19 . Memory (MB): peak = 2279.953 ; gain = 155.500 ; free physical = 15398 ; free virtual = 37383 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 840 (col length:140) BRAMs: 890 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 2279.953 ; gain = 155.500 ; free physical = 15395 ; free virtual = 37383 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2279.953 ; gain = 155.500 ; free physical = 15274 ; free virtual = 37262 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2279.953 ; gain = 155.500 ; free physical = 15274 ; free virtual = 37262 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2279.969 ; gain = 155.516 ; free physical = 15273 ; free virtual = 37261 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 2285.906 ; gain = 161.453 ; free physical = 15272 ; free virtual = 37261 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 2285.906 ; gain = 161.453 ; free physical = 15272 ; free virtual = 37261 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 2285.906 ; gain = 161.453 ; free physical = 15272 ; free virtual = 37261 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 2285.906 ; gain = 161.453 ; free physical = 15272 ; free virtual = 37261 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 2285.906 ; gain = 161.453 ; free physical = 15272 ; free virtual = 37261 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 2285.906 ; gain = 161.453 ; free physical = 15272 ; free virtual = 37261 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ |1 |BUFG | 5| |2 |MMCME2_ADV | 1| |3 |IBUF | 1| +------+-----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 2285.906 ; gain = 161.453 ; free physical = 15272 ; free virtual = 37261 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2285.906 ; gain = 79.609 ; free physical = 15326 ; free virtual = 37315 Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:32 . Memory (MB): peak = 2285.914 ; gain = 161.453 ; free physical = 15326 ; free virtual = 37315 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2285.914 ; gain = 0.000 ; free physical = 15322 ; free virtual = 37310 INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2298.781 ; gain = 0.000 ; free physical = 15340 ; free virtual = 37328 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 28 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2298.781 ; gain = 182.332 ; free physical = 15471 ; free virtual = 37459 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.runs/xlnx_clk_gen_synth_1/xlnx_clk_gen.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_clk_gen, cache-ID = 38c326d66a516d65 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.runs/xlnx_clk_gen_synth_1/xlnx_clk_gen.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file xlnx_clk_gen_utilization_synth.rpt -pb xlnx_clk_gen_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:51:25 2023... [Tue Oct 10 08:51:35 2023] xlnx_clk_gen_synth_1 finished wait_on_run: Time (s): cpu = 00:00:59 ; elapsed = 00:01:12 . Memory (MB): peak = 2188.512 ; gain = 0.000 ; free physical = 16329 ; free virtual = 38313 INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:51:35 2023... #vivado -mode batch -source tcl/run.tcl make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen' mkdir -p work-fpga Generating xlnx_mig_7_ddr3.xci make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3' rm -rf ip/* mkdir -p ip rm -rf xlnx_mig_7_ddr3.* rm -rf component.xml rm -rf vivado*.jou rm -rf vivado*.log rm -rf vivado*.str rm -rf xgui rm -rf .Xil make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3' make[2]: Entering directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3' vivado -mode batch -source tcl/run.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source tcl/run.tcl # set partNumber $::env(XILINX_PART) # set boardName $::env(XILINX_BOARD) # set boardNameShort $::env(BOARD) # set ipName xlnx_mig_7_ddr3 # create_project $ipName . -force -part $partNumber # set_property board_part $boardName [current_project] # create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.1/data/ip'. # exec cp mig_$boardNameShort.prj ./$ipName.srcs/sources_1/ip/$ipName/mig_a.prj # set_property -dict [list CONFIG.XML_INPUT_FILE {mig_a.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName] # generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'xlnx_mig_7_ddr3'... # generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'xlnx_mig_7_ddr3'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'xlnx_mig_7_ddr3'... INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'xlnx_mig_7_ddr3'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'xlnx_mig_7_ddr3'... generate_target: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2174.316 ; gain = 15.031 ; free physical = 16093 ; free virtual = 38025 # create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] # launch_run -jobs 8 ${ipName}_synth_1 [Tue Oct 10 08:52:33 2023] Launched xlnx_mig_7_ddr3_synth_1... Run output will be captured here: /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/runme.log # wait_on_run ${ipName}_synth_1 [Tue Oct 10 08:52:34 2023] Waiting for xlnx_mig_7_ddr3_synth_1 to finish... *** Running vivado with args -log xlnx_mig_7_ddr3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_mig_7_ddr3.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source xlnx_mig_7_ddr3.tcl -notrace Command: synth_design -top xlnx_mig_7_ddr3 -part xc7k325tffg900-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 1625870 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2156.332 ; gain = 31.875 ; free physical = 15087 ; free virtual = 37019 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'xlnx_mig_7_ddr3' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3.v:70] INFO: [Synth 8-6157] synthesizing module 'xlnx_mig_7_ddr3_mig' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:75] Parameter BANK_WIDTH bound to: 3 - type: integer Parameter CK_WIDTH bound to: 1 - type: integer Parameter COL_WIDTH bound to: 10 - type: integer Parameter CS_WIDTH bound to: 1 - type: integer Parameter nCS_PER_RANK bound to: 1 - type: integer Parameter CKE_WIDTH bound to: 1 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DQ_CNT_WIDTH bound to: 5 - type: integer Parameter DQ_PER_DM bound to: 8 - type: integer Parameter DM_WIDTH bound to: 4 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DRAM_WIDTH bound to: 8 - type: integer Parameter ECC bound to: OFF - type: string Parameter DATA_WIDTH bound to: 32 - type: integer Parameter ECC_TEST bound to: OFF - type: string Parameter PAYLOAD_WIDTH bound to: 32 - type: integer Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string Parameter nBANK_MACHS bound to: 4 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter ODT_WIDTH bound to: 1 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter ADDR_WIDTH bound to: 29 - type: integer Parameter USE_CS_PORT bound to: 1 - type: integer Parameter USE_DM_PORT bound to: 1 - type: integer Parameter USE_ODT_PORT bound to: 1 - type: integer Parameter IS_CLK_SHARED bound to: FALSE - type: string Parameter PHY_CONTROL_MASTER_BANK bound to: 1 - type: integer Parameter MEM_DENSITY bound to: 4Gb - type: string Parameter MEM_SPEEDGRADE bound to: 107E - type: string Parameter MEM_DEVICE_WIDTH bound to: 16 - type: integer Parameter AL bound to: 0 - type: string Parameter nAL bound to: 0 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter BURST_TYPE bound to: SEQ - type: string Parameter CL bound to: 11 - type: integer Parameter CWL bound to: 8 - type: integer Parameter OUTPUT_DRV bound to: HIGH - type: string Parameter RTT_NOM bound to: 40 - type: string Parameter RTT_WR bound to: OFF - type: string Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter REG_CTRL bound to: OFF - type: string Parameter CA_MIRROR bound to: OFF - type: string Parameter VDD_OP_VOLT bound to: 150 - type: string Parameter CLKIN_PERIOD bound to: 5000 - type: integer Parameter CLKFBOUT_MULT bound to: 8 - type: integer Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter CLKOUT0_PHASE bound to: 337.500000 - type: double Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer Parameter CLKOUT1_DIVIDE bound to: 2 - type: integer Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer Parameter CLKOUT3_DIVIDE bound to: 8 - type: integer Parameter MMCM_VCO bound to: 800 - type: integer Parameter MMCM_MULT_F bound to: 4 - type: integer Parameter MMCM_DIVCLK_DIVIDE bound to: 1 - type: integer Parameter tCKE bound to: 5000 - type: integer Parameter tFAW bound to: 35000 - type: integer Parameter tPRDI bound to: 1000000 - type: integer Parameter tRAS bound to: 34000 - type: integer Parameter tRCD bound to: 13910 - type: integer Parameter tREFI bound to: 7800000 - type: integer Parameter tRFC bound to: 260000 - type: integer Parameter tRP bound to: 13910 - type: integer Parameter tRRD bound to: 6000 - type: integer Parameter tRTP bound to: 7500 - type: integer Parameter tWTR bound to: 7500 - type: integer Parameter tZQI bound to: 128000000 - type: integer Parameter tZQCS bound to: 64 - type: integer Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string Parameter SIMULATION bound to: FALSE - type: string Parameter BYTE_LANES_B0 bound to: 4'b1111 Parameter BYTE_LANES_B1 bound to: 4'b1111 Parameter BYTE_LANES_B2 bound to: 4'b0000 Parameter BYTE_LANES_B3 bound to: 4'b0000 Parameter BYTE_LANES_B4 bound to: 4'b0000 Parameter DATA_CTL_B0 bound to: 4'b1111 Parameter DATA_CTL_B1 bound to: 4'b0000 Parameter DATA_CTL_B2 bound to: 4'b0000 Parameter DATA_CTL_B3 bound to: 4'b0000 Parameter DATA_CTL_B4 bound to: 4'b0000 Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110001111111110001011111111 Parameter PHY_1_BITLANES bound to: 48'b001111111110111111111100110000010000000000000011 Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011 Parameter ADDR_MAP bound to: 192'b000000000000000100010100000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100100101000100101000000100100111000100100110000100101011 Parameter BANK_MAP bound to: 36'b000100101010000100101001000100100100 Parameter CAS_MAP bound to: 12'b000100100010 Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011 Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010 Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 Parameter PARITY_MAP bound to: 12'b000000000000 Parameter RAS_MAP bound to: 12'b000100100011 Parameter WE_MAP bound to: 12'b000100000001 Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011 Parameter DATA0_MAP bound to: 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000 Parameter DATA1_MAP bound to: 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000 Parameter DATA2_MAP bound to: 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000 Parameter DATA3_MAP bound to: 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111 Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001 Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter SLOT_0_CONFIG bound to: 8'b00000001 Parameter SLOT_1_CONFIG bound to: 8'b00000000 Parameter IBUF_LPWR_MODE bound to: OFF - type: string Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string Parameter BANK_TYPE bound to: HP_IO - type: string Parameter DATA_IO_PRIM_TYPE bound to: HP_LP - type: string Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter USER_REFRESH bound to: OFF - type: string Parameter WRLVL bound to: ON - type: string Parameter ORDERING bound to: NORM - type: string Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 Parameter CALIB_COL_ADD bound to: 12'b000000000000 Parameter CALIB_BA_ADD bound to: 3'b000 Parameter TCQ bound to: 100 - type: integer Parameter IDELAY_ADJ bound to: ON - type: string Parameter FINE_PER_BIT bound to: ON - type: string Parameter CENTER_COMP_MODE bound to: ON - type: string Parameter PI_VAL_ADJ bound to: ON - type: string Parameter IODELAY_GRP0 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG0 - type: string Parameter IODELAY_GRP1 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter SYSCLK_TYPE bound to: DIFFERENTIAL - type: string Parameter REFCLK_TYPE bound to: USE_SYSTEM_CLOCK - type: string Parameter SYS_RST_PORT bound to: FALSE - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter CMD_PIPE_PLUS1 bound to: ON - type: string Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter CAL_WIDTH bound to: HALF - type: string Parameter STARVE_LIMIT bound to: 2 - type: integer Parameter REF_CLK_MMCM_IODELAY_CTRL bound to: TRUE - type: string Parameter REFCLK_FREQ bound to: 200.000000 - type: double Parameter DIFF_TERM_REFCLK bound to: TRUE - type: string Parameter tCK bound to: 1250 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter DIFF_TERM_SYSCLK bound to: FALSE - type: string Parameter UI_EXTRA_CLOCKS bound to: FALSE - type: string Parameter C_S_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_S_AXI_MEM_SIZE bound to: 1073741824 - type: string Parameter C_S_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_MC_nCK_PER_CLK bound to: 4 - type: integer Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000 Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000 Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_BASEADDR bound to: 0 - type: integer Parameter C_ECC_ONOFF_RESET_VALUE bound to: 1 - type: integer Parameter C_ECC_CE_COUNTER_WIDTH bound to: 8 - type: integer Parameter DEBUG_PORT bound to: OFF - type: string Parameter TEMP_MON_CONTROL bound to: INTERNAL - type: string Parameter FPGA_VOLT_TYPE bound to: N - type: string Parameter RST_ACT_LOW bound to: 1 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter ECC_WIDTH bound to: 0 - type: integer Parameter DATA_BUF_OFFSET_WIDTH bound to: 1 - type: integer Parameter MC_ERR_ADDR_WIDTH bound to: 29 - type: integer Parameter APP_DATA_WIDTH bound to: 256 - type: integer Parameter APP_MASK_WIDTH bound to: 32 - type: integer Parameter TEMP_MON_EN bound to: ON - type: string Parameter tTEMPSAMPLE bound to: 10000000 - type: integer Parameter XADC_CLK_PERIOD bound to: 5000 - type: integer Parameter SKIP_CALIB bound to: FALSE - type: string Parameter TAPSPERKCLK bound to: 56 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_tempmon' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] Parameter TCQ bound to: 100 - type: integer Parameter TEMP_MON_CONTROL bound to: INTERNAL - type: string Parameter XADC_CLK_PERIOD bound to: 5000 - type: integer Parameter tTEMPSAMPLE bound to: 10000000 - type: integer INFO: [Synth 8-6157] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:82207] Parameter INIT_40 bound to: 16'b0001000000000000 Parameter INIT_41 bound to: 16'b0010111111111111 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000100000001 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000100000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b1011010111101101 Parameter INIT_51 bound to: 16'b0101011111100100 Parameter INIT_52 bound to: 16'b1010000101000111 Parameter INIT_53 bound to: 16'b1100101000110011 Parameter INIT_54 bound to: 16'b1010100100111010 Parameter INIT_55 bound to: 16'b0101001011000110 Parameter INIT_56 bound to: 16'b1001010101010101 Parameter INIT_57 bound to: 16'b1010111001001110 Parameter INIT_58 bound to: 16'b0101100110011001 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0101000100010001 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-6155] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:82207] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_tempmon' (2#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_iodelay_ctrl' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] Parameter TCQ bound to: 100 - type: integer Parameter IODELAY_GRP0 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG0 - type: string Parameter IODELAY_GRP1 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter REFCLK_TYPE bound to: USE_SYSTEM_CLOCK - type: string Parameter SYSCLK_TYPE bound to: DIFFERENTIAL - type: string Parameter SYS_RST_PORT bound to: FALSE - type: string Parameter RST_ACT_LOW bound to: 1 - type: integer Parameter DIFF_TERM_REFCLK bound to: TRUE - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter REF_CLK_MMCM_IODELAY_CTRL bound to: TRUE - type: string Parameter RST_SYNC_NUM bound to: 15 - type: integer INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:39994] Parameter BANDWIDTH bound to: HIGH - type: string Parameter CLKFBOUT_MULT_F bound to: 6.000000 - type: double Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string Parameter CLKIN1_PERIOD bound to: 5.000000 - type: double Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 4.000000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT1_DIVIDE bound to: 3 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT4_CASCADE bound to: FALSE - type: string Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string Parameter COMPENSATION bound to: INTERNAL - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PSEN_INVERTED bound to: 1'b0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.000000 - type: double Parameter REF_JITTER2 bound to: 0.010000 - type: double Parameter SS_EN bound to: FALSE - type: string Parameter SS_MODE bound to: CENTER_HIGH - type: string Parameter SS_MOD_PERIOD bound to: 10000 - type: integer Parameter STARTUP_WAIT bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (3#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:39994] INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1083] INFO: [Synth 8-6155] done synthesizing module 'BUFG' (4#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1083] INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:35056] Parameter SIM_DEVICE bound to: 7SERIES - type: string INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (5#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:35056] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_iodelay_ctrl' (6#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_clk_ibuf' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] Parameter SYSCLK_TYPE bound to: DIFFERENTIAL - type: string Parameter DIFF_TERM_SYSCLK bound to: FALSE - type: string INFO: [Synth 8-6157] synthesizing module 'IBUFGDS' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:33458] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: FALSE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-6155] done synthesizing module 'IBUFGDS' (7#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:33458] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_clk_ibuf' (8#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_infrastructure' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] Parameter SIMULATION bound to: FALSE - type: string Parameter TCQ bound to: 100 - type: integer Parameter CLKIN_PERIOD bound to: 5000 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter SYSCLK_TYPE bound to: DIFFERENTIAL - type: string Parameter UI_EXTRA_CLOCKS bound to: FALSE - type: string Parameter CLKFBOUT_MULT bound to: 8 - type: integer Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter CLKOUT0_PHASE bound to: 337.500000 - type: double Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer Parameter CLKOUT1_DIVIDE bound to: 2 - type: integer Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer Parameter CLKOUT3_DIVIDE bound to: 8 - type: integer Parameter MMCM_VCO bound to: 800 - type: integer Parameter MMCM_MULT_F bound to: 4 - type: integer Parameter MMCM_DIVCLK_DIVIDE bound to: 1 - type: integer Parameter MMCM_CLKOUT0_EN bound to: FALSE - type: string Parameter MMCM_CLKOUT1_EN bound to: FALSE - type: string Parameter MMCM_CLKOUT2_EN bound to: FALSE - type: string Parameter MMCM_CLKOUT3_EN bound to: FALSE - type: string Parameter MMCM_CLKOUT4_EN bound to: FALSE - type: string Parameter MMCM_CLKOUT0_DIVIDE bound to: 1 - type: integer Parameter MMCM_CLKOUT1_DIVIDE bound to: 1 - type: integer Parameter MMCM_CLKOUT2_DIVIDE bound to: 1 - type: integer Parameter MMCM_CLKOUT3_DIVIDE bound to: 1 - type: integer Parameter MMCM_CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter RST_ACT_LOW bound to: 1 - type: integer Parameter tCK bound to: 1250 - type: integer Parameter MEM_TYPE bound to: DDR3 - type: string Parameter RST_SYNC_NUM bound to: 25 - type: integer Parameter RST_DIV_SYNC_NUM bound to: 13 - type: integer Parameter CLKIN1_PERIOD_NS bound to: 5.000000 - type: double Parameter CLKOUT4_DIVIDE bound to: 4 - type: integer Parameter VCO_PERIOD bound to: 625 - type: integer Parameter CLKOUT0_PERIOD bound to: 1250 - type: integer Parameter CLKOUT1_PERIOD bound to: 1250 - type: integer Parameter CLKOUT2_PERIOD bound to: 20000 - type: integer Parameter CLKOUT3_PERIOD bound to: 5000 - type: integer Parameter CLKOUT4_PERIOD bound to: 2500 - type: integer Parameter CLKOUT4_PHASE bound to: 168.750000 - type: double Parameter CLKOUT3_PERIOD_NS bound to: 5.000000 - type: double Parameter CLKOUT4_PERIOD_NS bound to: 2.500000 - type: double Parameter MMCM_VCO_PERIOD bound to: 1250.000000 - type: double Parameter ONE bound to: 1 - type: integer Parameter TAPSPERFCLK bound to: 224 - type: integer Parameter TAPSPERFCLK_MINUS_ONE bound to: 223 - type: integer Parameter QCNTR_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV__parameterized0' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:39994] Parameter BANDWIDTH bound to: HIGH - type: string Parameter CLKFBOUT_MULT_F bound to: 4.000000 - type: double Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string Parameter CLKIN1_PERIOD bound to: 5.000000 - type: double Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double Parameter CLKOUT0_DIVIDE_F bound to: 8.000000 - type: double Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double Parameter CLKOUT0_USE_FINE_PS bound to: TRUE - type: string Parameter CLKOUT1_DIVIDE bound to: 2 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT4_CASCADE bound to: FALSE - type: string Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string Parameter COMPENSATION bound to: BUF_IN - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PSEN_INVERTED bound to: 1'b0 Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.000000 - type: double Parameter REF_JITTER2 bound to: 0.010000 - type: double Parameter SS_EN bound to: FALSE - type: string Parameter SS_MODE bound to: CENTER_HIGH - type: string Parameter SS_MOD_PERIOD bound to: 10000 - type: integer Parameter STARTUP_WAIT bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV__parameterized0' (8#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:39994] INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61519] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT bound to: 8 - type: integer Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double Parameter CLKIN1_PERIOD bound to: 5.000000 - type: double Parameter CLKIN2_PERIOD bound to: 0.000000 - type: double Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT0_PHASE bound to: 337.500000 - type: double Parameter CLKOUT1_DIVIDE bound to: 2 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.062500 - type: double Parameter CLKOUT2_PHASE bound to: 9.843750 - type: double Parameter CLKOUT3_DIVIDE bound to: 8 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double Parameter CLKOUT4_DIVIDE bound to: 4 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT4_PHASE bound to: 168.750000 - type: double Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double Parameter COMPENSATION bound to: INTERNAL - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.010000 - type: double Parameter REF_JITTER2 bound to: 0.010000 - type: double Parameter STARTUP_WAIT bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (9#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61519] INFO: [Synth 8-6157] synthesizing module 'BUFH' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1319] INFO: [Synth 8-6155] done synthesizing module 'BUFH' (10#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1319] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_infrastructure' (11#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:72] Parameter TCQ bound to: 100 - type: integer Parameter DDR3_VDD_OP_VOLT bound to: 150 - type: string Parameter PAYLOAD_WIDTH bound to: 32 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter AL bound to: 0 - type: string Parameter BANK_WIDTH bound to: 3 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter BURST_TYPE bound to: SEQ - type: string Parameter CA_MIRROR bound to: OFF - type: string Parameter CK_WIDTH bound to: 1 - type: integer Parameter CL bound to: 11 - type: integer Parameter COL_WIDTH bound to: 10 - type: integer Parameter CMD_PIPE_PLUS1 bound to: ON - type: string Parameter CS_WIDTH bound to: 1 - type: integer Parameter CKE_WIDTH bound to: 1 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DATA_BUF_OFFSET_WIDTH bound to: 1 - type: integer Parameter DDR2_DQSN_ENABLE bound to: YES - type: string Parameter DM_WIDTH bound to: 4 - type: integer Parameter DQ_CNT_WIDTH bound to: 5 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter DRAM_WIDTH bound to: 8 - type: integer Parameter ECC bound to: OFF - type: string Parameter ECC_WIDTH bound to: 0 - type: integer Parameter ECC_TEST bound to: OFF - type: string Parameter MC_ERR_ADDR_WIDTH bound to: 29 - type: integer Parameter MASTER_PHY_CTL bound to: 1 - type: integer Parameter nAL bound to: 0 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nCS_PER_RANK bound to: 1 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter IBUF_LPWR_MODE bound to: OFF - type: string Parameter BANK_TYPE bound to: HP_IO - type: string Parameter DATA_IO_PRIM_TYPE bound to: HP_LP - type: string Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string Parameter IODELAY_GRP0 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG0 - type: string Parameter IODELAY_GRP1 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter OUTPUT_DRV bound to: HIGH - type: string Parameter REG_CTRL bound to: OFF - type: string Parameter RTT_NOM bound to: 40 - type: string Parameter RTT_WR bound to: OFF - type: string Parameter STARVE_LIMIT bound to: 2 - type: integer Parameter tCK bound to: 1250 - type: integer Parameter tCKE bound to: 5000 - type: integer Parameter tFAW bound to: 35000 - type: integer Parameter tPRDI bound to: 1000000 - type: integer Parameter tRAS bound to: 34000 - type: integer Parameter tRCD bound to: 13910 - type: integer Parameter tREFI bound to: 7800000 - type: integer Parameter tRFC bound to: 260000 - type: integer Parameter tRP bound to: 13910 - type: integer Parameter tRRD bound to: 6000 - type: integer Parameter tRTP bound to: 7500 - type: integer Parameter tWTR bound to: 7500 - type: integer Parameter tZQI bound to: 128000000 - type: integer Parameter tZQCS bound to: 64 - type: integer Parameter USER_REFRESH bound to: OFF - type: string Parameter TEMP_MON_EN bound to: ON - type: string Parameter WRLVL bound to: ON - type: string Parameter DEBUG_PORT bound to: OFF - type: string Parameter CAL_WIDTH bound to: HALF - type: string Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter ODT_WIDTH bound to: 1 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter ADDR_WIDTH bound to: 29 - type: integer Parameter APP_MASK_WIDTH bound to: 32 - type: integer Parameter APP_DATA_WIDTH bound to: 256 - type: integer Parameter BYTE_LANES_B0 bound to: 4'b1111 Parameter BYTE_LANES_B1 bound to: 4'b1111 Parameter BYTE_LANES_B2 bound to: 4'b0000 Parameter BYTE_LANES_B3 bound to: 4'b0000 Parameter BYTE_LANES_B4 bound to: 4'b0000 Parameter DATA_CTL_B0 bound to: 4'b1111 Parameter DATA_CTL_B1 bound to: 4'b0000 Parameter DATA_CTL_B2 bound to: 4'b0000 Parameter DATA_CTL_B3 bound to: 4'b0000 Parameter DATA_CTL_B4 bound to: 4'b0000 Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110001111111110001011111111 Parameter PHY_1_BITLANES bound to: 48'b001111111110111111111100110000010000000000000011 Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011 Parameter ADDR_MAP bound to: 192'b000000000000000100010100000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100100101000100101000000100100111000100100110000100101011 Parameter BANK_MAP bound to: 36'b000100101010000100101001000100100100 Parameter CAS_MAP bound to: 12'b000100100010 Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011 Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010 Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 Parameter PARITY_MAP bound to: 12'b000000000000 Parameter RAS_MAP bound to: 12'b000100100011 Parameter WE_MAP bound to: 12'b000100000001 Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011 Parameter DATA0_MAP bound to: 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000 Parameter DATA1_MAP bound to: 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000 Parameter DATA2_MAP bound to: 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000 Parameter DATA3_MAP bound to: 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111 Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001 Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter SLOT_0_CONFIG bound to: 8'b00000001 Parameter SLOT_1_CONFIG bound to: 8'b00000000 Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 Parameter CALIB_COL_ADD bound to: 12'b000000000000 Parameter CALIB_BA_ADD bound to: 3'b000 Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string Parameter REFCLK_FREQ bound to: 200.000000 - type: double Parameter USE_CS_PORT bound to: 1 - type: integer Parameter USE_DM_PORT bound to: 1 - type: integer Parameter USE_ODT_PORT bound to: 1 - type: integer Parameter IDELAY_ADJ bound to: ON - type: string Parameter FINE_PER_BIT bound to: ON - type: string Parameter CENTER_COMP_MODE bound to: ON - type: string Parameter PI_VAL_ADJ bound to: ON - type: string Parameter SKIP_CALIB bound to: FALSE - type: string Parameter TAPSPERKCLK bound to: 56 - type: integer Parameter C_S_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000 Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000 Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_BASEADDR bound to: 0 - type: integer Parameter C_ECC_ONOFF_RESET_VALUE bound to: 1 - type: integer Parameter C_ECC_CE_COUNTER_WIDTH bound to: 8 - type: integer Parameter FPGA_VOLT_TYPE bound to: N - type: string Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter INTERFACE bound to: AXI4 - type: string Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_MC_DATA_WIDTH_LCL bound to: 256 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] Parameter TCQ bound to: 100 - type: integer Parameter DDR3_VDD_OP_VOLT bound to: 150 - type: string Parameter PAYLOAD_WIDTH bound to: 32 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter AL bound to: 0 - type: string Parameter BANK_WIDTH bound to: 3 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter BURST_TYPE bound to: SEQ - type: string Parameter CA_MIRROR bound to: OFF - type: string Parameter CK_WIDTH bound to: 1 - type: integer Parameter DATA_CTL_B0 bound to: 4'b1111 Parameter DATA_CTL_B1 bound to: 4'b0000 Parameter DATA_CTL_B2 bound to: 4'b0000 Parameter DATA_CTL_B3 bound to: 4'b0000 Parameter DATA_CTL_B4 bound to: 4'b0000 Parameter BYTE_LANES_B0 bound to: 4'b1111 Parameter BYTE_LANES_B1 bound to: 4'b1111 Parameter BYTE_LANES_B2 bound to: 4'b0000 Parameter BYTE_LANES_B3 bound to: 4'b0000 Parameter BYTE_LANES_B4 bound to: 4'b0000 Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110001111111110001011111111 Parameter PHY_1_BITLANES bound to: 48'b001111111110111111111100110000010000000000000011 Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011 Parameter ADDR_MAP bound to: 192'b000000000000000100010100000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100100101000100101000000100100111000100100110000100101011 Parameter BANK_MAP bound to: 36'b000100101010000100101001000100100100 Parameter CAS_MAP bound to: 12'b000100100010 Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011 Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010 Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 Parameter PARITY_MAP bound to: 12'b000000000000 Parameter RAS_MAP bound to: 12'b000100100011 Parameter WE_MAP bound to: 12'b000100000001 Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011 Parameter DATA0_MAP bound to: 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000 Parameter DATA1_MAP bound to: 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000 Parameter DATA2_MAP bound to: 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000 Parameter DATA3_MAP bound to: 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111 Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001 Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 Parameter CALIB_COL_ADD bound to: 12'b000000000000 Parameter CALIB_BA_ADD bound to: 3'b000 Parameter CL bound to: 11 - type: integer Parameter COL_WIDTH bound to: 10 - type: integer Parameter CMD_PIPE_PLUS1 bound to: ON - type: string Parameter CS_WIDTH bound to: 1 - type: integer Parameter CKE_WIDTH bound to: 1 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DATA_BUF_OFFSET_WIDTH bound to: 1 - type: integer Parameter DDR2_DQSN_ENABLE bound to: YES - type: string Parameter DM_WIDTH bound to: 4 - type: integer Parameter DQ_CNT_WIDTH bound to: 5 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter DRAM_WIDTH bound to: 8 - type: integer Parameter ECC bound to: OFF - type: string Parameter ECC_WIDTH bound to: 0 - type: integer Parameter MC_ERR_ADDR_WIDTH bound to: 29 - type: integer Parameter nAL bound to: 0 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter PRE_REV3ES bound to: OFF - type: string Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nCS_PER_RANK bound to: 1 - type: integer Parameter PHYCTL_CMD_FIFO bound to: FALSE - type: string Parameter ORDERING bound to: NORM - type: string Parameter PHASE_DETECT bound to: OFF - type: string Parameter IBUF_LPWR_MODE bound to: OFF - type: string Parameter BANK_TYPE bound to: HP_IO - type: string Parameter DATA_IO_PRIM_TYPE bound to: HP_LP - type: string Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter OUTPUT_DRV bound to: HIGH - type: string Parameter REG_CTRL bound to: OFF - type: string Parameter RTT_NOM bound to: 40 - type: string Parameter RTT_WR bound to: OFF - type: string Parameter STARVE_LIMIT bound to: 2 - type: integer Parameter tCK bound to: 1250 - type: integer Parameter tCKE bound to: 5000 - type: integer Parameter tFAW bound to: 35000 - type: integer Parameter tPRDI bound to: 1000000 - type: integer Parameter tRAS bound to: 34000 - type: integer Parameter tRCD bound to: 13910 - type: integer Parameter tREFI bound to: 7800000 - type: integer Parameter tRFC bound to: 260000 - type: integer Parameter tRP bound to: 13910 - type: integer Parameter tRRD bound to: 6000 - type: integer Parameter tRTP bound to: 7500 - type: integer Parameter tWTR bound to: 7500 - type: integer Parameter tZQI bound to: 128000000 - type: integer Parameter tZQCS bound to: 64 - type: integer Parameter WRLVL bound to: ON - type: string Parameter DEBUG_PORT bound to: OFF - type: string Parameter CAL_WIDTH bound to: HALF - type: string Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter ODT_WIDTH bound to: 1 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter SLOT_0_CONFIG bound to: 8'b00000001 Parameter SLOT_1_CONFIG bound to: 8'b00000000 Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string Parameter REFCLK_FREQ bound to: 200.000000 - type: double Parameter nDQS_COL0 bound to: 4 - type: integer Parameter nDQS_COL1 bound to: 0 - type: integer Parameter nDQS_COL2 bound to: 0 - type: integer Parameter nDQS_COL3 bound to: 0 - type: integer Parameter DQS_LOC_COL0 bound to: 144'b000100010001000000001111000011100000110100001100000010110000101000001001000010000000011100000110000001010000010000000011000000100000000100000000 Parameter DQS_LOC_COL1 bound to: 0 - type: integer Parameter DQS_LOC_COL2 bound to: 0 - type: integer Parameter DQS_LOC_COL3 bound to: 0 - type: integer Parameter USE_CS_PORT bound to: 1 - type: integer Parameter USE_DM_PORT bound to: 1 - type: integer Parameter USE_ODT_PORT bound to: 1 - type: integer Parameter MASTER_PHY_CTL bound to: 1 - type: integer Parameter USER_REFRESH bound to: OFF - type: string Parameter TEMP_MON_EN bound to: ON - type: string Parameter IDELAY_ADJ bound to: ON - type: string Parameter FINE_PER_BIT bound to: ON - type: string Parameter CENTER_COMP_MODE bound to: ON - type: string Parameter PI_VAL_ADJ bound to: ON - type: string Parameter TAPSPERKCLK bound to: 56 - type: integer Parameter SKIP_CALIB bound to: FALSE - type: string Parameter FPGA_VOLT_TYPE bound to: N - type: string Parameter nSLOTS bound to: 1 - type: integer Parameter SLOT_0_CONFIG_MC bound to: 8'b00001111 Parameter SLOT_1_CONFIG_MC bound to: 8'b00000000 Parameter REFRESH_TIMER bound to: 12210 - type: integer Parameter CWL_T bound to: 8 - type: integer Parameter CLK_PERIOD bound to: 5000 - type: integer Parameter nCL bound to: 11 - type: integer Parameter nCWL bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] Parameter TCQ bound to: 100 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BANK_WIDTH bound to: 3 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter CL bound to: 11 - type: integer Parameter CMD_PIPE_PLUS1 bound to: ON - type: string Parameter COL_WIDTH bound to: 10 - type: integer Parameter CS_WIDTH bound to: 1 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DATA_BUF_OFFSET_WIDTH bound to: 1 - type: integer Parameter DATA_WIDTH bound to: 32 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter ECC bound to: OFF - type: string Parameter ECC_WIDTH bound to: 0 - type: integer Parameter MAINT_PRESCALER_PERIOD bound to: 200000 - type: integer Parameter MC_ERR_ADDR_WIDTH bound to: 29 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nCS_PER_RANK bound to: 1 - type: integer Parameter nREFRESH_BANK bound to: 1 - type: integer Parameter nSLOTS bound to: 1 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter PAYLOAD_WIDTH bound to: 32 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter REG_CTRL bound to: OFF - type: string Parameter ROW_WIDTH bound to: 15 - type: integer Parameter RTT_NOM bound to: 40 - type: string Parameter RTT_WR bound to: OFF - type: string Parameter SLOT_0_CONFIG bound to: 8'b00001111 Parameter SLOT_1_CONFIG bound to: 8'b00000000 Parameter STARVE_LIMIT bound to: 2 - type: integer Parameter tCK bound to: 1250 - type: integer Parameter tCKE bound to: 5000 - type: integer Parameter tFAW bound to: 35000 - type: integer Parameter tRAS bound to: 34000 - type: integer Parameter tRCD bound to: 13910 - type: integer Parameter tREFI bound to: 7800000 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter tRFC bound to: 260000 - type: integer Parameter tRP bound to: 13910 - type: integer Parameter tRRD bound to: 6000 - type: integer Parameter tRTP bound to: 7500 - type: integer Parameter tWTR bound to: 7500 - type: integer Parameter tZQCS bound to: 64 - type: integer Parameter tZQI bound to: 128000000 - type: integer Parameter tPRDI bound to: 1000000 - type: integer Parameter USER_REFRESH bound to: OFF - type: string Parameter nPHY_WRLAT bound to: 2 - type: integer Parameter DELAY_WR_DATA_CNTRL bound to: 1 - type: integer Parameter EARLY_WR_DATA_ADDR bound to: OFF - type: string Parameter nCKE bound to: 4 - type: integer Parameter nRP bound to: 12 - type: integer Parameter nRCD bound to: 12 - type: integer Parameter nRAS bound to: 28 - type: integer Parameter nFAW bound to: 28 - type: integer Parameter nRFC bound to: 208 - type: integer Parameter nWR_CK bound to: 12 - type: integer Parameter nWR bound to: 12 - type: integer Parameter nRRD_CK bound to: 5 - type: integer Parameter nRRD bound to: 5 - type: integer Parameter nWTR_CK bound to: 6 - type: integer Parameter nWTR bound to: 6 - type: integer Parameter nRTP_CK bound to: 6 - type: integer Parameter nRTP bound to: 6 - type: integer Parameter CWL_M bound to: 8 - type: integer Parameter CL_M bound to: 11 - type: integer Parameter DQRD2DQWR_DLY bound to: 4 - type: integer Parameter nCKESR bound to: 5 - type: integer Parameter tXSDLL bound to: 512 - type: integer Parameter MAINT_PRESCALER_DIV bound to: 40 - type: integer Parameter REFRESH_TIMER_DIV bound to: 38 - type: integer Parameter PERIODIC_RD_TIMER_DIV bound to: 5 - type: integer Parameter MAINT_PRESCALER_PERIOD_NS bound to: 200 - type: integer Parameter ZQ_TIMER_DIV bound to: 640000 - type: integer Parameter RANK_BM_BV_WIDTH bound to: 4 - type: integer Parameter EVEN_CWL_2T_MODE bound to: OFF - type: string Parameter nOP_WAIT bound to: 0 - type: integer Parameter LOW_IDLE_CNT bound to: 0 - type: integer Parameter CODE_WIDTH bound to: 32 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_mach' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] Parameter BURST_MODE bound to: 8 - type: string Parameter CS_WIDTH bound to: 1 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter MAINT_PRESCALER_DIV bound to: 40 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCKESR bound to: 5 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter CL bound to: 11 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DQRD2DQWR_DLY bound to: 4 - type: integer Parameter nFAW bound to: 28 - type: integer Parameter nREFRESH_BANK bound to: 1 - type: integer Parameter nRRD bound to: 5 - type: integer Parameter nWTR bound to: 6 - type: integer Parameter PERIODIC_RD_TIMER_DIV bound to: 5 - type: integer Parameter RANK_BM_BV_WIDTH bound to: 4 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter REFRESH_TIMER_DIV bound to: 38 - type: integer Parameter ZQ_TIMER_DIV bound to: 640000 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_cntrl' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] Parameter TCQ bound to: 100 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter DQRD2DQWR_DLY bound to: 4 - type: integer Parameter CL bound to: 11 - type: integer Parameter CWL bound to: 8 - type: integer Parameter ID bound to: 0 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nFAW bound to: 28 - type: integer Parameter nREFRESH_BANK bound to: 1 - type: integer Parameter nRRD bound to: 5 - type: integer Parameter nWTR bound to: 6 - type: integer Parameter PERIODIC_RD_TIMER_DIV bound to: 5 - type: integer Parameter RANK_BM_BV_WIDTH bound to: 4 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter REFRESH_TIMER_DIV bound to: 38 - type: integer Parameter nADD_RRD bound to: -3 - type: integer Parameter nRRD_CLKS bound to: 1 - type: integer Parameter ADD_RRD_CNTR_WIDTH bound to: 1 - type: integer Parameter nFAW_CLKS bound to: 7 - type: integer Parameter ONE bound to: 1 - type: integer Parameter TWO bound to: 2 - type: integer Parameter CASWR2CASRD bound to: 18 - type: integer Parameter CASWR2CASRD_CLKS bound to: 5 - type: integer Parameter WTR_CNT_WIDTH bound to: 3 - type: integer Parameter CASRD2CASWR bound to: 11 - type: integer Parameter CASRD2CASWR_CLKS bound to: 3 - type: integer Parameter RTW_CNT_WIDTH bound to: 2 - type: integer Parameter REFRESH_BANK_WIDTH bound to: 1 - type: integer Parameter PERIODIC_RD_TIMER_WIDTH bound to: 3 - type: integer INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:78209] Parameter INIT bound to: 32'b00000000000000000000000000000000 Parameter IS_CLK_INVERTED bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (12#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:78209] WARNING: [Synth 8-567] referenced signal 'periodic_rd_generation.periodic_rd_timer_one' should be on the sensitivity list [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:509] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_cntrl' (13#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_common' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] Parameter TCQ bound to: 100 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter MAINT_PRESCALER_DIV bound to: 40 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCKESR bound to: 5 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter PERIODIC_RD_TIMER_DIV bound to: 5 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter REFRESH_TIMER_DIV bound to: 38 - type: integer Parameter ZQ_TIMER_DIV bound to: 640000 - type: integer Parameter ONE bound to: 1 - type: integer Parameter MAINT_PRESCALER_WIDTH bound to: 6 - type: integer Parameter REFRESH_TIMER_WIDTH bound to: 6 - type: integer Parameter ZQ_TIMER_WIDTH bound to: 20 - type: integer Parameter nCKESR_CLKS bound to: 2 - type: integer Parameter CKESR_TIMER_WIDTH bound to: 2 - type: integer WARNING: [Synth 8-567] referenced signal 'zq_cntrl.zq_tick' should be on the sensitivity list [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:172] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] Parameter TCQ bound to: 100 - type: integer Parameter WIDTH bound to: 3 - type: integer Parameter ONE bound to: 4 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb' (14#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] Parameter TCQ bound to: 100 - type: integer Parameter WIDTH bound to: 1 - type: integer Parameter ONE bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' (14#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_common' (15#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_mach' (16#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] Parameter TCQ bound to: 100 - type: integer Parameter EVEN_CWL_2T_MODE bound to: OFF - type: string Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BANK_WIDTH bound to: 3 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter COL_WIDTH bound to: 10 - type: integer Parameter CS_WIDTH bound to: 1 - type: integer Parameter CL bound to: 11 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter EARLY_WR_DATA_ADDR bound to: OFF - type: string Parameter ECC bound to: OFF - type: string Parameter LOW_IDLE_CNT bound to: 0 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nCS_PER_RANK bound to: 1 - type: integer Parameter nOP_WAIT bound to: 0 - type: integer Parameter nRAS bound to: 28 - type: integer Parameter nRCD bound to: 12 - type: integer Parameter nRFC bound to: 208 - type: integer Parameter nRTP bound to: 6 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter nRP bound to: 12 - type: integer Parameter nSLOTS bound to: 1 - type: integer Parameter nWR bound to: 12 - type: integer Parameter nXSDLL bound to: 512 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter RANK_BM_BV_WIDTH bound to: 4 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter RTT_NOM bound to: 40 - type: string Parameter RTT_WR bound to: OFF - type: string Parameter STARVE_LIMIT bound to: 2 - type: integer Parameter SLOT_0_CONFIG bound to: 8'b00001111 Parameter SLOT_1_CONFIG bound to: 8'b00000000 Parameter tZQCS bound to: 64 - type: integer Parameter RANK_VECT_INDX bound to: 3 - type: integer Parameter BANK_VECT_INDX bound to: 11 - type: integer Parameter ROW_VECT_INDX bound to: 59 - type: integer Parameter DATA_BUF_ADDR_VECT_INDX bound to: 19 - type: integer Parameter nRAS_CLKS bound to: 7 - type: integer Parameter nWTP bound to: 24 - type: integer Parameter nWTP_CLKS bound to: 8 - type: integer Parameter RAS_TIMER_WIDTH bound to: 3 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] Parameter TCQ bound to: 100 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BANK_WIDTH bound to: 3 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter COL_WIDTH bound to: 10 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter ECC bound to: OFF - type: string Parameter ID bound to: 0 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nOP_WAIT bound to: 0 - type: integer Parameter nRAS_CLKS bound to: 7 - type: integer Parameter nRCD bound to: 12 - type: integer Parameter nRTP bound to: 6 - type: integer Parameter nRP bound to: 12 - type: integer Parameter nWTP_CLKS bound to: 8 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter RAS_TIMER_WIDTH bound to: 3 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter STARVE_LIMIT bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_compare' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] Parameter BANK_WIDTH bound to: 3 - type: integer Parameter TCQ bound to: 100 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter COL_WIDTH bound to: 10 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter ECC bound to: OFF - type: string Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter ONE bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_compare' (17#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] Parameter TCQ bound to: 100 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter ECC bound to: OFF - type: string Parameter ID bound to: 0 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nOP_WAIT bound to: 0 - type: integer Parameter nRAS_CLKS bound to: 7 - type: integer Parameter nRP bound to: 12 - type: integer Parameter nRTP bound to: 6 - type: integer Parameter nRCD bound to: 12 - type: integer Parameter nWTP_CLKS bound to: 8 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter RANKS bound to: 1 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RAS_TIMER_WIDTH bound to: 3 - type: integer Parameter STARVE_LIMIT bound to: 2 - type: integer Parameter nRCD_CLKS bound to: 4 - type: integer Parameter nRCD_CLKS_M2 bound to: 2 - type: integer Parameter RCD_TIMER_WIDTH bound to: 2 - type: integer Parameter ZERO bound to: 0 - type: integer Parameter ONE bound to: 1 - type: integer Parameter TWO bound to: 2 - type: integer Parameter nRTP_CLKS bound to: 3 - type: integer Parameter nRTP_CLKS_M1 bound to: 2 - type: integer Parameter RTP_TIMER_WIDTH bound to: 2 - type: integer Parameter OP_WIDTH bound to: 1 - type: integer Parameter nRP_CLKS bound to: 3 - type: integer Parameter nRP_CLKS_M2 bound to: 1 - type: integer Parameter RP_TIMER_WIDTH bound to: 1 - type: integer Parameter STARVE_LIMIT_CNT bound to: 8 - type: integer Parameter STARVE_LIMIT_WIDTH bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state' (18#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] Parameter TCQ bound to: 100 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter ID bound to: 0 - type: integer Parameter ZERO bound to: 0 - type: integer Parameter ONE bound to: 1 - type: integer Parameter BM_CNT_ZERO bound to: 2'b00 Parameter BM_CNT_ONE bound to: 2'b01 INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue' (19#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] Parameter TCQ bound to: 100 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BANK_WIDTH bound to: 3 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter COL_WIDTH bound to: 10 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter ECC bound to: OFF - type: string Parameter ID bound to: 1 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nOP_WAIT bound to: 0 - type: integer Parameter nRAS_CLKS bound to: 7 - type: integer Parameter nRCD bound to: 12 - type: integer Parameter nRTP bound to: 6 - type: integer Parameter nRP bound to: 12 - type: integer Parameter nWTP_CLKS bound to: 8 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter RAS_TIMER_WIDTH bound to: 3 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter STARVE_LIMIT bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] Parameter TCQ bound to: 100 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter ECC bound to: OFF - type: string Parameter ID bound to: 1 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nOP_WAIT bound to: 0 - type: integer Parameter nRAS_CLKS bound to: 7 - type: integer Parameter nRP bound to: 12 - type: integer Parameter nRTP bound to: 6 - type: integer Parameter nRCD bound to: 12 - type: integer Parameter nWTP_CLKS bound to: 8 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter RANKS bound to: 1 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RAS_TIMER_WIDTH bound to: 3 - type: integer Parameter STARVE_LIMIT bound to: 2 - type: integer Parameter nRCD_CLKS bound to: 4 - type: integer Parameter nRCD_CLKS_M2 bound to: 2 - type: integer Parameter RCD_TIMER_WIDTH bound to: 2 - type: integer Parameter ZERO bound to: 0 - type: integer Parameter ONE bound to: 1 - type: integer Parameter TWO bound to: 2 - type: integer Parameter nRTP_CLKS bound to: 3 - type: integer Parameter nRTP_CLKS_M1 bound to: 2 - type: integer Parameter RTP_TIMER_WIDTH bound to: 2 - type: integer Parameter OP_WIDTH bound to: 1 - type: integer Parameter nRP_CLKS bound to: 3 - type: integer Parameter nRP_CLKS_M2 bound to: 1 - type: integer Parameter RP_TIMER_WIDTH bound to: 1 - type: integer Parameter STARVE_LIMIT_CNT bound to: 8 - type: integer Parameter STARVE_LIMIT_WIDTH bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] Parameter TCQ bound to: 100 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter ID bound to: 1 - type: integer Parameter ZERO bound to: 0 - type: integer Parameter ONE bound to: 1 - type: integer Parameter BM_CNT_ZERO bound to: 2'b00 Parameter BM_CNT_ONE bound to: 2'b01 INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] Parameter TCQ bound to: 100 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BANK_WIDTH bound to: 3 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter COL_WIDTH bound to: 10 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter ECC bound to: OFF - type: string Parameter ID bound to: 2 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nOP_WAIT bound to: 0 - type: integer Parameter nRAS_CLKS bound to: 7 - type: integer Parameter nRCD bound to: 12 - type: integer Parameter nRTP bound to: 6 - type: integer Parameter nRP bound to: 12 - type: integer Parameter nWTP_CLKS bound to: 8 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter RAS_TIMER_WIDTH bound to: 3 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter STARVE_LIMIT bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] Parameter TCQ bound to: 100 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter ECC bound to: OFF - type: string Parameter ID bound to: 2 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nOP_WAIT bound to: 0 - type: integer Parameter nRAS_CLKS bound to: 7 - type: integer Parameter nRP bound to: 12 - type: integer Parameter nRTP bound to: 6 - type: integer Parameter nRCD bound to: 12 - type: integer Parameter nWTP_CLKS bound to: 8 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter RANKS bound to: 1 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RAS_TIMER_WIDTH bound to: 3 - type: integer Parameter STARVE_LIMIT bound to: 2 - type: integer Parameter nRCD_CLKS bound to: 4 - type: integer Parameter nRCD_CLKS_M2 bound to: 2 - type: integer Parameter RCD_TIMER_WIDTH bound to: 2 - type: integer Parameter ZERO bound to: 0 - type: integer Parameter ONE bound to: 1 - type: integer Parameter TWO bound to: 2 - type: integer Parameter nRTP_CLKS bound to: 3 - type: integer Parameter nRTP_CLKS_M1 bound to: 2 - type: integer Parameter RTP_TIMER_WIDTH bound to: 2 - type: integer Parameter OP_WIDTH bound to: 1 - type: integer Parameter nRP_CLKS bound to: 3 - type: integer Parameter nRP_CLKS_M2 bound to: 1 - type: integer Parameter RP_TIMER_WIDTH bound to: 1 - type: integer Parameter STARVE_LIMIT_CNT bound to: 8 - type: integer Parameter STARVE_LIMIT_WIDTH bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] Parameter TCQ bound to: 100 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter ID bound to: 2 - type: integer Parameter ZERO bound to: 0 - type: integer Parameter ONE bound to: 1 - type: integer Parameter BM_CNT_ZERO bound to: 2'b00 Parameter BM_CNT_ONE bound to: 2'b01 INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] Parameter TCQ bound to: 100 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BANK_WIDTH bound to: 3 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter COL_WIDTH bound to: 10 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter ECC bound to: OFF - type: string Parameter ID bound to: 3 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nOP_WAIT bound to: 0 - type: integer Parameter nRAS_CLKS bound to: 7 - type: integer Parameter nRCD bound to: 12 - type: integer Parameter nRTP bound to: 6 - type: integer Parameter nRP bound to: 12 - type: integer Parameter nWTP_CLKS bound to: 8 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter RAS_TIMER_WIDTH bound to: 3 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter STARVE_LIMIT bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] Parameter TCQ bound to: 100 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter ECC bound to: OFF - type: string Parameter ID bound to: 3 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nOP_WAIT bound to: 0 - type: integer Parameter nRAS_CLKS bound to: 7 - type: integer Parameter nRP bound to: 12 - type: integer Parameter nRTP bound to: 6 - type: integer Parameter nRCD bound to: 12 - type: integer Parameter nWTP_CLKS bound to: 8 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter RANKS bound to: 1 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RAS_TIMER_WIDTH bound to: 3 - type: integer Parameter STARVE_LIMIT bound to: 2 - type: integer Parameter nRCD_CLKS bound to: 4 - type: integer Parameter nRCD_CLKS_M2 bound to: 2 - type: integer Parameter RCD_TIMER_WIDTH bound to: 2 - type: integer Parameter ZERO bound to: 0 - type: integer Parameter ONE bound to: 1 - type: integer Parameter TWO bound to: 2 - type: integer Parameter nRTP_CLKS bound to: 3 - type: integer Parameter nRTP_CLKS_M1 bound to: 2 - type: integer Parameter RTP_TIMER_WIDTH bound to: 2 - type: integer Parameter OP_WIDTH bound to: 1 - type: integer Parameter nRP_CLKS bound to: 3 - type: integer Parameter nRP_CLKS_M2 bound to: 1 - type: integer Parameter RP_TIMER_WIDTH bound to: 1 - type: integer Parameter STARVE_LIMIT_CNT bound to: 8 - type: integer Parameter STARVE_LIMIT_WIDTH bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] Parameter TCQ bound to: 100 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter ID bound to: 3 - type: integer Parameter ZERO bound to: 0 - type: integer Parameter ONE bound to: 1 - type: integer Parameter BM_CNT_ZERO bound to: 2'b00 Parameter BM_CNT_ONE bound to: 2'b01 INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' (20#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_common' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] Parameter TCQ bound to: 100 - type: integer Parameter BM_CNT_WIDTH bound to: 2 - type: integer Parameter LOW_IDLE_CNT bound to: 0 - type: integer Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nOP_WAIT bound to: 0 - type: integer Parameter nRFC bound to: 208 - type: integer Parameter nXSDLL bound to: 512 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter CWL bound to: 8 - type: integer Parameter tZQCS bound to: 64 - type: integer Parameter ZERO bound to: 0 - type: integer Parameter ONE bound to: 1 - type: integer Parameter BM_CNT_ZERO bound to: 2'b00 Parameter BM_CNT_ONE bound to: 2'b01 Parameter nRFC_CLKS bound to: 52 - type: integer Parameter nZQCS_CLKS bound to: 16 - type: integer Parameter nXSDLL_CLKS bound to: 128 - type: integer Parameter RFC_ZQ_TIMER_WIDTH bound to: 8 - type: integer Parameter THREE bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_common' (21#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_mux' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] Parameter TCQ bound to: 100 - type: integer Parameter EVEN_CWL_2T_MODE bound to: OFF - type: string Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BANK_VECT_INDX bound to: 11 - type: integer Parameter BANK_WIDTH bound to: 3 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter CS_WIDTH bound to: 1 - type: integer Parameter CL bound to: 11 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_VECT_INDX bound to: 19 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter EARLY_WR_DATA_ADDR bound to: OFF - type: string Parameter ECC bound to: OFF - type: string Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nCS_PER_RANK bound to: 1 - type: integer Parameter nRAS bound to: 28 - type: integer Parameter nRCD bound to: 12 - type: integer Parameter nSLOTS bound to: 1 - type: integer Parameter nWR bound to: 12 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter RANK_VECT_INDX bound to: 3 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter ROW_VECT_INDX bound to: 59 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter RTT_NOM bound to: 40 - type: string Parameter RTT_WR bound to: OFF - type: string Parameter SLOT_0_CONFIG bound to: 8'b00001111 Parameter SLOT_1_CONFIG bound to: 8'b00000000 INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_row_col' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] Parameter TCQ bound to: 100 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter CWL bound to: 8 - type: integer Parameter EARLY_WR_DATA_ADDR bound to: OFF - type: string Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nRAS bound to: 28 - type: integer Parameter nRCD bound to: 12 - type: integer Parameter nWR bound to: 12 - type: integer Parameter RNK2RNK_DLY bound to: 12 - type: integer Parameter RNK2RNK_DLY_CLKS bound to: 3 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] Parameter TCQ bound to: 100 - type: integer Parameter WIDTH bound to: 4 - type: integer Parameter ONE bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' (21#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_row_col' (22#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_select' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] Parameter TCQ bound to: 100 - type: integer Parameter EVEN_CWL_2T_MODE bound to: OFF - type: string Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BANK_VECT_INDX bound to: 11 - type: integer Parameter BANK_WIDTH bound to: 3 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter CS_WIDTH bound to: 1 - type: integer Parameter CL bound to: 11 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_VECT_INDX bound to: 19 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter EARLY_WR_DATA_ADDR bound to: OFF - type: string Parameter ECC bound to: OFF - type: string Parameter nBANK_MACHS bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nCS_PER_RANK bound to: 1 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter nSLOTS bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter RANK_VECT_INDX bound to: 3 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter ROW_VECT_INDX bound to: 59 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter RTT_NOM bound to: 40 - type: string Parameter RTT_WR bound to: OFF - type: string Parameter SLOT_0_CONFIG bound to: 8'b00001111 Parameter SLOT_1_CONFIG bound to: 8'b00000000 Parameter OUT_CMD_WIDTH bound to: 22 - type: integer Parameter ONE bound to: 1'b1 INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_select' (23#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_mux' (24#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_mach' (25#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] WARNING: [Synth 8-7071] port 'idle' of module 'mig_7series_v4_2_bank_mach' is unconnected for instance 'bank_mach0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] WARNING: [Synth 8-7023] instance 'bank_mach0' of module 'mig_7series_v4_2_bank_mach' has 74 connections declared, but only 73 given [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_col_mach' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] Parameter TCQ bound to: 100 - type: integer Parameter BANK_WIDTH bound to: 3 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter COL_WIDTH bound to: 10 - type: integer Parameter CS_WIDTH bound to: 1 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter DATA_BUF_OFFSET_WIDTH bound to: 1 - type: integer Parameter DELAY_WR_DATA_CNTRL bound to: 1 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter EARLY_WR_DATA_ADDR bound to: OFF - type: string Parameter ECC bound to: OFF - type: string Parameter MC_ERR_ADDR_WIDTH bound to: 29 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nPHY_WRLAT bound to: 2 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter MC_ERR_LINE_WIDTH bound to: 28 - type: integer Parameter FIFO_WIDTH bound to: 8 - type: integer Parameter FULL_RAM_CNT bound to: 1 - type: integer Parameter REMAINDER bound to: 2 - type: integer Parameter RAM_CNT bound to: 2 - type: integer Parameter RAM_WIDTH bound to: 12 - type: integer INFO: [Synth 8-6157] synthesizing module 'RAM32M' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:70128] Parameter INIT_A bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_B bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_C bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_D bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter IS_WCLK_INVERTED bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'RAM32M' (26#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:70128] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_col_mach' (27#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mc' (28#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_top' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] Parameter TCQ bound to: 100 - type: integer Parameter DDR3_VDD_OP_VOLT bound to: 150 - type: string Parameter AL bound to: 0 - type: string Parameter BANK_WIDTH bound to: 3 - type: integer Parameter BURST_MODE bound to: 8 - type: string Parameter BURST_TYPE bound to: SEQ - type: string Parameter CA_MIRROR bound to: OFF - type: string Parameter CK_WIDTH bound to: 1 - type: integer Parameter CL bound to: 11 - type: integer Parameter COL_WIDTH bound to: 10 - type: integer Parameter CS_WIDTH bound to: 1 - type: integer Parameter CKE_WIDTH bound to: 1 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DM_WIDTH bound to: 4 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter DRAM_WIDTH bound to: 8 - type: integer Parameter MASTER_PHY_CTL bound to: 1 - type: integer Parameter LP_DDR_CK_WIDTH bound to: 2 - type: integer Parameter PHYCTL_CMD_FIFO bound to: FALSE - type: string Parameter DATA_CTL_B0 bound to: 4'b1111 Parameter DATA_CTL_B1 bound to: 4'b0000 Parameter DATA_CTL_B2 bound to: 4'b0000 Parameter DATA_CTL_B3 bound to: 4'b0000 Parameter DATA_CTL_B4 bound to: 4'b0000 Parameter BYTE_LANES_B0 bound to: 4'b1111 Parameter BYTE_LANES_B1 bound to: 4'b1111 Parameter BYTE_LANES_B2 bound to: 4'b0000 Parameter BYTE_LANES_B3 bound to: 4'b0000 Parameter BYTE_LANES_B4 bound to: 4'b0000 Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110001111111110001011111111 Parameter PHY_1_BITLANES bound to: 48'b001111111110111111111100110000010000000000000011 Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011 Parameter ADDR_MAP bound to: 192'b000000000000000100010100000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100100101000100101000000100100111000100100110000100101011 Parameter BANK_MAP bound to: 36'b000100101010000100101001000100100100 Parameter CAS_MAP bound to: 12'b000100100010 Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011 Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010 Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 Parameter PARITY_MAP bound to: 12'b000000000000 Parameter RAS_MAP bound to: 12'b000100100011 Parameter WE_MAP bound to: 12'b000100000001 Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011 Parameter DATA0_MAP bound to: 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000 Parameter DATA1_MAP bound to: 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000 Parameter DATA2_MAP bound to: 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000 Parameter DATA3_MAP bound to: 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111 Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001 Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter PRE_REV3ES bound to: OFF - type: string Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nCS_PER_RANK bound to: 1 - type: integer Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BANK_TYPE bound to: HP_IO - type: string Parameter DATA_IO_PRIM_TYPE bound to: HP_LP - type: string Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter IBUF_LPWR_MODE bound to: OFF - type: string Parameter OUTPUT_DRV bound to: HIGH - type: string Parameter REG_CTRL bound to: OFF - type: string Parameter RTT_NOM bound to: 40 - type: string Parameter RTT_WR bound to: OFF - type: string Parameter tCK bound to: 1250 - type: integer Parameter tRFC bound to: 260000 - type: integer Parameter tREFI bound to: 7800000 - type: integer Parameter DDR2_DQSN_ENABLE bound to: YES - type: string Parameter WRLVL bound to: ON - type: string Parameter DEBUG_PORT bound to: OFF - type: string Parameter RANKS bound to: 1 - type: integer Parameter ODT_WIDTH bound to: 1 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter SLOT_1_CONFIG bound to: 8'b00000000 Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 Parameter CALIB_COL_ADD bound to: 12'b000000000000 Parameter CALIB_BA_ADD bound to: 3'b000 Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string Parameter REFCLK_FREQ bound to: 200.000000 - type: double Parameter USE_CS_PORT bound to: 1 - type: integer Parameter USE_DM_PORT bound to: 1 - type: integer Parameter USE_ODT_PORT bound to: 1 - type: integer Parameter RD_PATH_REG bound to: 0 - type: integer Parameter IDELAY_ADJ bound to: ON - type: string Parameter FINE_PER_BIT bound to: ON - type: string Parameter CENTER_COMP_MODE bound to: ON - type: string Parameter PI_VAL_ADJ bound to: ON - type: string Parameter TAPSPERKCLK bound to: 56 - type: integer Parameter POC_USE_METASTABLE_SAMP bound to: FALSE - type: string Parameter SKIP_CALIB bound to: FALSE - type: string Parameter FPGA_VOLT_TYPE bound to: N - type: string Parameter nSLOTS bound to: 1 - type: integer Parameter CLK_PERIOD bound to: 5000 - type: integer Parameter SIM_INIT_OPTION bound to: NONE - type: string Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter WRLVL_W bound to: ON - type: string Parameter HIGHEST_BANK bound to: 2 - type: integer Parameter HIGHEST_LANE_B0 bound to: 4 - type: integer Parameter HIGHEST_LANE_B1 bound to: 4 - type: integer Parameter HIGHEST_LANE_B2 bound to: 0 - type: integer Parameter HIGHEST_LANE_B3 bound to: 0 - type: integer Parameter HIGHEST_LANE_B4 bound to: 0 - type: integer Parameter HIGHEST_LANE bound to: 8 - type: integer Parameter N_CTL_LANES bound to: 4 - type: integer Parameter CTL_BANK bound to: 3'b001 Parameter CTL_BYTE_LANE bound to: 8'b11100100 Parameter PI_DIV2_INCDEC bound to: FALSE - type: string INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] Parameter TCQ bound to: 100 - type: integer Parameter tCK bound to: 1250 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter DATA_IO_PRIM_TYPE bound to: HP_LP - type: string Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nCS_PER_RANK bound to: 1 - type: integer Parameter BANK_WIDTH bound to: 3 - type: integer Parameter CKE_WIDTH bound to: 1 - type: integer Parameter CS_WIDTH bound to: 1 - type: integer Parameter CK_WIDTH bound to: 1 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DDR2_DQSN_ENABLE bound to: YES - type: string Parameter DM_WIDTH bound to: 4 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter RANKS bound to: 1 - type: integer Parameter ODT_WIDTH bound to: 1 - type: integer Parameter POC_USE_METASTABLE_SAMP bound to: FALSE - type: string Parameter REG_CTRL bound to: OFF - type: string Parameter ROW_WIDTH bound to: 15 - type: integer Parameter USE_CS_PORT bound to: 1 - type: integer Parameter USE_DM_PORT bound to: 1 - type: integer Parameter USE_ODT_PORT bound to: 1 - type: integer Parameter IBUF_LPWR_MODE bound to: OFF - type: string Parameter LP_DDR_CK_WIDTH bound to: 2 - type: integer Parameter PHYCTL_CMD_FIFO bound to: FALSE - type: string Parameter DATA_CTL_B0 bound to: 4'b1111 Parameter DATA_CTL_B1 bound to: 4'b0000 Parameter DATA_CTL_B2 bound to: 4'b0000 Parameter DATA_CTL_B3 bound to: 4'b0000 Parameter DATA_CTL_B4 bound to: 4'b0000 Parameter BYTE_LANES_B0 bound to: 4'b1111 Parameter BYTE_LANES_B1 bound to: 4'b1111 Parameter BYTE_LANES_B2 bound to: 4'b0000 Parameter BYTE_LANES_B3 bound to: 4'b0000 Parameter BYTE_LANES_B4 bound to: 4'b0000 Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110001111111110001011111111 Parameter PHY_1_BITLANES bound to: 48'b001111111110111111111100110000010000000000000011 Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 Parameter HIGHEST_BANK bound to: 2 - type: integer Parameter HIGHEST_LANE bound to: 8 - type: integer Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011 Parameter ADDR_MAP bound to: 192'b000000000000000100010100000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100100101000100101000000100100111000100100110000100101011 Parameter BANK_MAP bound to: 36'b000100101010000100101001000100100100 Parameter CAS_MAP bound to: 12'b000100100010 Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011 Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010 Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 Parameter PARITY_MAP bound to: 12'b000000000000 Parameter RAS_MAP bound to: 12'b000100100011 Parameter WE_MAP bound to: 12'b000100000001 Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011 Parameter DATA0_MAP bound to: 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000 Parameter DATA1_MAP bound to: 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000 Parameter DATA2_MAP bound to: 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000 Parameter DATA3_MAP bound to: 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111 Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001 Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter MASTER_PHY_CTL bound to: 1 - type: integer Parameter DRAM_WIDTH bound to: 8 - type: integer Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter IBUF_LOW_PWR bound to: FALSE - type: string Parameter DQ_PER_DQS bound to: 8 - type: integer Parameter PHASE_PER_CLK bound to: 8 - type: integer Parameter PHASE_DIV bound to: 1 - type: integer Parameter CLK_PERIOD bound to: 5000 - type: integer Parameter FULL_DATA_MAP bound to: 1728'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000 Parameter FULL_MASK_MAP bound to: 216'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001 Parameter TMP_BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000001000000000000000000000000000 Parameter TMP_GENERATE_DDR_CK_MAP bound to: 16'b0011000101000100 Parameter PHY_BITLANES_OUTONLY bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000001000000000001000000000001000000000 Parameter PHY_0_BITLANES_OUTONLY bound to: 48'b001000000000001000000000001000000000001000000000 Parameter PHY_1_BITLANES_OUTONLY bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PHY_2_BITLANES_OUTONLY bound to: 48'b000000000000000000000000000000000000000000000000 Parameter CKE_ODT_RCLK_SELECT_BANK_AUX_ON bound to: 0 - type: integer Parameter CKE_ODT_RCLK_SELECT_LANE_AUX_ON bound to: A - type: string Parameter CKE_ODT_RCLK_SELECT_BANK_AUX_OFF bound to: 1 - type: integer Parameter CKE_ODT_RCLK_SELECT_LANE_AUX_OFF bound to: B - type: string Parameter CKE_ODT_RCLK_SELECT_BANK bound to: 1 - type: integer Parameter CKE_ODT_RCLK_SELECT_LANE bound to: B - type: string Parameter PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter PHY_0_A_PI_FREQ_REF_DIV bound to: NONE - type: string Parameter FREQ_REF_DIV bound to: 1 - type: integer Parameter INT_DELAY bound to: 0.519200 - type: double Parameter HALF_CYCLE_DELAY bound to: 0.500000 - type: double Parameter MC_OCLK_DELAY bound to: 14.540400 - type: double Parameter PHY_0_A_PO_OCLK_DELAY_HW bound to: 29 - type: integer Parameter PHY_0_A_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_0_A_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_0_RD_CMD_OFFSET_0 bound to: 10 - type: integer Parameter PHY_0_RD_CMD_OFFSET_1 bound to: 10 - type: integer Parameter PHY_0_RD_CMD_OFFSET_2 bound to: 10 - type: integer Parameter PHY_0_RD_CMD_OFFSET_3 bound to: 10 - type: integer Parameter PHY_0_WR_CMD_OFFSET_0 bound to: 8 - type: integer Parameter PHY_0_WR_CMD_OFFSET_1 bound to: 8 - type: integer Parameter PHY_0_WR_CMD_OFFSET_2 bound to: 8 - type: integer Parameter PHY_0_WR_CMD_OFFSET_3 bound to: 8 - type: integer Parameter PHY_0_WR_DURATION_0 bound to: 7 - type: integer Parameter PHY_0_WR_DURATION_1 bound to: 7 - type: integer Parameter PHY_0_WR_DURATION_2 bound to: 7 - type: integer Parameter PHY_0_WR_DURATION_3 bound to: 7 - type: integer Parameter CWL_M bound to: 8 - type: integer Parameter PHY_0_CMD_OFFSET bound to: 9 - type: integer Parameter PHY_COUNT_EN bound to: TRUE - type: string INFO: [Synth 8-6157] synthesizing module 'OBUF' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:46314] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-6155] done synthesizing module 'OBUF' (29#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:46314] INFO: [Synth 8-6157] synthesizing module 'OBUFT' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:46607] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DRIVE bound to: 12 - type: integer Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-6155] done synthesizing module 'OBUFT' (30#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:46607] INFO: [Synth 8-6157] synthesizing module 'IOBUF_DCIEN' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:36555] Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: FALSE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SLEW bound to: SLOW - type: string Parameter USE_IBUFDISABLE bound to: TRUE - type: string INFO: [Synth 8-6155] done synthesizing module 'IOBUF_DCIEN' (31#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:36555] INFO: [Synth 8-6157] synthesizing module 'IOBUFDS_DIFF_OUT_DCIEN' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:36394] Parameter DIFF_TERM bound to: FALSE - type: string Parameter DQS_BIAS bound to: TRUE - type: string Parameter IBUF_LOW_PWR bound to: FALSE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter USE_IBUFDISABLE bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'IOBUFDS_DIFF_OUT_DCIEN' (32#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:36394] WARNING: [Synth 8-7071] port 'IBUFDISABLE' of module 'IOBUFDS_DIFF_OUT_DCIEN' is unconnected for instance 'u_iobuf_dqs' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261] WARNING: [Synth 8-7023] instance 'u_iobuf_dqs' of module 'IOBUFDS_DIFF_OUT_DCIEN' has 9 connections declared, but only 8 given [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_pd' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v:70] Parameter POC_USE_METASTABLE_SAMP bound to: FALSE - type: string Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter TCQ bound to: 100 - type: integer INFO: [Synth 8-6157] synthesizing module 'IDDR' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:34934] Parameter DDR_CLK_EDGE bound to: OPPOSITE_EDGE - type: string Parameter INIT_Q1 bound to: 1'b0 Parameter INIT_Q2 bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter SRTYPE bound to: SYNC - type: string INFO: [Synth 8-6155] done synthesizing module 'IDDR' (33#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:34934] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_pd' (34#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v:70] WARNING: [Synth 8-7071] port 'IBUFDISABLE' of module 'IOBUFDS_DIFF_OUT_DCIEN' is unconnected for instance 'u_iobuf_dqs' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261] WARNING: [Synth 8-7023] instance 'u_iobuf_dqs' of module 'IOBUFDS_DIFF_OUT_DCIEN' has 9 connections declared, but only 8 given [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261] WARNING: [Synth 8-7071] port 'IBUFDISABLE' of module 'IOBUFDS_DIFF_OUT_DCIEN' is unconnected for instance 'u_iobuf_dqs' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261] WARNING: [Synth 8-7023] instance 'u_iobuf_dqs' of module 'IOBUFDS_DIFF_OUT_DCIEN' has 9 connections declared, but only 8 given [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261] WARNING: [Synth 8-7071] port 'IBUFDISABLE' of module 'IOBUFDS_DIFF_OUT_DCIEN' is unconnected for instance 'u_iobuf_dqs' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261] WARNING: [Synth 8-7023] instance 'u_iobuf_dqs' of module 'IOBUFDS_DIFF_OUT_DCIEN' has 9 connections declared, but only 8 given [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] Parameter TCQ bound to: 25 - type: integer Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 32 - type: integer Parameter PTR_BITS bound to: 3 - type: integer Parameter ALMOST_FULL_VALUE bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' (35#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_0' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] Parameter TCQ bound to: 25 - type: integer Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 6 - type: integer Parameter PTR_BITS bound to: 3 - type: integer Parameter ALMOST_FULL_VALUE bound to: 3 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' (35#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_1' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_1' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_2' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_2' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] Parameter BYTE_LANES_B0 bound to: 4'b1111 Parameter BYTE_LANES_B1 bound to: 4'b1111 Parameter BYTE_LANES_B2 bound to: 4'b0000 Parameter BYTE_LANES_B3 bound to: 4'b0000 Parameter BYTE_LANES_B4 bound to: 4'b0000 Parameter DATA_CTL_B0 bound to: 4'b1111 Parameter DATA_CTL_B1 bound to: 4'b0000 Parameter DATA_CTL_B2 bound to: 4'b0000 Parameter DATA_CTL_B3 bound to: 4'b0000 Parameter DATA_CTL_B4 bound to: 4'b0000 Parameter RCLK_SELECT_BANK bound to: 1 - type: integer Parameter RCLK_SELECT_LANE bound to: B - type: string Parameter RCLK_SELECT_EDGE bound to: 4'b1111 Parameter GENERATE_DDR_CK_MAP bound to: 16'b0011000101000100 Parameter BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000001000000000000000000000000000 Parameter USE_PRE_POST_FIFO bound to: TRUE - type: string Parameter SYNTHESIS bound to: TRUE - type: string Parameter PO_CTL_COARSE_BYPASS bound to: FALSE - type: string Parameter PI_SEL_CLK_OFFSET bound to: 6 - type: integer Parameter PHYCTL_CMD_FIFO bound to: FALSE - type: string Parameter PHY_CLK_RATIO bound to: 4 - type: integer Parameter PHY_FOUR_WINDOW_CLOCKS bound to: 63 - type: integer Parameter PHY_EVENTS_DELAY bound to: 18 - type: integer Parameter PHY_COUNT_EN bound to: FALSE - type: string Parameter PHY_SYNC_MODE bound to: FALSE - type: string Parameter PHY_DISABLE_SEQ_MATCH bound to: TRUE - type: string Parameter MASTER_PHY_CTL bound to: 1 - type: integer Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110001111111110001011111111 Parameter PHY_0_BITLANES_OUTONLY bound to: 48'b001000000000001000000000001000000000001000000000 Parameter PHY_0_LANE_REMAP bound to: 16'b0011001000010000 Parameter PHY_0_GENERATE_IDELAYCTRL bound to: FALSE - type: string Parameter PHY_0_IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter NUM_DDR_CK bound to: 1 - type: integer Parameter PHY_0_DATA_CTL bound to: 4'b1111 Parameter PHY_0_CMD_OFFSET bound to: 9 - type: integer Parameter PHY_0_RD_CMD_OFFSET_0 bound to: 10 - type: integer Parameter PHY_0_RD_CMD_OFFSET_1 bound to: 10 - type: integer Parameter PHY_0_RD_CMD_OFFSET_2 bound to: 10 - type: integer Parameter PHY_0_RD_CMD_OFFSET_3 bound to: 10 - type: integer Parameter PHY_0_RD_DURATION_0 bound to: 6 - type: integer Parameter PHY_0_RD_DURATION_1 bound to: 6 - type: integer Parameter PHY_0_RD_DURATION_2 bound to: 6 - type: integer Parameter PHY_0_RD_DURATION_3 bound to: 6 - type: integer Parameter PHY_0_WR_CMD_OFFSET_0 bound to: 8 - type: integer Parameter PHY_0_WR_CMD_OFFSET_1 bound to: 8 - type: integer Parameter PHY_0_WR_CMD_OFFSET_2 bound to: 8 - type: integer Parameter PHY_0_WR_CMD_OFFSET_3 bound to: 8 - type: integer Parameter PHY_0_WR_DURATION_0 bound to: 7 - type: integer Parameter PHY_0_WR_DURATION_1 bound to: 7 - type: integer Parameter PHY_0_WR_DURATION_2 bound to: 7 - type: integer Parameter PHY_0_WR_DURATION_3 bound to: 7 - type: integer Parameter PHY_0_AO_WRLVL_EN bound to: 0 - type: integer Parameter PHY_0_AO_TOGGLE bound to: 1 - type: integer Parameter PHY_0_OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter PHY_0_IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter PHY_0_A_PI_FREQ_REF_DIV bound to: NONE - type: string Parameter PHY_0_A_PI_CLKOUT_DIV bound to: 2 - type: integer Parameter PHY_0_A_PO_CLKOUT_DIV bound to: 2 - type: integer Parameter PHY_0_A_BURST_MODE bound to: TRUE - type: string Parameter PHY_0_A_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PHY_0_A_PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PHY_0_A_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_0_B_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_0_C_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_0_D_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_0_A_PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter PHY_0_A_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_0_B_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_0_C_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_0_D_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_0_A_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_0_B_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_0_C_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_0_D_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_0_A_OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter PHY_0_A_OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter PHY_0_B_OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter PHY_0_B_OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter PHY_0_C_OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter PHY_0_C_OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter PHY_0_D_OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter PHY_0_D_OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter PHY_0_A_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter PHY_0_A_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_0_B_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter PHY_0_B_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_0_C_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter PHY_0_C_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_0_D_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter PHY_0_D_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_1_BITLANES bound to: 48'b001111111110111111111100110000010000000000000011 Parameter PHY_1_BITLANES_OUTONLY bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PHY_1_LANE_REMAP bound to: 16'b0011001000010000 Parameter PHY_1_GENERATE_IDELAYCTRL bound to: FALSE - type: string Parameter PHY_1_IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter PHY_1_DATA_CTL bound to: 4'b0000 Parameter PHY_1_CMD_OFFSET bound to: 9 - type: integer Parameter PHY_1_RD_CMD_OFFSET_0 bound to: 10 - type: integer Parameter PHY_1_RD_CMD_OFFSET_1 bound to: 10 - type: integer Parameter PHY_1_RD_CMD_OFFSET_2 bound to: 10 - type: integer Parameter PHY_1_RD_CMD_OFFSET_3 bound to: 10 - type: integer Parameter PHY_1_RD_DURATION_0 bound to: 6 - type: integer Parameter PHY_1_RD_DURATION_1 bound to: 6 - type: integer Parameter PHY_1_RD_DURATION_2 bound to: 6 - type: integer Parameter PHY_1_RD_DURATION_3 bound to: 6 - type: integer Parameter PHY_1_WR_CMD_OFFSET_0 bound to: 8 - type: integer Parameter PHY_1_WR_CMD_OFFSET_1 bound to: 8 - type: integer Parameter PHY_1_WR_CMD_OFFSET_2 bound to: 8 - type: integer Parameter PHY_1_WR_CMD_OFFSET_3 bound to: 8 - type: integer Parameter PHY_1_WR_DURATION_0 bound to: 7 - type: integer Parameter PHY_1_WR_DURATION_1 bound to: 7 - type: integer Parameter PHY_1_WR_DURATION_2 bound to: 7 - type: integer Parameter PHY_1_WR_DURATION_3 bound to: 7 - type: integer Parameter PHY_1_AO_WRLVL_EN bound to: 0 - type: integer Parameter PHY_1_AO_TOGGLE bound to: 1 - type: integer Parameter PHY_1_OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter PHY_1_IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter PHY_1_A_PI_FREQ_REF_DIV bound to: NONE - type: string Parameter PHY_1_A_PI_CLKOUT_DIV bound to: 2 - type: integer Parameter PHY_1_A_PO_CLKOUT_DIV bound to: 2 - type: integer Parameter PHY_1_A_BURST_MODE bound to: TRUE - type: string Parameter PHY_1_A_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PHY_1_A_PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PHY_1_A_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_1_B_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_1_C_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_1_D_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_1_A_PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter PHY_1_A_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter PHY_1_A_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_1_B_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter PHY_1_B_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_1_C_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter PHY_1_C_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_1_D_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter PHY_1_D_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_1_A_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_1_B_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_1_C_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_1_D_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_1_A_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_1_B_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_1_C_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_1_D_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_1_A_OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter PHY_1_A_OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter PHY_1_B_OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter PHY_1_B_OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter PHY_1_C_OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter PHY_1_C_OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter PHY_1_D_OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter PHY_1_D_OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PHY_2_BITLANES_OUTONLY bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PHY_2_LANE_REMAP bound to: 16'b0011001000010000 Parameter PHY_2_GENERATE_IDELAYCTRL bound to: FALSE - type: string Parameter PHY_2_IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter PHY_2_DATA_CTL bound to: 4'b0000 Parameter PHY_2_CMD_OFFSET bound to: 9 - type: integer Parameter PHY_2_RD_CMD_OFFSET_0 bound to: 10 - type: integer Parameter PHY_2_RD_CMD_OFFSET_1 bound to: 10 - type: integer Parameter PHY_2_RD_CMD_OFFSET_2 bound to: 10 - type: integer Parameter PHY_2_RD_CMD_OFFSET_3 bound to: 10 - type: integer Parameter PHY_2_RD_DURATION_0 bound to: 6 - type: integer Parameter PHY_2_RD_DURATION_1 bound to: 6 - type: integer Parameter PHY_2_RD_DURATION_2 bound to: 6 - type: integer Parameter PHY_2_RD_DURATION_3 bound to: 6 - type: integer Parameter PHY_2_WR_CMD_OFFSET_0 bound to: 8 - type: integer Parameter PHY_2_WR_CMD_OFFSET_1 bound to: 8 - type: integer Parameter PHY_2_WR_CMD_OFFSET_2 bound to: 8 - type: integer Parameter PHY_2_WR_CMD_OFFSET_3 bound to: 8 - type: integer Parameter PHY_2_WR_DURATION_0 bound to: 7 - type: integer Parameter PHY_2_WR_DURATION_1 bound to: 7 - type: integer Parameter PHY_2_WR_DURATION_2 bound to: 7 - type: integer Parameter PHY_2_WR_DURATION_3 bound to: 7 - type: integer Parameter PHY_2_AO_WRLVL_EN bound to: 0 - type: integer Parameter PHY_2_AO_TOGGLE bound to: 1 - type: integer Parameter PHY_2_OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter PHY_2_IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter PHY_2_A_PI_FREQ_REF_DIV bound to: NONE - type: string Parameter PHY_2_A_PI_CLKOUT_DIV bound to: 2 - type: integer Parameter PHY_2_A_PO_CLKOUT_DIV bound to: 2 - type: integer Parameter PHY_2_A_BURST_MODE bound to: TRUE - type: string Parameter PHY_2_A_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PHY_2_A_PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PHY_2_A_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_2_B_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_2_C_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_2_D_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_2_A_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_2_B_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_2_C_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_2_D_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter PHY_2_A_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_2_B_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_2_C_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_2_D_PO_OCLK_DELAY bound to: 29 - type: integer Parameter PHY_2_A_PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter PHY_2_A_OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter PHY_2_A_OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter PHY_2_B_OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter PHY_2_B_OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter PHY_2_C_OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter PHY_2_C_OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter PHY_2_D_OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter PHY_2_D_OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter PHY_2_A_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter PHY_2_A_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_2_B_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter PHY_2_B_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_2_C_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter PHY_2_C_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_2_D_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter PHY_2_D_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PHY_0_IS_LAST_BANK bound to: FALSE - type: string Parameter PHY_1_IS_LAST_BANK bound to: FALSE - type: string Parameter PHY_2_IS_LAST_BANK bound to: FALSE - type: string Parameter TCK bound to: 1250 - type: integer Parameter N_LANES bound to: 8 - type: integer Parameter HIGHEST_BANK bound to: 2 - type: integer Parameter HIGHEST_LANE_B0 bound to: 4 - type: integer Parameter HIGHEST_LANE_B1 bound to: 4 - type: integer Parameter HIGHEST_LANE_B2 bound to: 0 - type: integer Parameter HIGHEST_LANE_B3 bound to: 0 - type: integer Parameter HIGHEST_LANE_B4 bound to: 0 - type: integer Parameter HIGHEST_LANE bound to: 8 - type: integer Parameter LP_DDR_CK_WIDTH bound to: 2 - type: integer Parameter GENERATE_SIGNAL_SPLIT bound to: FALSE - type: string Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter IF_ARRAY_MODE bound to: ARRAY_MODE_4_X_4 - type: string Parameter IF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter IF_SLOW_WR_CLK bound to: FALSE - type: string Parameter IF_SLOW_RD_CLK bound to: FALSE - type: string Parameter PHY_MULTI_REGION bound to: TRUE - type: string Parameter RCLK_NEG_EDGE bound to: 3'b000 Parameter RCLK_POS_EDGE bound to: 3'b111 Parameter LP_PHY_0_BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 Parameter LP_PHY_1_BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000001000 Parameter LP_PHY_2_BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 Parameter PC_DATA_OFFSET_RANGE_HI bound to: 22 - type: integer Parameter PC_DATA_OFFSET_RANGE_LO bound to: 17 - type: integer Parameter RCLK_PI_OUTPUT_CLK_SRC bound to: DELAYED_MEM_REF - type: string Parameter DDR_TCK bound to: 1250 - type: integer Parameter FREQ_REF_PERIOD bound to: 1250.000000 - type: double Parameter L_FREQ_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter PO_S3_TAPS bound to: 64 - type: integer Parameter PI_S2_TAPS bound to: 128 - type: integer Parameter PO_S2_TAPS bound to: 128 - type: integer Parameter PI_STG1_INTRINSIC_DELAY bound to: 0.000000 - type: double Parameter PI_STG2_INTRINSIC_DELAY bound to: 744.000000 - type: double Parameter PO_STG1_INTRINSIC_DELAY bound to: 0.000000 - type: double Parameter PO_STG2_FINE_INTRINSIC_DELAY bound to: 769.250000 - type: double Parameter PO_STG2_COARSE_INTRINSIC_DELAY bound to: 511.000000 - type: double Parameter PO_STG2_INTRINSIC_DELAY bound to: 1280.250000 - type: double Parameter PO_S2_TAPS_SIZE bound to: 9.765625 - type: double Parameter PO_CIRC_BUF_META_ZONE bound to: 200.000000 - type: double Parameter PO_CIRC_BUF_EARLY bound to: 1'b0 Parameter PO_CIRC_BUF_OFFSET bound to: 30.250000 - type: double Parameter PO_CIRC_BUF_DELAY bound to: 60 - type: integer Parameter PI_S2_TAPS_SIZE bound to: 9.765625 - type: double Parameter PI_MAX_STG2_DELAY bound to: 615.234375 - type: double Parameter PI_INTRINSIC_DELAY bound to: 744.000000 - type: double Parameter PO_INTRINSIC_DELAY bound to: 1280.250000 - type: double Parameter PO_DELAY bound to: 1866.187500 - type: double Parameter RCLK_BUFIO_DELAY bound to: 1200 - type: integer Parameter RCLK_DELAY_INT bound to: 1944 - type: integer Parameter PO_DELAY_INT bound to: 1866 - type: integer Parameter PI_OFFSET bound to: -78 - type: integer Parameter PI_STG2_DELAY_CAND bound to: 547.000000 - type: double Parameter PI_STG2_DELAY bound to: 547.000000 - type: double Parameter DEFAULT_RCLK_DELAY bound to: 56 - type: integer Parameter LP_RCLK_SELECT_EDGE bound to: 4'b0000 Parameter L_PHY_0_PO_FINE_DELAY bound to: 60 - type: integer Parameter L_PHY_1_PO_FINE_DELAY bound to: 60 - type: integer Parameter L_PHY_2_PO_FINE_DELAY bound to: 60 - type: integer Parameter L_PHY_0_A_PI_FINE_DELAY bound to: 33 - type: integer Parameter L_PHY_0_B_PI_FINE_DELAY bound to: 33 - type: integer Parameter L_PHY_0_C_PI_FINE_DELAY bound to: 33 - type: integer Parameter L_PHY_0_D_PI_FINE_DELAY bound to: 33 - type: integer Parameter L_PHY_1_A_PI_FINE_DELAY bound to: 56 - type: integer Parameter L_PHY_1_B_PI_FINE_DELAY bound to: 56 - type: integer Parameter L_PHY_1_C_PI_FINE_DELAY bound to: 56 - type: integer Parameter L_PHY_1_D_PI_FINE_DELAY bound to: 56 - type: integer Parameter L_PHY_2_A_PI_FINE_DELAY bound to: 33 - type: integer Parameter L_PHY_2_B_PI_FINE_DELAY bound to: 33 - type: integer Parameter L_PHY_2_C_PI_FINE_DELAY bound to: 33 - type: integer Parameter L_PHY_2_D_PI_FINE_DELAY bound to: 33 - type: integer Parameter L_PHY_0_A_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter L_PHY_0_B_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter L_PHY_0_C_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter L_PHY_0_D_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter L_PHY_1_A_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter L_PHY_1_B_PI_OUTPUT_CLK_SRC bound to: DELAYED_MEM_REF - type: string Parameter L_PHY_1_C_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter L_PHY_1_D_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter L_PHY_2_A_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter L_PHY_2_B_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter L_PHY_2_C_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter L_PHY_2_D_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter L_RESET_SELECT_BANK bound to: 1 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] Parameter GENERATE_IDELAYCTRL bound to: FALSE - type: string Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 Parameter NUM_DDR_CK bound to: 1 - type: integer Parameter BYTE_LANES bound to: 4'b1111 Parameter DATA_CTL_N bound to: 4'b1111 Parameter BITLANES bound to: 48'b001111111110001111111110001111111110001011111111 Parameter BITLANES_OUTONLY bound to: 48'b001000000000001000000000001000000000001000000000 Parameter LANE_REMAP bound to: 16'b0011001000010000 Parameter LAST_BANK bound to: FALSE - type: string Parameter USE_PRE_POST_FIFO bound to: TRUE - type: string Parameter RCLK_SELECT_LANE bound to: B - type: string Parameter TCK bound to: 1250.000000 - type: double Parameter SYNTHESIS bound to: TRUE - type: string Parameter PO_CTL_COARSE_BYPASS bound to: FALSE - type: string Parameter PO_FINE_DELAY bound to: 60 - type: integer Parameter PI_SEL_CLK_OFFSET bound to: 6 - type: integer Parameter PC_CLK_RATIO bound to: 4 - type: integer Parameter A_PI_FREQ_REF_DIV bound to: NONE - type: string Parameter A_PI_CLKOUT_DIV bound to: 2 - type: integer Parameter A_PI_BURST_MODE bound to: TRUE - type: string Parameter A_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter A_PI_FINE_DELAY bound to: 33 - type: integer Parameter A_PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter B_PI_FREQ_REF_DIV bound to: NONE - type: string Parameter B_PI_CLKOUT_DIV bound to: 2 - type: integer Parameter B_PI_BURST_MODE bound to: TRUE - type: string Parameter B_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter B_PI_FINE_DELAY bound to: 33 - type: integer Parameter B_PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter C_PI_FREQ_REF_DIV bound to: NONE - type: string Parameter C_PI_CLKOUT_DIV bound to: 2 - type: integer Parameter C_PI_BURST_MODE bound to: TRUE - type: string Parameter C_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter C_PI_FINE_DELAY bound to: 33 - type: integer Parameter C_PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter D_PI_FREQ_REF_DIV bound to: NONE - type: string Parameter D_PI_CLKOUT_DIV bound to: 2 - type: integer Parameter D_PI_BURST_MODE bound to: TRUE - type: string Parameter D_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter D_PI_FINE_DELAY bound to: 33 - type: integer Parameter D_PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter A_PO_CLKOUT_DIV bound to: 2 - type: integer Parameter A_PO_FINE_DELAY bound to: 60 - type: integer Parameter A_PO_COARSE_DELAY bound to: 0 - type: integer Parameter A_PO_OCLK_DELAY bound to: 29 - type: integer Parameter A_PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter A_PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter A_PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter B_PO_CLKOUT_DIV bound to: 2 - type: integer Parameter B_PO_FINE_DELAY bound to: 60 - type: integer Parameter B_PO_COARSE_DELAY bound to: 0 - type: integer Parameter B_PO_OCLK_DELAY bound to: 29 - type: integer Parameter B_PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter B_PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter B_PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter C_PO_CLKOUT_DIV bound to: 2 - type: integer Parameter C_PO_FINE_DELAY bound to: 60 - type: integer Parameter C_PO_COARSE_DELAY bound to: 0 - type: integer Parameter C_PO_OCLK_DELAY bound to: 29 - type: integer Parameter C_PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter C_PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter C_PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter D_PO_CLKOUT_DIV bound to: 2 - type: integer Parameter D_PO_FINE_DELAY bound to: 60 - type: integer Parameter D_PO_COARSE_DELAY bound to: 0 - type: integer Parameter D_PO_OCLK_DELAY bound to: 29 - type: integer Parameter D_PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter D_PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter D_PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter A_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter A_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter B_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter B_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter C_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter C_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter D_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter D_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PC_BURST_MODE bound to: TRUE - type: string Parameter PC_DATA_CTL_N bound to: 4'b1111 Parameter PC_CMD_OFFSET bound to: 9 - type: integer Parameter PC_RD_CMD_OFFSET_0 bound to: 10 - type: integer Parameter PC_RD_CMD_OFFSET_1 bound to: 10 - type: integer Parameter PC_RD_CMD_OFFSET_2 bound to: 10 - type: integer Parameter PC_RD_CMD_OFFSET_3 bound to: 10 - type: integer Parameter PC_CO_DURATION bound to: 1 - type: integer Parameter PC_DI_DURATION bound to: 1 - type: integer Parameter PC_DO_DURATION bound to: 1 - type: integer Parameter PC_RD_DURATION_0 bound to: 6 - type: integer Parameter PC_RD_DURATION_1 bound to: 6 - type: integer Parameter PC_RD_DURATION_2 bound to: 6 - type: integer Parameter PC_RD_DURATION_3 bound to: 6 - type: integer Parameter PC_WR_CMD_OFFSET_0 bound to: 8 - type: integer Parameter PC_WR_CMD_OFFSET_1 bound to: 8 - type: integer Parameter PC_WR_CMD_OFFSET_2 bound to: 8 - type: integer Parameter PC_WR_CMD_OFFSET_3 bound to: 8 - type: integer Parameter PC_WR_DURATION_0 bound to: 7 - type: integer Parameter PC_WR_DURATION_1 bound to: 7 - type: integer Parameter PC_WR_DURATION_2 bound to: 7 - type: integer Parameter PC_WR_DURATION_3 bound to: 7 - type: integer Parameter PC_AO_WRLVL_EN bound to: 0 - type: integer Parameter PC_AO_TOGGLE bound to: 1 - type: integer Parameter PC_FOUR_WINDOW_CLOCKS bound to: 63 - type: integer Parameter PC_EVENTS_DELAY bound to: 18 - type: integer Parameter PC_PHY_COUNT_EN bound to: FALSE - type: string Parameter PC_SYNC_MODE bound to: FALSE - type: string Parameter PC_DISABLE_SEQ_MATCH bound to: TRUE - type: string Parameter PC_MULTI_REGION bound to: TRUE - type: string Parameter A_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter B_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter C_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter D_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter OF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter OF_OUTPUT_DISABLE bound to: TRUE - type: string Parameter OF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter A_OS_DATA_RATE bound to: UNDECLARED - type: string Parameter A_OS_DATA_WIDTH bound to: UNDECLARED - type: string Parameter B_OS_DATA_RATE bound to: UNDECLARED - type: string Parameter B_OS_DATA_WIDTH bound to: UNDECLARED - type: string Parameter C_OS_DATA_RATE bound to: UNDECLARED - type: string Parameter C_OS_DATA_WIDTH bound to: UNDECLARED - type: string Parameter D_OS_DATA_RATE bound to: UNDECLARED - type: string Parameter D_OS_DATA_WIDTH bound to: UNDECLARED - type: string Parameter A_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter B_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter C_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter D_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter IF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter IF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter HIGHEST_LANE bound to: 4 - type: integer Parameter N_CTL_LANES bound to: 0 - type: integer Parameter N_BYTE_LANES bound to: 4 - type: integer Parameter N_DATA_LANES bound to: 4 - type: integer Parameter AUXOUT_WIDTH bound to: 4 - type: integer Parameter LP_DDR_CK_WIDTH bound to: 2 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter DATA_CTL_A bound to: 1'b0 Parameter DATA_CTL_B bound to: 1'b0 Parameter DATA_CTL_C bound to: 1'b0 Parameter DATA_CTL_D bound to: 1'b0 Parameter PRESENT_CTL_A bound to: 1'b0 Parameter PRESENT_CTL_B bound to: 1'b0 Parameter PRESENT_CTL_C bound to: 1'b0 Parameter PRESENT_CTL_D bound to: 1'b0 Parameter PRESENT_DATA_A bound to: 1'b1 Parameter PRESENT_DATA_B bound to: 1'b1 Parameter PRESENT_DATA_C bound to: 1'b1 Parameter PRESENT_DATA_D bound to: 1'b1 Parameter PC_DATA_CTL_A bound to: TRUE - type: string Parameter PC_DATA_CTL_B bound to: TRUE - type: string Parameter PC_DATA_CTL_C bound to: TRUE - type: string Parameter PC_DATA_CTL_D bound to: TRUE - type: string Parameter A_PO_COARSE_BYPASS bound to: FALSE - type: string Parameter B_PO_COARSE_BYPASS bound to: FALSE - type: string Parameter C_PO_COARSE_BYPASS bound to: FALSE - type: string Parameter D_PO_COARSE_BYPASS bound to: FALSE - type: string Parameter IO_A_START bound to: 41 - type: integer Parameter IO_A_END bound to: 40 - type: integer Parameter IO_B_START bound to: 43 - type: integer Parameter IO_B_END bound to: 42 - type: integer Parameter IO_C_START bound to: 45 - type: integer Parameter IO_C_END bound to: 44 - type: integer Parameter IO_D_START bound to: 47 - type: integer Parameter IO_D_END bound to: 46 - type: integer Parameter IO_A_X_START bound to: 41 - type: integer Parameter IO_A_X_END bound to: 40 - type: integer Parameter IO_B_X_START bound to: 43 - type: integer Parameter IO_B_X_END bound to: 42 - type: integer Parameter IO_C_X_START bound to: 45 - type: integer Parameter IO_C_X_END bound to: 44 - type: integer Parameter IO_D_X_START bound to: 47 - type: integer Parameter IO_D_X_END bound to: 46 - type: integer Parameter MSB_BURST_PEND_PO bound to: 3 - type: integer Parameter MSB_BURST_PEND_PI bound to: 7 - type: integer Parameter MSB_RANK_SEL_I bound to: 15 - type: integer Parameter PHASER_CTL_BUS_WIDTH bound to: 16 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] Parameter ABCD bound to: A - type: string Parameter PO_DATA_CTL bound to: TRUE - type: string Parameter BITLANES bound to: 12'b001011111111 Parameter BITLANES_OUTONLY bound to: 12'b001000000000 Parameter BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 Parameter RCLK_SELECT_LANE bound to: B - type: string Parameter PC_CLK_RATIO bound to: 4 - type: integer Parameter USE_PRE_POST_FIFO bound to: TRUE - type: string Parameter OF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter OF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter OF_OUTPUT_DISABLE bound to: FALSE - type: string Parameter OF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter IF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter IF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter IF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter PI_BURST_MODE bound to: TRUE - type: string Parameter PI_CLKOUT_DIV bound to: 2 - type: integer Parameter PI_FREQ_REF_DIV bound to: NONE - type: string Parameter PI_FINE_DELAY bound to: 33 - type: integer Parameter PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PI_SEL_CLK_OFFSET bound to: 6 - type: integer Parameter PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter PO_CLKOUT_DIV bound to: 2 - type: integer Parameter PO_FINE_DELAY bound to: 60 - type: integer Parameter PO_COARSE_BYPASS bound to: FALSE - type: string Parameter PO_COARSE_DELAY bound to: 0 - type: integer Parameter PO_OCLK_DELAY bound to: 29 - type: integer Parameter PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter TCK bound to: 1250.000000 - type: double Parameter SYNTHESIS bound to: TRUE - type: string Parameter BUS_WIDTH bound to: 12 - type: integer Parameter MSB_BURST_PEND_PO bound to: 3 - type: integer Parameter MSB_BURST_PEND_PI bound to: 7 - type: integer Parameter MSB_RANK_SEL_I bound to: 15 - type: integer Parameter PHASER_CTL_BUS_WIDTH bound to: 16 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter PHASER_INDEX bound to: 0 - type: integer Parameter L_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter L_IF_ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter L_OSERDES_DATA_RATE bound to: DDR - type: string Parameter L_OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter L_FREQ_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_MEM_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_PHASE_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter PO_DCD_CORRECTION bound to: ON - type: string Parameter PO_DCD_SETTING bound to: 3'b111 Parameter DQS_AUTO_RECAL bound to: 0 - type: integer Parameter DQS_FIND_PATTERN bound to: 000 - type: string INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] Parameter TCQ bound to: 25 - type: integer Parameter DEPTH bound to: 4 - type: integer Parameter WIDTH bound to: 80 - type: integer Parameter PTR_BITS bound to: 2 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:110] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' (36#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] Parameter TCQ bound to: 25 - type: integer Parameter DEPTH bound to: 9 - type: integer Parameter WIDTH bound to: 80 - type: integer Parameter PTR_BITS bound to: 4 - type: integer Parameter ALMOST_FULL_VALUE bound to: 4 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' (36#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] INFO: [Synth 8-6157] synthesizing module 'PHASER_IN_PHY' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61205] Parameter BURST_MODE bound to: TRUE - type: string Parameter CLKOUT_DIV bound to: 2 - type: integer Parameter DQS_AUTO_RECAL bound to: 0 - type: integer Parameter DQS_BIAS_MODE bound to: FALSE - type: string Parameter DQS_FIND_PATTERN bound to: 3'b000 Parameter FINE_DELAY bound to: 33 - type: integer Parameter FREQ_REF_DIV bound to: NONE - type: string Parameter IS_RST_INVERTED bound to: 1'b0 Parameter MEMREFCLK_PERIOD bound to: 1.250000 - type: double Parameter OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PHASEREFCLK_PERIOD bound to: 1.250000 - type: double Parameter REFCLK_PERIOD bound to: 1.250000 - type: double Parameter SEL_CLK_OFFSET bound to: 6 - type: integer Parameter SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter WR_CYCLES bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'PHASER_IN_PHY' (37#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61205] INFO: [Synth 8-6157] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:36170] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'IN_FIFO' (38#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:36170] INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61342] Parameter CLKOUT_DIV bound to: 2 - type: integer Parameter COARSE_BYPASS bound to: FALSE - type: string Parameter COARSE_DELAY bound to: 0 - type: integer Parameter DATA_CTL_N bound to: TRUE - type: string Parameter DATA_RD_CYCLES bound to: FALSE - type: string Parameter FINE_DELAY bound to: 60 - type: integer Parameter IS_RST_INVERTED bound to: 1'b0 Parameter MEMREFCLK_PERIOD bound to: 1.250000 - type: double Parameter OCLKDELAY_INV bound to: TRUE - type: string Parameter OCLK_DELAY bound to: 29 - type: integer Parameter OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PHASEREFCLK_PERIOD bound to: 1.000000 - type: double Parameter PO bound to: 3'b111 Parameter REFCLK_PERIOD bound to: 1.250000 - type: double Parameter SYNC_IN_DIV_RST bound to: TRUE - type: string INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY' (39#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61342] INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:50506] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter OUTPUT_DISABLE bound to: FALSE - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO' (40#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:50506] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] Parameter BITLANES bound to: 12'b001011111111 Parameter BITLANES_OUTONLY bound to: 12'b001000000000 Parameter PO_DATA_CTL bound to: TRUE - type: string Parameter OSERDES_DATA_RATE bound to: DDR - type: string Parameter OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter TCK bound to: 1250.000000 - type: double Parameter BUS_WIDTH bound to: 12 - type: integer Parameter SYNTHESIS bound to: TRUE - type: string Parameter ISERDES_DQ_DATA_RATE bound to: DDR - type: string Parameter ISERDES_DQ_DATA_WIDTH bound to: 4 - type: integer Parameter ISERDES_DQ_DYN_CLKDIV_INV_EN bound to: FALSE - type: string Parameter ISERDES_DQ_DYN_CLK_INV_EN bound to: FALSE - type: string Parameter ISERDES_DQ_INIT_Q1 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q2 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q3 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q4 bound to: 1'b0 Parameter ISERDES_DQ_INTERFACE_TYPE bound to: MEMORY_DDR3 - type: string Parameter ISERDES_NUM_CE bound to: 2 - type: integer Parameter ISERDES_DQ_IOBDELAY bound to: IFD - type: string Parameter ISERDES_DQ_OFB_USED bound to: FALSE - type: string Parameter ISERDES_DQ_SERDES_MODE bound to: MASTER - type: string Parameter ISERDES_DQ_SRVAL_Q1 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q2 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q3 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q4 bound to: 1'b0 Parameter IDELAY_FINEDELAY_USE bound to: TRUE - type: string Parameter OSERDES_DQ_DATA_RATE_OQ bound to: DDR - type: string Parameter OSERDES_DQ_DATA_RATE_TQ bound to: DDR - type: string Parameter OSERDES_DQ_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter OSERDES_DQ_INIT_OQ bound to: 1'b1 Parameter OSERDES_DQ_INIT_TQ bound to: 1'b1 Parameter OSERDES_DQ_INTERFACE_TYPE bound to: DEFAULT - type: string Parameter OSERDES_DQ_ODELAY_USED bound to: 0 - type: integer Parameter OSERDES_DQ_SERDES_MODE bound to: MASTER - type: string Parameter OSERDES_DQ_SRVAL_OQ bound to: 1'b1 Parameter OSERDES_DQ_SRVAL_TQ bound to: 1'b1 Parameter OSERDES_DQ_TRISTATE_WIDTH bound to: 4 - type: integer Parameter OSERDES_DQS_DATA_RATE_OQ bound to: DDR - type: string Parameter OSERDES_DQS_DATA_RATE_TQ bound to: DDR - type: string Parameter OSERDES_DQS_TRISTATE_WIDTH bound to: 4 - type: integer Parameter OSERDES_DQS_DATA_WIDTH bound to: 4 - type: integer Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter OSERDES_TBYTE_CTL bound to: TRUE - type: string INFO: [Synth 8-6157] synthesizing module 'IDELAYE2_FINEDELAY' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:35111] Parameter CINVCTRL_SEL bound to: FALSE - type: string Parameter DELAY_SRC bound to: IDATAIN - type: string Parameter FINEDELAY bound to: ADD_DLY - type: string Parameter HIGH_PERFORMANCE_MODE bound to: TRUE - type: string Parameter IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAY_VALUE bound to: 0 - type: integer Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_DATAIN_INVERTED bound to: 1'b0 Parameter IS_IDATAIN_INVERTED bound to: 1'b0 Parameter PIPE_SEL bound to: FALSE - type: string Parameter REFCLK_FREQUENCY bound to: 400.000000 - type: double Parameter SIGNAL_PATTERN bound to: DATA - type: string INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2_FINEDELAY' (41#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:35111] INFO: [Synth 8-6157] synthesizing module 'ISERDESE2' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:38616] Parameter DATA_RATE bound to: DDR - type: string Parameter DATA_WIDTH bound to: 4 - type: integer Parameter DYN_CLKDIV_INV_EN bound to: FALSE - type: string Parameter DYN_CLK_INV_EN bound to: FALSE - type: string Parameter INIT_Q1 bound to: 1'b0 Parameter INIT_Q2 bound to: 1'b0 Parameter INIT_Q3 bound to: 1'b0 Parameter INIT_Q4 bound to: 1'b0 Parameter INTERFACE_TYPE bound to: MEMORY_DDR3 - type: string Parameter IOBDELAY bound to: IFD - type: string Parameter IS_CLKB_INVERTED bound to: 1'b0 Parameter IS_CLKDIVP_INVERTED bound to: 1'b0 Parameter IS_CLKDIV_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_OCLKB_INVERTED bound to: 1'b0 Parameter IS_OCLK_INVERTED bound to: 1'b0 Parameter NUM_CE bound to: 2 - type: integer Parameter OFB_USED bound to: FALSE - type: string Parameter SERDES_MODE bound to: MASTER - type: string Parameter SRVAL_Q1 bound to: 1'b0 Parameter SRVAL_Q2 bound to: 1'b0 Parameter SRVAL_Q3 bound to: 1'b0 Parameter SRVAL_Q4 bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'ISERDESE2' (42#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:38616] INFO: [Synth 8-6157] synthesizing module 'OSERDESE2' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:50391] Parameter DATA_RATE_OQ bound to: DDR - type: string Parameter DATA_RATE_TQ bound to: DDR - type: string Parameter DATA_WIDTH bound to: 4 - type: integer Parameter INIT_OQ bound to: 1'b1 Parameter INIT_TQ bound to: 1'b1 Parameter IS_CLKDIV_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_D1_INVERTED bound to: 1'b0 Parameter IS_D2_INVERTED bound to: 1'b0 Parameter IS_D3_INVERTED bound to: 1'b0 Parameter IS_D4_INVERTED bound to: 1'b0 Parameter IS_D5_INVERTED bound to: 1'b0 Parameter IS_D6_INVERTED bound to: 1'b0 Parameter IS_D7_INVERTED bound to: 1'b0 Parameter IS_D8_INVERTED bound to: 1'b0 Parameter IS_T1_INVERTED bound to: 1'b0 Parameter IS_T2_INVERTED bound to: 1'b0 Parameter IS_T3_INVERTED bound to: 1'b0 Parameter IS_T4_INVERTED bound to: 1'b0 Parameter SERDES_MODE bound to: MASTER - type: string Parameter SRVAL_OQ bound to: 1'b1 Parameter SRVAL_TQ bound to: 1'b1 Parameter TBYTE_CTL bound to: TRUE - type: string Parameter TBYTE_SRC bound to: TRUE - type: string Parameter TRISTATE_WIDTH bound to: 4 - type: integer INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2' (43#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:50391] INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized0' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:50391] Parameter DATA_RATE_OQ bound to: DDR - type: string Parameter DATA_RATE_TQ bound to: DDR - type: string Parameter DATA_WIDTH bound to: 4 - type: integer Parameter INIT_OQ bound to: 1'b1 Parameter INIT_TQ bound to: 1'b1 Parameter IS_CLKDIV_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_D1_INVERTED bound to: 1'b0 Parameter IS_D2_INVERTED bound to: 1'b0 Parameter IS_D3_INVERTED bound to: 1'b0 Parameter IS_D4_INVERTED bound to: 1'b0 Parameter IS_D5_INVERTED bound to: 1'b0 Parameter IS_D6_INVERTED bound to: 1'b0 Parameter IS_D7_INVERTED bound to: 1'b0 Parameter IS_D8_INVERTED bound to: 1'b0 Parameter IS_T1_INVERTED bound to: 1'b0 Parameter IS_T2_INVERTED bound to: 1'b0 Parameter IS_T3_INVERTED bound to: 1'b0 Parameter IS_T4_INVERTED bound to: 1'b0 Parameter SERDES_MODE bound to: MASTER - type: string Parameter SRVAL_OQ bound to: 1'b1 Parameter SRVAL_TQ bound to: 1'b1 Parameter TBYTE_CTL bound to: TRUE - type: string Parameter TBYTE_SRC bound to: FALSE - type: string Parameter TRISTATE_WIDTH bound to: 4 - type: integer INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized0' (43#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:50391] INFO: [Synth 8-6157] synthesizing module 'ODDR' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:49784] Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D1_INVERTED bound to: 1'b0 Parameter IS_D2_INVERTED bound to: 1'b0 Parameter SRTYPE bound to: SYNC - type: string INFO: [Synth 8-6155] done synthesizing module 'ODDR' (44#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:49784] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' (45#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane' (46#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] Parameter ABCD bound to: B - type: string Parameter PO_DATA_CTL bound to: TRUE - type: string Parameter BITLANES bound to: 12'b001111111110 Parameter BITLANES_OUTONLY bound to: 12'b001000000000 Parameter BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 Parameter RCLK_SELECT_LANE bound to: B - type: string Parameter PC_CLK_RATIO bound to: 4 - type: integer Parameter USE_PRE_POST_FIFO bound to: TRUE - type: string Parameter OF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter OF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter OF_OUTPUT_DISABLE bound to: FALSE - type: string Parameter OF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter IF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter IF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter IF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter PI_BURST_MODE bound to: TRUE - type: string Parameter PI_CLKOUT_DIV bound to: 2 - type: integer Parameter PI_FREQ_REF_DIV bound to: NONE - type: string Parameter PI_FINE_DELAY bound to: 33 - type: integer Parameter PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PI_SEL_CLK_OFFSET bound to: 6 - type: integer Parameter PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter PO_CLKOUT_DIV bound to: 2 - type: integer Parameter PO_FINE_DELAY bound to: 60 - type: integer Parameter PO_COARSE_BYPASS bound to: FALSE - type: string Parameter PO_COARSE_DELAY bound to: 0 - type: integer Parameter PO_OCLK_DELAY bound to: 29 - type: integer Parameter PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter TCK bound to: 1250.000000 - type: double Parameter SYNTHESIS bound to: TRUE - type: string Parameter BUS_WIDTH bound to: 12 - type: integer Parameter MSB_BURST_PEND_PO bound to: 3 - type: integer Parameter MSB_BURST_PEND_PI bound to: 7 - type: integer Parameter MSB_RANK_SEL_I bound to: 15 - type: integer Parameter PHASER_CTL_BUS_WIDTH bound to: 16 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter PHASER_INDEX bound to: 1 - type: integer Parameter L_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter L_IF_ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter L_OSERDES_DATA_RATE bound to: DDR - type: string Parameter L_OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter L_FREQ_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_MEM_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_PHASE_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter PO_DCD_CORRECTION bound to: ON - type: string Parameter PO_DCD_SETTING bound to: 3'b111 Parameter DQS_AUTO_RECAL bound to: 0 - type: integer Parameter DQS_FIND_PATTERN bound to: 000 - type: string INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] Parameter BITLANES bound to: 12'b001111111110 Parameter BITLANES_OUTONLY bound to: 12'b001000000000 Parameter PO_DATA_CTL bound to: TRUE - type: string Parameter OSERDES_DATA_RATE bound to: DDR - type: string Parameter OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter TCK bound to: 1250.000000 - type: double Parameter BUS_WIDTH bound to: 12 - type: integer Parameter SYNTHESIS bound to: TRUE - type: string Parameter ISERDES_DQ_DATA_RATE bound to: DDR - type: string Parameter ISERDES_DQ_DATA_WIDTH bound to: 4 - type: integer Parameter ISERDES_DQ_DYN_CLKDIV_INV_EN bound to: FALSE - type: string Parameter ISERDES_DQ_DYN_CLK_INV_EN bound to: FALSE - type: string Parameter ISERDES_DQ_INIT_Q1 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q2 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q3 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q4 bound to: 1'b0 Parameter ISERDES_DQ_INTERFACE_TYPE bound to: MEMORY_DDR3 - type: string Parameter ISERDES_NUM_CE bound to: 2 - type: integer Parameter ISERDES_DQ_IOBDELAY bound to: IFD - type: string Parameter ISERDES_DQ_OFB_USED bound to: FALSE - type: string Parameter ISERDES_DQ_SERDES_MODE bound to: MASTER - type: string Parameter ISERDES_DQ_SRVAL_Q1 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q2 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q3 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q4 bound to: 1'b0 Parameter IDELAY_FINEDELAY_USE bound to: TRUE - type: string Parameter OSERDES_DQ_DATA_RATE_OQ bound to: DDR - type: string Parameter OSERDES_DQ_DATA_RATE_TQ bound to: DDR - type: string Parameter OSERDES_DQ_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter OSERDES_DQ_INIT_OQ bound to: 1'b1 Parameter OSERDES_DQ_INIT_TQ bound to: 1'b1 Parameter OSERDES_DQ_INTERFACE_TYPE bound to: DEFAULT - type: string Parameter OSERDES_DQ_ODELAY_USED bound to: 0 - type: integer Parameter OSERDES_DQ_SERDES_MODE bound to: MASTER - type: string Parameter OSERDES_DQ_SRVAL_OQ bound to: 1'b1 Parameter OSERDES_DQ_SRVAL_TQ bound to: 1'b1 Parameter OSERDES_DQ_TRISTATE_WIDTH bound to: 4 - type: integer Parameter OSERDES_DQS_DATA_RATE_OQ bound to: DDR - type: string Parameter OSERDES_DQS_DATA_RATE_TQ bound to: DDR - type: string Parameter OSERDES_DQS_TRISTATE_WIDTH bound to: 4 - type: integer Parameter OSERDES_DQS_DATA_WIDTH bound to: 4 - type: integer Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter OSERDES_TBYTE_CTL bound to: TRUE - type: string INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' (46#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' (46#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] Parameter ABCD bound to: C - type: string Parameter PO_DATA_CTL bound to: TRUE - type: string Parameter BITLANES bound to: 12'b001111111110 Parameter BITLANES_OUTONLY bound to: 12'b001000000000 Parameter BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 Parameter RCLK_SELECT_LANE bound to: B - type: string Parameter PC_CLK_RATIO bound to: 4 - type: integer Parameter USE_PRE_POST_FIFO bound to: TRUE - type: string Parameter OF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter OF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter OF_OUTPUT_DISABLE bound to: FALSE - type: string Parameter OF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter IF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter IF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter IF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter PI_BURST_MODE bound to: TRUE - type: string Parameter PI_CLKOUT_DIV bound to: 2 - type: integer Parameter PI_FREQ_REF_DIV bound to: NONE - type: string Parameter PI_FINE_DELAY bound to: 33 - type: integer Parameter PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PI_SEL_CLK_OFFSET bound to: 6 - type: integer Parameter PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter PO_CLKOUT_DIV bound to: 2 - type: integer Parameter PO_FINE_DELAY bound to: 60 - type: integer Parameter PO_COARSE_BYPASS bound to: FALSE - type: string Parameter PO_COARSE_DELAY bound to: 0 - type: integer Parameter PO_OCLK_DELAY bound to: 29 - type: integer Parameter PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter TCK bound to: 1250.000000 - type: double Parameter SYNTHESIS bound to: TRUE - type: string Parameter BUS_WIDTH bound to: 12 - type: integer Parameter MSB_BURST_PEND_PO bound to: 3 - type: integer Parameter MSB_BURST_PEND_PI bound to: 7 - type: integer Parameter MSB_RANK_SEL_I bound to: 15 - type: integer Parameter PHASER_CTL_BUS_WIDTH bound to: 16 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter PHASER_INDEX bound to: 2 - type: integer Parameter L_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter L_IF_ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter L_OSERDES_DATA_RATE bound to: DDR - type: string Parameter L_OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter L_FREQ_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_MEM_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_PHASE_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter PO_DCD_CORRECTION bound to: ON - type: string Parameter PO_DCD_SETTING bound to: 3'b111 Parameter DQS_AUTO_RECAL bound to: 0 - type: integer Parameter DQS_FIND_PATTERN bound to: 000 - type: string INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' (46#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] Parameter ABCD bound to: D - type: string Parameter PO_DATA_CTL bound to: TRUE - type: string Parameter BITLANES bound to: 12'b001111111110 Parameter BITLANES_OUTONLY bound to: 12'b001000000000 Parameter BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000000000 Parameter RCLK_SELECT_LANE bound to: B - type: string Parameter PC_CLK_RATIO bound to: 4 - type: integer Parameter USE_PRE_POST_FIFO bound to: TRUE - type: string Parameter OF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter OF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter OF_OUTPUT_DISABLE bound to: FALSE - type: string Parameter OF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter IF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter IF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter IF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter PI_BURST_MODE bound to: TRUE - type: string Parameter PI_CLKOUT_DIV bound to: 2 - type: integer Parameter PI_FREQ_REF_DIV bound to: NONE - type: string Parameter PI_FINE_DELAY bound to: 33 - type: integer Parameter PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PI_SEL_CLK_OFFSET bound to: 6 - type: integer Parameter PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter PO_CLKOUT_DIV bound to: 2 - type: integer Parameter PO_FINE_DELAY bound to: 60 - type: integer Parameter PO_COARSE_BYPASS bound to: FALSE - type: string Parameter PO_COARSE_DELAY bound to: 0 - type: integer Parameter PO_OCLK_DELAY bound to: 29 - type: integer Parameter PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter TCK bound to: 1250.000000 - type: double Parameter SYNTHESIS bound to: TRUE - type: string Parameter BUS_WIDTH bound to: 12 - type: integer Parameter MSB_BURST_PEND_PO bound to: 3 - type: integer Parameter MSB_BURST_PEND_PI bound to: 7 - type: integer Parameter MSB_RANK_SEL_I bound to: 15 - type: integer Parameter PHASER_CTL_BUS_WIDTH bound to: 16 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter PHASER_INDEX bound to: 3 - type: integer Parameter L_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter L_IF_ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter L_OSERDES_DATA_RATE bound to: DDR - type: string Parameter L_OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter L_FREQ_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_MEM_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_PHASE_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter PO_DCD_CORRECTION bound to: ON - type: string Parameter PO_DCD_SETTING bound to: 3'b111 Parameter DQS_AUTO_RECAL bound to: 0 - type: integer Parameter DQS_FIND_PATTERN bound to: 000 - type: string INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' (46#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1344] INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (47#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:1344] INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61433] Parameter AO_TOGGLE bound to: 1 - type: integer Parameter AO_WRLVL_EN bound to: 0 - type: integer Parameter BURST_MODE bound to: TRUE - type: string Parameter CLK_RATIO bound to: 4 - type: integer Parameter CMD_OFFSET bound to: 9 - type: integer Parameter CO_DURATION bound to: 1 - type: integer Parameter DATA_CTL_A_N bound to: TRUE - type: string Parameter DATA_CTL_B_N bound to: TRUE - type: string Parameter DATA_CTL_C_N bound to: TRUE - type: string Parameter DATA_CTL_D_N bound to: TRUE - type: string Parameter DISABLE_SEQ_MATCH bound to: TRUE - type: string Parameter DI_DURATION bound to: 1 - type: integer Parameter DO_DURATION bound to: 1 - type: integer Parameter EVENTS_DELAY bound to: 18 - type: integer Parameter FOUR_WINDOW_CLOCKS bound to: 63 - type: integer Parameter MULTI_REGION bound to: TRUE - type: string Parameter PHY_COUNT_ENABLE bound to: FALSE - type: string Parameter RD_CMD_OFFSET_0 bound to: 10 - type: integer Parameter RD_CMD_OFFSET_1 bound to: 10 - type: integer Parameter RD_CMD_OFFSET_2 bound to: 10 - type: integer Parameter RD_CMD_OFFSET_3 bound to: 10 - type: integer Parameter RD_DURATION_0 bound to: 6 - type: integer Parameter RD_DURATION_1 bound to: 6 - type: integer Parameter RD_DURATION_2 bound to: 6 - type: integer Parameter RD_DURATION_3 bound to: 6 - type: integer Parameter SYNC_MODE bound to: FALSE - type: string Parameter WR_CMD_OFFSET_0 bound to: 8 - type: integer Parameter WR_CMD_OFFSET_1 bound to: 8 - type: integer Parameter WR_CMD_OFFSET_2 bound to: 8 - type: integer Parameter WR_CMD_OFFSET_3 bound to: 8 - type: integer Parameter WR_DURATION_0 bound to: 7 - type: integer Parameter WR_DURATION_1 bound to: 7 - type: integer Parameter WR_DURATION_2 bound to: 7 - type: integer Parameter WR_DURATION_3 bound to: 7 - type: integer INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL' (48#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61433] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557] INFO: [Synth 8-6157] synthesizing module 'PHASER_REF' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61417] Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'PHASER_REF' (49#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61417] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' (50#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes__parameterized0' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] Parameter GENERATE_IDELAYCTRL bound to: FALSE - type: string Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000001000 Parameter NUM_DDR_CK bound to: 1 - type: integer Parameter BYTE_LANES bound to: 4'b1111 Parameter DATA_CTL_N bound to: 4'b0000 Parameter BITLANES bound to: 48'b001111111110111111111100110000010000000000000011 Parameter BITLANES_OUTONLY bound to: 48'b000000000000000000000000000000000000000000000000 Parameter LANE_REMAP bound to: 16'b0011001000010000 Parameter LAST_BANK bound to: FALSE - type: string Parameter USE_PRE_POST_FIFO bound to: TRUE - type: string Parameter RCLK_SELECT_LANE bound to: B - type: string Parameter TCK bound to: 1250.000000 - type: double Parameter SYNTHESIS bound to: TRUE - type: string Parameter PO_CTL_COARSE_BYPASS bound to: FALSE - type: string Parameter PO_FINE_DELAY bound to: 60 - type: integer Parameter PI_SEL_CLK_OFFSET bound to: 6 - type: integer Parameter PC_CLK_RATIO bound to: 4 - type: integer Parameter A_PI_FREQ_REF_DIV bound to: NONE - type: string Parameter A_PI_CLKOUT_DIV bound to: 2 - type: integer Parameter A_PI_BURST_MODE bound to: TRUE - type: string Parameter A_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter A_PI_FINE_DELAY bound to: 56 - type: integer Parameter A_PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter B_PI_FREQ_REF_DIV bound to: NONE - type: string Parameter B_PI_CLKOUT_DIV bound to: 2 - type: integer Parameter B_PI_BURST_MODE bound to: TRUE - type: string Parameter B_PI_OUTPUT_CLK_SRC bound to: DELAYED_MEM_REF - type: string Parameter B_PI_FINE_DELAY bound to: 56 - type: integer Parameter B_PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter C_PI_FREQ_REF_DIV bound to: NONE - type: string Parameter C_PI_CLKOUT_DIV bound to: 2 - type: integer Parameter C_PI_BURST_MODE bound to: TRUE - type: string Parameter C_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter C_PI_FINE_DELAY bound to: 56 - type: integer Parameter C_PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter D_PI_FREQ_REF_DIV bound to: NONE - type: string Parameter D_PI_CLKOUT_DIV bound to: 2 - type: integer Parameter D_PI_BURST_MODE bound to: TRUE - type: string Parameter D_PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter D_PI_FINE_DELAY bound to: 56 - type: integer Parameter D_PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter A_PO_CLKOUT_DIV bound to: 4 - type: integer Parameter A_PO_FINE_DELAY bound to: 60 - type: integer Parameter A_PO_COARSE_DELAY bound to: 0 - type: integer Parameter A_PO_OCLK_DELAY bound to: 29 - type: integer Parameter A_PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter A_PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter A_PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter B_PO_CLKOUT_DIV bound to: 4 - type: integer Parameter B_PO_FINE_DELAY bound to: 60 - type: integer Parameter B_PO_COARSE_DELAY bound to: 0 - type: integer Parameter B_PO_OCLK_DELAY bound to: 29 - type: integer Parameter B_PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter B_PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter B_PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter C_PO_CLKOUT_DIV bound to: 4 - type: integer Parameter C_PO_FINE_DELAY bound to: 60 - type: integer Parameter C_PO_COARSE_DELAY bound to: 0 - type: integer Parameter C_PO_OCLK_DELAY bound to: 29 - type: integer Parameter C_PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter C_PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter C_PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter D_PO_CLKOUT_DIV bound to: 4 - type: integer Parameter D_PO_FINE_DELAY bound to: 60 - type: integer Parameter D_PO_COARSE_DELAY bound to: 0 - type: integer Parameter D_PO_OCLK_DELAY bound to: 29 - type: integer Parameter D_PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter D_PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter D_PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter A_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter A_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter B_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter B_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter C_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter C_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter D_IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter D_IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter PC_BURST_MODE bound to: TRUE - type: string Parameter PC_DATA_CTL_N bound to: 4'b0000 Parameter PC_CMD_OFFSET bound to: 9 - type: integer Parameter PC_RD_CMD_OFFSET_0 bound to: 10 - type: integer Parameter PC_RD_CMD_OFFSET_1 bound to: 10 - type: integer Parameter PC_RD_CMD_OFFSET_2 bound to: 10 - type: integer Parameter PC_RD_CMD_OFFSET_3 bound to: 10 - type: integer Parameter PC_CO_DURATION bound to: 1 - type: integer Parameter PC_DI_DURATION bound to: 1 - type: integer Parameter PC_DO_DURATION bound to: 1 - type: integer Parameter PC_RD_DURATION_0 bound to: 6 - type: integer Parameter PC_RD_DURATION_1 bound to: 6 - type: integer Parameter PC_RD_DURATION_2 bound to: 6 - type: integer Parameter PC_RD_DURATION_3 bound to: 6 - type: integer Parameter PC_WR_CMD_OFFSET_0 bound to: 8 - type: integer Parameter PC_WR_CMD_OFFSET_1 bound to: 8 - type: integer Parameter PC_WR_CMD_OFFSET_2 bound to: 8 - type: integer Parameter PC_WR_CMD_OFFSET_3 bound to: 8 - type: integer Parameter PC_WR_DURATION_0 bound to: 7 - type: integer Parameter PC_WR_DURATION_1 bound to: 7 - type: integer Parameter PC_WR_DURATION_2 bound to: 7 - type: integer Parameter PC_WR_DURATION_3 bound to: 7 - type: integer Parameter PC_AO_WRLVL_EN bound to: 0 - type: integer Parameter PC_AO_TOGGLE bound to: 1 - type: integer Parameter PC_FOUR_WINDOW_CLOCKS bound to: 63 - type: integer Parameter PC_EVENTS_DELAY bound to: 18 - type: integer Parameter PC_PHY_COUNT_EN bound to: FALSE - type: string Parameter PC_SYNC_MODE bound to: FALSE - type: string Parameter PC_DISABLE_SEQ_MATCH bound to: TRUE - type: string Parameter PC_MULTI_REGION bound to: TRUE - type: string Parameter A_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter B_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter C_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter D_OF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter OF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter OF_OUTPUT_DISABLE bound to: TRUE - type: string Parameter OF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter A_OS_DATA_RATE bound to: UNDECLARED - type: string Parameter A_OS_DATA_WIDTH bound to: UNDECLARED - type: string Parameter B_OS_DATA_RATE bound to: UNDECLARED - type: string Parameter B_OS_DATA_WIDTH bound to: UNDECLARED - type: string Parameter C_OS_DATA_RATE bound to: UNDECLARED - type: string Parameter C_OS_DATA_WIDTH bound to: UNDECLARED - type: string Parameter D_OS_DATA_RATE bound to: UNDECLARED - type: string Parameter D_OS_DATA_WIDTH bound to: UNDECLARED - type: string Parameter A_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter B_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter C_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter D_IF_ARRAY_MODE bound to: ARRAY_MODE_8_X_4 - type: string Parameter IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter IF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter IF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter HIGHEST_LANE bound to: 4 - type: integer Parameter N_CTL_LANES bound to: 4 - type: integer Parameter N_BYTE_LANES bound to: 4 - type: integer Parameter N_DATA_LANES bound to: 0 - type: integer Parameter AUXOUT_WIDTH bound to: 4 - type: integer Parameter LP_DDR_CK_WIDTH bound to: 2 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter DATA_CTL_A bound to: 1'b1 Parameter DATA_CTL_B bound to: 1'b1 Parameter DATA_CTL_C bound to: 1'b1 Parameter DATA_CTL_D bound to: 1'b1 Parameter PRESENT_CTL_A bound to: 1'b1 Parameter PRESENT_CTL_B bound to: 1'b1 Parameter PRESENT_CTL_C bound to: 1'b1 Parameter PRESENT_CTL_D bound to: 1'b1 Parameter PRESENT_DATA_A bound to: 1'b0 Parameter PRESENT_DATA_B bound to: 1'b0 Parameter PRESENT_DATA_C bound to: 1'b0 Parameter PRESENT_DATA_D bound to: 1'b0 Parameter PC_DATA_CTL_A bound to: FALSE - type: string Parameter PC_DATA_CTL_B bound to: FALSE - type: string Parameter PC_DATA_CTL_C bound to: FALSE - type: string Parameter PC_DATA_CTL_D bound to: FALSE - type: string Parameter A_PO_COARSE_BYPASS bound to: FALSE - type: string Parameter B_PO_COARSE_BYPASS bound to: FALSE - type: string Parameter C_PO_COARSE_BYPASS bound to: FALSE - type: string Parameter D_PO_COARSE_BYPASS bound to: FALSE - type: string Parameter IO_A_START bound to: 41 - type: integer Parameter IO_A_END bound to: 40 - type: integer Parameter IO_B_START bound to: 43 - type: integer Parameter IO_B_END bound to: 42 - type: integer Parameter IO_C_START bound to: 45 - type: integer Parameter IO_C_END bound to: 44 - type: integer Parameter IO_D_START bound to: 47 - type: integer Parameter IO_D_END bound to: 46 - type: integer Parameter IO_A_X_START bound to: 41 - type: integer Parameter IO_A_X_END bound to: 40 - type: integer Parameter IO_B_X_START bound to: 43 - type: integer Parameter IO_B_X_END bound to: 42 - type: integer Parameter IO_C_X_START bound to: 45 - type: integer Parameter IO_C_X_END bound to: 44 - type: integer Parameter IO_D_X_START bound to: 47 - type: integer Parameter IO_D_X_END bound to: 46 - type: integer Parameter MSB_BURST_PEND_PO bound to: 3 - type: integer Parameter MSB_BURST_PEND_PI bound to: 7 - type: integer Parameter MSB_RANK_SEL_I bound to: 15 - type: integer Parameter PHASER_CTL_BUS_WIDTH bound to: 16 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized3' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] Parameter ABCD bound to: A - type: string Parameter PO_DATA_CTL bound to: FALSE - type: string Parameter BITLANES bound to: 12'b000000000011 Parameter BITLANES_OUTONLY bound to: 12'b000000000000 Parameter BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000001000 Parameter RCLK_SELECT_LANE bound to: B - type: string Parameter PC_CLK_RATIO bound to: 4 - type: integer Parameter USE_PRE_POST_FIFO bound to: TRUE - type: string Parameter OF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter OF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter OF_OUTPUT_DISABLE bound to: FALSE - type: string Parameter OF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter IF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter IF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter IF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter PI_BURST_MODE bound to: TRUE - type: string Parameter PI_CLKOUT_DIV bound to: 2 - type: integer Parameter PI_FREQ_REF_DIV bound to: NONE - type: string Parameter PI_FINE_DELAY bound to: 56 - type: integer Parameter PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PI_SEL_CLK_OFFSET bound to: 6 - type: integer Parameter PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter PO_CLKOUT_DIV bound to: 4 - type: integer Parameter PO_FINE_DELAY bound to: 60 - type: integer Parameter PO_COARSE_BYPASS bound to: FALSE - type: string Parameter PO_COARSE_DELAY bound to: 0 - type: integer Parameter PO_OCLK_DELAY bound to: 29 - type: integer Parameter PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter TCK bound to: 1250.000000 - type: double Parameter SYNTHESIS bound to: TRUE - type: string Parameter BUS_WIDTH bound to: 12 - type: integer Parameter MSB_BURST_PEND_PO bound to: 3 - type: integer Parameter MSB_BURST_PEND_PI bound to: 7 - type: integer Parameter MSB_RANK_SEL_I bound to: 15 - type: integer Parameter PHASER_CTL_BUS_WIDTH bound to: 16 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter PHASER_INDEX bound to: 0 - type: integer Parameter L_OF_ARRAY_MODE bound to: ARRAY_MODE_4_X_4 - type: string Parameter L_IF_ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter L_OSERDES_DATA_RATE bound to: SDR - type: string Parameter L_OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter L_FREQ_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_MEM_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_PHASE_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter PO_DCD_CORRECTION bound to: ON - type: string Parameter PO_DCD_SETTING bound to: 3'b111 Parameter DQS_AUTO_RECAL bound to: 0 - type: integer Parameter DQS_FIND_PATTERN bound to: 000 - type: string INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY__parameterized0' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61342] Parameter CLKOUT_DIV bound to: 4 - type: integer Parameter COARSE_BYPASS bound to: FALSE - type: string Parameter COARSE_DELAY bound to: 0 - type: integer Parameter DATA_CTL_N bound to: FALSE - type: string Parameter DATA_RD_CYCLES bound to: FALSE - type: string Parameter FINE_DELAY bound to: 60 - type: integer Parameter IS_RST_INVERTED bound to: 1'b0 Parameter MEMREFCLK_PERIOD bound to: 1.250000 - type: double Parameter OCLKDELAY_INV bound to: TRUE - type: string Parameter OCLK_DELAY bound to: 29 - type: integer Parameter OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PHASEREFCLK_PERIOD bound to: 1.000000 - type: double Parameter PO bound to: 3'b111 Parameter REFCLK_PERIOD bound to: 1.250000 - type: double Parameter SYNC_IN_DIV_RST bound to: TRUE - type: string INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY__parameterized0' (50#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61342] INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO__parameterized0' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:50506] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_4 - type: string Parameter OUTPUT_DISABLE bound to: FALSE - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO__parameterized0' (50#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:50506] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] Parameter BITLANES bound to: 12'b000000000011 Parameter BITLANES_OUTONLY bound to: 12'b000000000000 Parameter PO_DATA_CTL bound to: FALSE - type: string Parameter OSERDES_DATA_RATE bound to: SDR - type: string Parameter OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter TCK bound to: 1250.000000 - type: double Parameter BUS_WIDTH bound to: 12 - type: integer Parameter SYNTHESIS bound to: TRUE - type: string Parameter ISERDES_DQ_DATA_RATE bound to: DDR - type: string Parameter ISERDES_DQ_DATA_WIDTH bound to: 4 - type: integer Parameter ISERDES_DQ_DYN_CLKDIV_INV_EN bound to: FALSE - type: string Parameter ISERDES_DQ_DYN_CLK_INV_EN bound to: FALSE - type: string Parameter ISERDES_DQ_INIT_Q1 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q2 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q3 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q4 bound to: 1'b0 Parameter ISERDES_DQ_INTERFACE_TYPE bound to: MEMORY_DDR3 - type: string Parameter ISERDES_NUM_CE bound to: 2 - type: integer Parameter ISERDES_DQ_IOBDELAY bound to: IFD - type: string Parameter ISERDES_DQ_OFB_USED bound to: FALSE - type: string Parameter ISERDES_DQ_SERDES_MODE bound to: MASTER - type: string Parameter ISERDES_DQ_SRVAL_Q1 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q2 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q3 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q4 bound to: 1'b0 Parameter IDELAY_FINEDELAY_USE bound to: TRUE - type: string Parameter OSERDES_DQ_DATA_RATE_OQ bound to: SDR - type: string Parameter OSERDES_DQ_DATA_RATE_TQ bound to: SDR - type: string Parameter OSERDES_DQ_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter OSERDES_DQ_INIT_OQ bound to: 1'b1 Parameter OSERDES_DQ_INIT_TQ bound to: 1'b1 Parameter OSERDES_DQ_INTERFACE_TYPE bound to: DEFAULT - type: string Parameter OSERDES_DQ_ODELAY_USED bound to: 0 - type: integer Parameter OSERDES_DQ_SERDES_MODE bound to: MASTER - type: string Parameter OSERDES_DQ_SRVAL_OQ bound to: 1'b1 Parameter OSERDES_DQ_SRVAL_TQ bound to: 1'b1 Parameter OSERDES_DQ_TRISTATE_WIDTH bound to: 1 - type: integer Parameter OSERDES_DQS_DATA_RATE_OQ bound to: DDR - type: string Parameter OSERDES_DQS_DATA_RATE_TQ bound to: DDR - type: string Parameter OSERDES_DQS_TRISTATE_WIDTH bound to: 4 - type: integer Parameter OSERDES_DQS_DATA_WIDTH bound to: 4 - type: integer Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter OSERDES_TBYTE_CTL bound to: TRUE - type: string INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized1' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:50391] Parameter DATA_RATE_OQ bound to: SDR - type: string Parameter DATA_RATE_TQ bound to: SDR - type: string Parameter DATA_WIDTH bound to: 4 - type: integer Parameter INIT_OQ bound to: 1'b0 Parameter INIT_TQ bound to: 1'b1 Parameter IS_CLKDIV_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_D1_INVERTED bound to: 1'b0 Parameter IS_D2_INVERTED bound to: 1'b0 Parameter IS_D3_INVERTED bound to: 1'b0 Parameter IS_D4_INVERTED bound to: 1'b0 Parameter IS_D5_INVERTED bound to: 1'b0 Parameter IS_D6_INVERTED bound to: 1'b0 Parameter IS_D7_INVERTED bound to: 1'b0 Parameter IS_D8_INVERTED bound to: 1'b0 Parameter IS_T1_INVERTED bound to: 1'b0 Parameter IS_T2_INVERTED bound to: 1'b0 Parameter IS_T3_INVERTED bound to: 1'b0 Parameter IS_T4_INVERTED bound to: 1'b0 Parameter SERDES_MODE bound to: MASTER - type: string Parameter SRVAL_OQ bound to: 1'b0 Parameter SRVAL_TQ bound to: 1'b1 Parameter TBYTE_CTL bound to: FALSE - type: string Parameter TBYTE_SRC bound to: FALSE - type: string Parameter TRISTATE_WIDTH bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized1' (50#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:50391] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' (50#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized3' (50#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized4' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] Parameter ABCD bound to: B - type: string Parameter PO_DATA_CTL bound to: FALSE - type: string Parameter BITLANES bound to: 12'b110000010000 Parameter BITLANES_OUTONLY bound to: 12'b000000000000 Parameter BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000001000 Parameter RCLK_SELECT_LANE bound to: B - type: string Parameter PC_CLK_RATIO bound to: 4 - type: integer Parameter USE_PRE_POST_FIFO bound to: TRUE - type: string Parameter OF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter OF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter OF_OUTPUT_DISABLE bound to: FALSE - type: string Parameter OF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter IF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter IF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter IF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter PI_BURST_MODE bound to: TRUE - type: string Parameter PI_CLKOUT_DIV bound to: 2 - type: integer Parameter PI_FREQ_REF_DIV bound to: NONE - type: string Parameter PI_FINE_DELAY bound to: 56 - type: integer Parameter PI_OUTPUT_CLK_SRC bound to: DELAYED_MEM_REF - type: string Parameter PI_SEL_CLK_OFFSET bound to: 6 - type: integer Parameter PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter PO_CLKOUT_DIV bound to: 4 - type: integer Parameter PO_FINE_DELAY bound to: 60 - type: integer Parameter PO_COARSE_BYPASS bound to: FALSE - type: string Parameter PO_COARSE_DELAY bound to: 0 - type: integer Parameter PO_OCLK_DELAY bound to: 29 - type: integer Parameter PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter TCK bound to: 1250.000000 - type: double Parameter SYNTHESIS bound to: TRUE - type: string Parameter BUS_WIDTH bound to: 12 - type: integer Parameter MSB_BURST_PEND_PO bound to: 3 - type: integer Parameter MSB_BURST_PEND_PI bound to: 7 - type: integer Parameter MSB_RANK_SEL_I bound to: 15 - type: integer Parameter PHASER_CTL_BUS_WIDTH bound to: 16 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter PHASER_INDEX bound to: 1 - type: integer Parameter L_OF_ARRAY_MODE bound to: ARRAY_MODE_4_X_4 - type: string Parameter L_IF_ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter L_OSERDES_DATA_RATE bound to: SDR - type: string Parameter L_OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter L_FREQ_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_MEM_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_PHASE_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter PO_DCD_CORRECTION bound to: ON - type: string Parameter PO_DCD_SETTING bound to: 3'b111 Parameter DQS_AUTO_RECAL bound to: 0 - type: integer Parameter DQS_FIND_PATTERN bound to: 000 - type: string INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized2' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] Parameter BITLANES bound to: 12'b110000010000 Parameter BITLANES_OUTONLY bound to: 12'b000000000000 Parameter PO_DATA_CTL bound to: FALSE - type: string Parameter OSERDES_DATA_RATE bound to: SDR - type: string Parameter OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter TCK bound to: 1250.000000 - type: double Parameter BUS_WIDTH bound to: 12 - type: integer Parameter SYNTHESIS bound to: TRUE - type: string Parameter ISERDES_DQ_DATA_RATE bound to: DDR - type: string Parameter ISERDES_DQ_DATA_WIDTH bound to: 4 - type: integer Parameter ISERDES_DQ_DYN_CLKDIV_INV_EN bound to: FALSE - type: string Parameter ISERDES_DQ_DYN_CLK_INV_EN bound to: FALSE - type: string Parameter ISERDES_DQ_INIT_Q1 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q2 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q3 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q4 bound to: 1'b0 Parameter ISERDES_DQ_INTERFACE_TYPE bound to: MEMORY_DDR3 - type: string Parameter ISERDES_NUM_CE bound to: 2 - type: integer Parameter ISERDES_DQ_IOBDELAY bound to: IFD - type: string Parameter ISERDES_DQ_OFB_USED bound to: FALSE - type: string Parameter ISERDES_DQ_SERDES_MODE bound to: MASTER - type: string Parameter ISERDES_DQ_SRVAL_Q1 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q2 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q3 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q4 bound to: 1'b0 Parameter IDELAY_FINEDELAY_USE bound to: TRUE - type: string Parameter OSERDES_DQ_DATA_RATE_OQ bound to: SDR - type: string Parameter OSERDES_DQ_DATA_RATE_TQ bound to: SDR - type: string Parameter OSERDES_DQ_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter OSERDES_DQ_INIT_OQ bound to: 1'b1 Parameter OSERDES_DQ_INIT_TQ bound to: 1'b1 Parameter OSERDES_DQ_INTERFACE_TYPE bound to: DEFAULT - type: string Parameter OSERDES_DQ_ODELAY_USED bound to: 0 - type: integer Parameter OSERDES_DQ_SERDES_MODE bound to: MASTER - type: string Parameter OSERDES_DQ_SRVAL_OQ bound to: 1'b1 Parameter OSERDES_DQ_SRVAL_TQ bound to: 1'b1 Parameter OSERDES_DQ_TRISTATE_WIDTH bound to: 1 - type: integer Parameter OSERDES_DQS_DATA_RATE_OQ bound to: DDR - type: string Parameter OSERDES_DQS_DATA_RATE_TQ bound to: DDR - type: string Parameter OSERDES_DQS_TRISTATE_WIDTH bound to: 4 - type: integer Parameter OSERDES_DQS_DATA_WIDTH bound to: 4 - type: integer Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter OSERDES_TBYTE_CTL bound to: TRUE - type: string INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized2' (50#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized4' (50#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized5' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] Parameter ABCD bound to: C - type: string Parameter PO_DATA_CTL bound to: FALSE - type: string Parameter BITLANES bound to: 12'b111111111100 Parameter BITLANES_OUTONLY bound to: 12'b000000000000 Parameter BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000001000 Parameter RCLK_SELECT_LANE bound to: B - type: string Parameter PC_CLK_RATIO bound to: 4 - type: integer Parameter USE_PRE_POST_FIFO bound to: TRUE - type: string Parameter OF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter OF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter OF_OUTPUT_DISABLE bound to: FALSE - type: string Parameter OF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter IF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter IF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter IF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter PI_BURST_MODE bound to: TRUE - type: string Parameter PI_CLKOUT_DIV bound to: 2 - type: integer Parameter PI_FREQ_REF_DIV bound to: NONE - type: string Parameter PI_FINE_DELAY bound to: 56 - type: integer Parameter PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PI_SEL_CLK_OFFSET bound to: 6 - type: integer Parameter PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter PO_CLKOUT_DIV bound to: 4 - type: integer Parameter PO_FINE_DELAY bound to: 60 - type: integer Parameter PO_COARSE_BYPASS bound to: FALSE - type: string Parameter PO_COARSE_DELAY bound to: 0 - type: integer Parameter PO_OCLK_DELAY bound to: 29 - type: integer Parameter PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter TCK bound to: 1250.000000 - type: double Parameter SYNTHESIS bound to: TRUE - type: string Parameter BUS_WIDTH bound to: 12 - type: integer Parameter MSB_BURST_PEND_PO bound to: 3 - type: integer Parameter MSB_BURST_PEND_PI bound to: 7 - type: integer Parameter MSB_RANK_SEL_I bound to: 15 - type: integer Parameter PHASER_CTL_BUS_WIDTH bound to: 16 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter PHASER_INDEX bound to: 2 - type: integer Parameter L_OF_ARRAY_MODE bound to: ARRAY_MODE_4_X_4 - type: string Parameter L_IF_ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter L_OSERDES_DATA_RATE bound to: SDR - type: string Parameter L_OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter L_FREQ_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_MEM_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_PHASE_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter PO_DCD_CORRECTION bound to: ON - type: string Parameter PO_DCD_SETTING bound to: 3'b111 Parameter DQS_AUTO_RECAL bound to: 0 - type: integer Parameter DQS_FIND_PATTERN bound to: 000 - type: string INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized3' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] Parameter BITLANES bound to: 12'b111111111100 Parameter BITLANES_OUTONLY bound to: 12'b000000000000 Parameter PO_DATA_CTL bound to: FALSE - type: string Parameter OSERDES_DATA_RATE bound to: SDR - type: string Parameter OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter TCK bound to: 1250.000000 - type: double Parameter BUS_WIDTH bound to: 12 - type: integer Parameter SYNTHESIS bound to: TRUE - type: string Parameter ISERDES_DQ_DATA_RATE bound to: DDR - type: string Parameter ISERDES_DQ_DATA_WIDTH bound to: 4 - type: integer Parameter ISERDES_DQ_DYN_CLKDIV_INV_EN bound to: FALSE - type: string Parameter ISERDES_DQ_DYN_CLK_INV_EN bound to: FALSE - type: string Parameter ISERDES_DQ_INIT_Q1 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q2 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q3 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q4 bound to: 1'b0 Parameter ISERDES_DQ_INTERFACE_TYPE bound to: MEMORY_DDR3 - type: string Parameter ISERDES_NUM_CE bound to: 2 - type: integer Parameter ISERDES_DQ_IOBDELAY bound to: IFD - type: string Parameter ISERDES_DQ_OFB_USED bound to: FALSE - type: string Parameter ISERDES_DQ_SERDES_MODE bound to: MASTER - type: string Parameter ISERDES_DQ_SRVAL_Q1 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q2 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q3 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q4 bound to: 1'b0 Parameter IDELAY_FINEDELAY_USE bound to: TRUE - type: string Parameter OSERDES_DQ_DATA_RATE_OQ bound to: SDR - type: string Parameter OSERDES_DQ_DATA_RATE_TQ bound to: SDR - type: string Parameter OSERDES_DQ_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter OSERDES_DQ_INIT_OQ bound to: 1'b1 Parameter OSERDES_DQ_INIT_TQ bound to: 1'b1 Parameter OSERDES_DQ_INTERFACE_TYPE bound to: DEFAULT - type: string Parameter OSERDES_DQ_ODELAY_USED bound to: 0 - type: integer Parameter OSERDES_DQ_SERDES_MODE bound to: MASTER - type: string Parameter OSERDES_DQ_SRVAL_OQ bound to: 1'b1 Parameter OSERDES_DQ_SRVAL_TQ bound to: 1'b1 Parameter OSERDES_DQ_TRISTATE_WIDTH bound to: 1 - type: integer Parameter OSERDES_DQS_DATA_RATE_OQ bound to: DDR - type: string Parameter OSERDES_DQS_DATA_RATE_TQ bound to: DDR - type: string Parameter OSERDES_DQS_TRISTATE_WIDTH bound to: 4 - type: integer Parameter OSERDES_DQS_DATA_WIDTH bound to: 4 - type: integer Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter OSERDES_TBYTE_CTL bound to: TRUE - type: string INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized3' (50#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized5' (50#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized6' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] Parameter ABCD bound to: D - type: string Parameter PO_DATA_CTL bound to: FALSE - type: string Parameter BITLANES bound to: 12'b001111111110 Parameter BITLANES_OUTONLY bound to: 12'b000000000000 Parameter BYTELANES_DDR_CK bound to: 72'b000000000000000000000000000000000000000000000000000000000000000000001000 Parameter RCLK_SELECT_LANE bound to: B - type: string Parameter PC_CLK_RATIO bound to: 4 - type: integer Parameter USE_PRE_POST_FIFO bound to: TRUE - type: string Parameter OF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter OF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter OF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter OF_OUTPUT_DISABLE bound to: FALSE - type: string Parameter OF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter IF_ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter IF_ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter IF_ARRAY_MODE bound to: UNDECLARED - type: string Parameter IF_SYNCHRONOUS_MODE bound to: FALSE - type: string Parameter PI_BURST_MODE bound to: TRUE - type: string Parameter PI_CLKOUT_DIV bound to: 2 - type: integer Parameter PI_FREQ_REF_DIV bound to: NONE - type: string Parameter PI_FINE_DELAY bound to: 56 - type: integer Parameter PI_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PI_SEL_CLK_OFFSET bound to: 6 - type: integer Parameter PI_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter PO_CLKOUT_DIV bound to: 4 - type: integer Parameter PO_FINE_DELAY bound to: 60 - type: integer Parameter PO_COARSE_BYPASS bound to: FALSE - type: string Parameter PO_COARSE_DELAY bound to: 0 - type: integer Parameter PO_OCLK_DELAY bound to: 29 - type: integer Parameter PO_OCLKDELAY_INV bound to: TRUE - type: string Parameter PO_OUTPUT_CLK_SRC bound to: DELAYED_REF - type: string Parameter PO_SYNC_IN_DIV_RST bound to: TRUE - type: string Parameter OSERDES_DATA_RATE bound to: UNDECLARED - type: string Parameter OSERDES_DATA_WIDTH bound to: UNDECLARED - type: string Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter TCK bound to: 1250.000000 - type: double Parameter SYNTHESIS bound to: TRUE - type: string Parameter BUS_WIDTH bound to: 12 - type: integer Parameter MSB_BURST_PEND_PO bound to: 3 - type: integer Parameter MSB_BURST_PEND_PI bound to: 7 - type: integer Parameter MSB_RANK_SEL_I bound to: 15 - type: integer Parameter PHASER_CTL_BUS_WIDTH bound to: 16 - type: integer Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter PHASER_INDEX bound to: 3 - type: integer Parameter L_OF_ARRAY_MODE bound to: ARRAY_MODE_4_X_4 - type: string Parameter L_IF_ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter L_OSERDES_DATA_RATE bound to: SDR - type: string Parameter L_OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter L_FREQ_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_MEM_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter L_PHASE_REF_PERIOD_NS bound to: 1.250000 - type: double Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter PO_DCD_CORRECTION bound to: ON - type: string Parameter PO_DCD_SETTING bound to: 3'b111 Parameter DQS_AUTO_RECAL bound to: 0 - type: integer Parameter DQS_FIND_PATTERN bound to: 000 - type: string INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:46328] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (51#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:46328] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized4' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] Parameter BITLANES bound to: 12'b001111111110 Parameter BITLANES_OUTONLY bound to: 12'b000000000000 Parameter PO_DATA_CTL bound to: FALSE - type: string Parameter OSERDES_DATA_RATE bound to: SDR - type: string Parameter OSERDES_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter IDELAYE2_IDELAY_TYPE bound to: VARIABLE - type: string Parameter IDELAYE2_IDELAY_VALUE bound to: 0 - type: integer Parameter IODELAY_GRP bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer Parameter TCK bound to: 1250.000000 - type: double Parameter BUS_WIDTH bound to: 12 - type: integer Parameter SYNTHESIS bound to: TRUE - type: string Parameter ISERDES_DQ_DATA_RATE bound to: DDR - type: string Parameter ISERDES_DQ_DATA_WIDTH bound to: 4 - type: integer Parameter ISERDES_DQ_DYN_CLKDIV_INV_EN bound to: FALSE - type: string Parameter ISERDES_DQ_DYN_CLK_INV_EN bound to: FALSE - type: string Parameter ISERDES_DQ_INIT_Q1 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q2 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q3 bound to: 1'b0 Parameter ISERDES_DQ_INIT_Q4 bound to: 1'b0 Parameter ISERDES_DQ_INTERFACE_TYPE bound to: MEMORY_DDR3 - type: string Parameter ISERDES_NUM_CE bound to: 2 - type: integer Parameter ISERDES_DQ_IOBDELAY bound to: IFD - type: string Parameter ISERDES_DQ_OFB_USED bound to: FALSE - type: string Parameter ISERDES_DQ_SERDES_MODE bound to: MASTER - type: string Parameter ISERDES_DQ_SRVAL_Q1 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q2 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q3 bound to: 1'b0 Parameter ISERDES_DQ_SRVAL_Q4 bound to: 1'b0 Parameter IDELAY_FINEDELAY_USE bound to: TRUE - type: string Parameter OSERDES_DQ_DATA_RATE_OQ bound to: SDR - type: string Parameter OSERDES_DQ_DATA_RATE_TQ bound to: SDR - type: string Parameter OSERDES_DQ_DATA_WIDTH bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000100 Parameter OSERDES_DQ_INIT_OQ bound to: 1'b1 Parameter OSERDES_DQ_INIT_TQ bound to: 1'b1 Parameter OSERDES_DQ_INTERFACE_TYPE bound to: DEFAULT - type: string Parameter OSERDES_DQ_ODELAY_USED bound to: 0 - type: integer Parameter OSERDES_DQ_SERDES_MODE bound to: MASTER - type: string Parameter OSERDES_DQ_SRVAL_OQ bound to: 1'b1 Parameter OSERDES_DQ_SRVAL_TQ bound to: 1'b1 Parameter OSERDES_DQ_TRISTATE_WIDTH bound to: 1 - type: integer Parameter OSERDES_DQS_DATA_RATE_OQ bound to: DDR - type: string Parameter OSERDES_DQS_DATA_RATE_TQ bound to: DDR - type: string Parameter OSERDES_DQS_TRISTATE_WIDTH bound to: 4 - type: integer Parameter OSERDES_DQS_DATA_WIDTH bound to: 4 - type: integer Parameter ODDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter OSERDES_TBYTE_CTL bound to: TRUE - type: string INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized4' (51#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized6' (51#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL__parameterized0' [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61433] Parameter AO_TOGGLE bound to: 1 - type: integer Parameter AO_WRLVL_EN bound to: 0 - type: integer Parameter BURST_MODE bound to: TRUE - type: string Parameter CLK_RATIO bound to: 4 - type: integer Parameter CMD_OFFSET bound to: 9 - type: integer Parameter CO_DURATION bound to: 1 - type: integer Parameter DATA_CTL_A_N bound to: FALSE - type: string Parameter DATA_CTL_B_N bound to: FALSE - type: string Parameter DATA_CTL_C_N bound to: FALSE - type: string Parameter DATA_CTL_D_N bound to: FALSE - type: string Parameter DISABLE_SEQ_MATCH bound to: TRUE - type: string Parameter DI_DURATION bound to: 1 - type: integer Parameter DO_DURATION bound to: 1 - type: integer Parameter EVENTS_DELAY bound to: 18 - type: integer Parameter FOUR_WINDOW_CLOCKS bound to: 63 - type: integer Parameter MULTI_REGION bound to: TRUE - type: string Parameter PHY_COUNT_ENABLE bound to: FALSE - type: string Parameter RD_CMD_OFFSET_0 bound to: 10 - type: integer Parameter RD_CMD_OFFSET_1 bound to: 10 - type: integer Parameter RD_CMD_OFFSET_2 bound to: 10 - type: integer Parameter RD_CMD_OFFSET_3 bound to: 10 - type: integer Parameter RD_DURATION_0 bound to: 6 - type: integer Parameter RD_DURATION_1 bound to: 6 - type: integer Parameter RD_DURATION_2 bound to: 6 - type: integer Parameter RD_DURATION_3 bound to: 6 - type: integer Parameter SYNC_MODE bound to: FALSE - type: string Parameter WR_CMD_OFFSET_0 bound to: 8 - type: integer Parameter WR_CMD_OFFSET_1 bound to: 8 - type: integer Parameter WR_CMD_OFFSET_2 bound to: 8 - type: integer Parameter WR_CMD_OFFSET_3 bound to: 8 - type: integer Parameter WR_DURATION_0 bound to: 7 - type: integer Parameter WR_DURATION_1 bound to: 7 - type: integer Parameter WR_DURATION_2 bound to: 7 - type: integer Parameter WR_DURATION_3 bound to: 7 - type: integer INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL__parameterized0' (51#1) [/opt/Xilinx/Vivado/2020.1/scripts/rt/data/unisim_comp.v:61433] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes__parameterized0' (51#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy' (52#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (8) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1671] WARNING: [Synth 8-689] width (12) of port connection 'pi_phase_locked_lanes' does not match port width (8) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1679] WARNING: [Synth 8-7071] port 'of_data_a_full' of module 'mig_7series_v4_2_ddr_mc_phy' is unconnected for instance 'u_ddr_mc_phy' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] WARNING: [Synth 8-7023] instance 'u_ddr_mc_phy' of module 'mig_7series_v4_2_ddr_mc_phy' has 89 connections declared, but only 88 given [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' (53#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_calib_top' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] Parameter TCQ bound to: 100 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter tCK bound to: 1250 - type: integer Parameter DDR3_VDD_OP_VOLT bound to: 150 - type: string Parameter CLK_PERIOD bound to: 5000 - type: integer Parameter N_CTL_LANES bound to: 4 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter PRBS_WIDTH bound to: 8 - type: integer Parameter HIGHEST_LANE bound to: 8 - type: integer Parameter HIGHEST_BANK bound to: 2 - type: integer Parameter BANK_TYPE bound to: HP_IO - type: string Parameter DATA_CTL_B0 bound to: 4'b1111 Parameter DATA_CTL_B1 bound to: 4'b0000 Parameter DATA_CTL_B2 bound to: 4'b0000 Parameter DATA_CTL_B3 bound to: 4'b0000 Parameter DATA_CTL_B4 bound to: 4'b0000 Parameter BYTE_LANES_B0 bound to: 4'b1111 Parameter BYTE_LANES_B1 bound to: 4'b1111 Parameter BYTE_LANES_B2 bound to: 4'b0000 Parameter BYTE_LANES_B3 bound to: 4'b0000 Parameter BYTE_LANES_B4 bound to: 4'b0000 Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011 Parameter CTL_BYTE_LANE bound to: 8'b11100100 Parameter CTL_BANK bound to: 3'b001 Parameter SLOT_1_CONFIG bound to: 8'b00000000 Parameter BANK_WIDTH bound to: 3 - type: integer Parameter CA_MIRROR bound to: OFF - type: string Parameter COL_WIDTH bound to: 10 - type: integer Parameter nCS_PER_RANK bound to: 1 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DRAM_WIDTH bound to: 8 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter CS_WIDTH bound to: 1 - type: integer Parameter CKE_WIDTH bound to: 1 - type: integer Parameter DDR2_DQSN_ENABLE bound to: YES - type: string Parameter PER_BIT_DESKEW bound to: OFF - type: string Parameter NUM_DQSFOUND_CAL bound to: 1020 - type: integer Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 Parameter CALIB_COL_ADD bound to: 12'b000000000000 Parameter CALIB_BA_ADD bound to: 3'b000 Parameter AL bound to: 0 - type: string Parameter TEST_AL bound to: 0 - type: string Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter BURST_MODE bound to: 8 - type: string Parameter BURST_TYPE bound to: SEQ - type: string Parameter nCL bound to: 11 - type: integer Parameter nCWL bound to: 8 - type: integer Parameter tRFC bound to: 260000 - type: integer Parameter tREFI bound to: 7800000 - type: integer Parameter OUTPUT_DRV bound to: HIGH - type: string Parameter REG_CTRL bound to: OFF - type: string Parameter RTT_NOM bound to: 40 - type: string Parameter RTT_WR bound to: OFF - type: string Parameter USE_ODT_PORT bound to: 1 - type: integer Parameter WRLVL bound to: ON - type: string Parameter PRE_REV3ES bound to: OFF - type: string Parameter POC_USE_METASTABLE_SAMP bound to: FALSE - type: string Parameter SIM_INIT_OPTION bound to: NONE - type: string Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter IDELAY_ADJ bound to: ON - type: string Parameter FINE_PER_BIT bound to: ON - type: string Parameter CENTER_COMP_MODE bound to: ON - type: string Parameter PI_VAL_ADJ bound to: ON - type: string Parameter TAPSPERKCLK bound to: 56 - type: integer Parameter DEBUG_PORT bound to: OFF - type: string Parameter SKIP_CALIB bound to: FALSE - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter nSLOTS bound to: 1 - type: integer Parameter OCAL_EN bound to: ON - type: string Parameter DQS_FOUND_N_CTL_LANES bound to: 4 - type: integer Parameter DQSFOUND_CAL bound to: RIGHT - type: string Parameter FIXED_VICTIM bound to: FALSE - type: string Parameter VCCO_PAT_EN bound to: 1 - type: integer Parameter VCCAUX_PAT_EN bound to: 1 - type: integer Parameter ISI_PAT_EN bound to: 1 - type: integer Parameter BYPASS_COMPLEX_RDLVL bound to: FALSE - type: string Parameter BYPASS_COMPLEX_OCAL bound to: TRUE - type: string Parameter REFRESH_TIMER bound to: 12210 - type: integer Parameter REFRESH_TIMER_WIDTH bound to: 14 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] Parameter TCQ bound to: 100 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DRAM_WIDTH bound to: 8 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter CLK_PERIOD bound to: 5000 - type: integer Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter WL_IDLE bound to: 5'b00000 Parameter WL_INIT bound to: 5'b00001 Parameter WL_INIT_FINE_INC bound to: 5'b00010 Parameter WL_INIT_FINE_INC_WAIT1 bound to: 5'b00011 Parameter WL_INIT_FINE_INC_WAIT bound to: 5'b00100 Parameter WL_INIT_FINE_DEC bound to: 5'b00101 Parameter WL_INIT_FINE_DEC_WAIT bound to: 5'b00110 Parameter WL_FINE_INC bound to: 5'b00111 Parameter WL_WAIT bound to: 5'b01000 Parameter WL_EDGE_CHECK bound to: 5'b01001 Parameter WL_DQS_CHECK bound to: 5'b01010 Parameter WL_DQS_CNT bound to: 5'b01011 Parameter WL_2RANK_TAP_DEC bound to: 5'b01100 Parameter WL_2RANK_DQS_CNT bound to: 5'b01101 Parameter WL_FINE_DEC bound to: 5'b01110 Parameter WL_FINE_DEC_WAIT bound to: 5'b01111 Parameter WL_CORSE_INC bound to: 5'b10000 Parameter WL_CORSE_INC_WAIT bound to: 5'b10001 Parameter WL_CORSE_INC_WAIT1 bound to: 5'b10010 Parameter WL_CORSE_INC_WAIT2 bound to: 5'b10011 Parameter WL_CORSE_DEC bound to: 5'b10100 Parameter WL_CORSE_DEC_WAIT bound to: 5'b10101 Parameter WL_CORSE_DEC_WAIT1 bound to: 5'b10110 Parameter WL_FINE_INC_WAIT bound to: 5'b10111 Parameter WL_2RANK_FINAL_TAP bound to: 5'b11000 Parameter WL_INIT_FINE_DEC_WAIT1 bound to: 5'b11001 Parameter WL_FINE_DEC_WAIT1 bound to: 5'b11010 Parameter WL_CORSE_INC_WAIT_TMP bound to: 5'b11011 Parameter COARSE_TAPS bound to: 7 - type: integer Parameter FAST_CAL_FINE bound to: 45 - type: integer Parameter FAST_CAL_COARSE bound to: 1 - type: integer Parameter REDO_COARSE bound to: 2 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:797] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' (54#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] Parameter TCQ bound to: 100 - type: integer Parameter tCK bound to: 1250 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter N_CTL_LANES bound to: 4 - type: integer Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter TAP_CNT_LIMIT bound to: 63 - type: integer Parameter FREQ_REF_DIV bound to: 1 - type: integer Parameter PHASER_TAP_RES bound to: 9 - type: integer Parameter CALC_TAP_CNT bound to: 350 - type: integer Parameter TAP_CNT bound to: 0 - type: integer Parameter TAP_DEC bound to: 29 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' (55#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_oclkdelay_cal' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v:69] Parameter TCQ bound to: 100 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter DRAM_WIDTH bound to: 8 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter MMCM_SAMP_WAIT bound to: 256 - type: integer Parameter OCAL_SIMPLE_SCAN_SAMPS bound to: 512 - type: integer Parameter PCT_SAMPS_SOLID bound to: 80 - type: integer Parameter POC_USE_METASTABLE_SAMP bound to: FALSE - type: string Parameter SCAN_PCT_SAMPS_SOLID bound to: 95 - type: integer Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter SAMPCNTRWIDTH bound to: 17 - type: integer Parameter SAMPLES bound to: 512 - type: integer Parameter TAPCNTRWIDTH bound to: 6 - type: integer Parameter TAPSPERKCLK bound to: 56 - type: integer Parameter BYPASS_COMPLEX_OCAL bound to: TRUE - type: string INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_lim' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v:69] Parameter TAPCNTRWIDTH bound to: 6 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter TCQ bound to: 100 - type: integer Parameter TAPSPERKCLK bound to: 56 - type: integer Parameter TDQSS_DEGREES bound to: 60 - type: integer Parameter BYPASS_COMPLEX_OCAL bound to: TRUE - type: string Parameter DIV_FACTOR bound to: 6 - type: integer Parameter TDQSS_LIM_MMCM_TAPS bound to: 9 - type: integer Parameter WAIT_CNT bound to: 15 - type: integer Parameter IDLE bound to: 14'b00000000000001 Parameter INIT bound to: 14'b00000000000010 Parameter WAIT_WR_REQ bound to: 14'b00000000000100 Parameter WAIT_POC_DONE bound to: 14'b00000000001000 Parameter WAIT_STG3 bound to: 14'b00000000010000 Parameter STAGE3_INC bound to: 14'b00000000100000 Parameter STAGE3_DEC bound to: 14'b00000001000000 Parameter STAGE2_INC bound to: 14'b00000010000000 Parameter STAGE2_DEC bound to: 14'b00000100000000 Parameter STG3_INCDEC_WAIT bound to: 14'b00001000000000 Parameter STG2_INCDEC_WAIT bound to: 14'b00010000000000 Parameter STAGE2_TAP_CHK bound to: 14'b00100000000000 Parameter PRECH_REQUEST bound to: 14'b01000000000000 Parameter LIMIT_DONE bound to: 14'b10000000000000 INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_lim' (56#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v:69] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_top' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v:68] Parameter LANE_CNT_WIDTH bound to: 2 - type: integer Parameter MMCM_SAMP_WAIT bound to: 256 - type: integer Parameter PCT_SAMPS_SOLID bound to: 80 - type: integer Parameter POC_USE_METASTABLE_SAMP bound to: FALSE - type: string Parameter TCQ bound to: 100 - type: integer Parameter CCENABLE bound to: 0 - type: integer Parameter SCANFROMRIGHT bound to: 1 - type: integer Parameter SAMPCNTRWIDTH bound to: 17 - type: integer Parameter SAMPLES bound to: 512 - type: integer Parameter TAPCNTRWIDTH bound to: 6 - type: integer Parameter TAPSPERKCLK bound to: 56 - type: integer Parameter SMWIDTH bound to: 2 - type: integer INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_tap_base' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v:99] Parameter MMCM_SAMP_WAIT bound to: 256 - type: integer Parameter POC_USE_METASTABLE_SAMP bound to: FALSE - type: string Parameter TCQ bound to: 100 - type: integer Parameter SAMPCNTRWIDTH bound to: 17 - type: integer Parameter SMWIDTH bound to: 2 - type: integer Parameter TAPCNTRWIDTH bound to: 6 - type: integer Parameter TAPSPERKCLK bound to: 56 - type: integer Parameter ONE bound to: 1 - type: integer Parameter SAMP_WAIT_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_tap_base' (57#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v:99] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_meta' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v:106] Parameter SCANFROMRIGHT bound to: 1 - type: integer Parameter TCQ bound to: 100 - type: integer Parameter TAPCNTRWIDTH bound to: 6 - type: integer Parameter TAPSPERKCLK bound to: 56 - type: integer Parameter NINETY bound to: 14 - type: integer Parameter TAPSPERKCLKX2 bound to: 112 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v:193] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_meta' (58#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v:106] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_edge_store' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v:68] Parameter TCQ bound to: 100 - type: integer Parameter TAPCNTRWIDTH bound to: 6 - type: integer Parameter TAPSPERKCLK bound to: 56 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_edge_store' (59#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v:68] INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_cc' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v:75] INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter TCQ bound to: 100 - type: integer Parameter CCENABLE bound to: 0 - type: integer Parameter LANE_CNT_WIDTH bound to: 2 - type: integer Parameter PCT_SAMPS_SOLID bound to: 80 - type: integer Parameter SAMPCNTRWIDTH bound to: 17 - type: integer Parameter SAMPLES bound to: 512 - type: integer Parameter SMWIDTH bound to: 2 - type: integer Parameter TAPCNTRWIDTH bound to: 6 - type: integer Parameter SAMPS_SOLID_THRESH bound to: 410 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_cc' (60#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v:75] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_top' (61#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v:68] Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter TCQ bound to: 100 - type: integer Parameter PO_WAIT bound to: 15 - type: integer Parameter POW_WIDTH bound to: 4 - type: integer Parameter ONE bound to: 1 - type: integer Parameter TWO bound to: 2 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_mux' (62#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v:72] Parameter TCQ bound to: 100 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter OCAL_DQ_MASK bound to: 8'b00000000 INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_data' (63#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v:120] Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter OCAL_SIMPLE_SCAN_SAMPS bound to: 512 - type: integer Parameter SCAN_PCT_SAMPS_SOLID bound to: 95 - type: integer Parameter TCQ bound to: 100 - type: integer Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter ONE bound to: 1 - type: integer Parameter CMPLX_DATA_CNT bound to: 157 - type: integer Parameter SIMP_DATA_CNT bound to: 1 - type: integer Parameter DATA_CNT_WIDTH bound to: 8 - type: integer Parameter CMPLX_SAMPS bound to: 50 - type: integer Parameter SAMP_CNT_WIDTH bound to: 10 - type: integer Parameter SIMP_SAMPS_SOLID_THRESH bound to: 486 - type: integer Parameter SIMP_SAMPS_HALF_THRESH bound to: 243 - type: integer Parameter CMPLX_SAMPS_SOLID_THRESH bound to: 48 - type: integer Parameter CMPLX_SAMPS_HALF_THRESH bound to: 24 - type: integer Parameter NULL bound to: 2'b11 Parameter FUZZ bound to: 2'b00 Parameter ONEEIGHTY bound to: 2'b10 Parameter ZERO bound to: 2'b01 INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_samp' (64#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v:109] Parameter TCQ bound to: 100 - type: integer Parameter NULL bound to: 2'b11 Parameter FUZZ bound to: 2'b00 Parameter ONEEIGHTY bound to: 2'b10 Parameter ZERO bound to: 2'b01 INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v:184] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_edge' (65#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v:91] Parameter TCQ bound to: 100 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter ONE bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_cntlr' (66#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v:82] Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter SAMPLES bound to: 512 - type: integer Parameter TCQ bound to: 100 - type: integer Parameter POC_SAMPLE_CLEAR_WAIT bound to: 1024 - type: integer Parameter MAX_RESUME_WAIT bound to: 1024 - type: integer Parameter RESUME_WAIT_WIDTH bound to: 11 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v:420] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_po_cntlr' (67#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v:105] INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_oclkdelay_cal' (68#1) [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v:69] INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter TCQ bound to: 100 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter nCL bound to: 11 - type: integer Parameter AL bound to: 0 - type: string Parameter nCWL bound to: 8 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter RANKS bound to: 1 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DRAM_WIDTH bound to: 8 - type: integer Parameter REG_CTRL bound to: OFF - type: string Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter NUM_DQSFOUND_CAL bound to: 1020 - type: integer Parameter N_CTL_LANES bound to: 4 - type: integer Parameter HIGHEST_LANE bound to: 8 - type: integer Parameter HIGHEST_BANK bound to: 2 - type: integer Parameter BYTE_LANES_B0 bound to: 4'b1111 Parameter BYTE_LANES_B1 bound to: 4'b1111 Parameter BYTE_LANES_B2 bound to: 4'b0000 Parameter BYTE_LANES_B3 bound to: 4'b0000 Parameter BYTE_LANES_B4 bound to: 4'b0000 Parameter DATA_CTL_B0 bound to: 4'b1111 Parameter DATA_CTL_B1 bound to: 4'b0000 Parameter DATA_CTL_B2 bound to: 4'b0000 Parameter DATA_CTL_B3 bound to: 4'b0000 Parameter DATA_CTL_B4 bound to: 4'b0000 Parameter nAL bound to: 0 - type: integer Parameter CWL_M bound to: 8 - type: integer Parameter LATENCY_FACTOR bound to: 13 - type: integer Parameter NUM_READS bound to: 7 - type: integer Parameter DATA_PRESENT bound to: 20'b00000000000000001111 Parameter FINE_ADJ_IDLE bound to: 4'b0000 Parameter RST_POSTWAIT bound to: 4'b0001 Parameter RST_POSTWAIT1 bound to: 4'b0010 Parameter RST_WAIT bound to: 4'b0011 Parameter FINE_ADJ_INIT bound to: 4'b0100 Parameter FINE_INC bound to: 4'b0101 Parameter FINE_INC_WAIT bound to: 4'b0110 Parameter FINE_INC_PREWAIT bound to: 4'b0111 Parameter DETECT_PREWAIT bound to: 4'b1000 Parameter DETECT_DQSFOUND bound to: 4'b1001 Parameter PRECH_WAIT bound to: 4'b1010 Parameter FINE_DEC bound to: 4'b1011 Parameter FINE_DEC_WAIT bound to: 4'b1100 Parameter FINE_DEC_PREWAIT bound to: 4'b1101 Parameter FINAL_WAIT bound to: 4'b1110 Parameter FINE_ADJ_DONE bound to: 4'b1111 Parameter TCQ bound to: 100 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter CLK_PERIOD bound to: 5000 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DRAM_WIDTH bound to: 8 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter PER_BIT_DESKEW bound to: OFF - type: string Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter DEBUG_PORT bound to: OFF - type: string Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter OCAL_EN bound to: ON - type: string Parameter IDELAY_ADJ bound to: ON - type: string Parameter PI_DIV2_INCDEC bound to: FALSE - type: string Parameter MIN_EYE_SIZE bound to: 16 - type: integer Parameter CAL_PAT_LEN bound to: 8 - type: integer Parameter RD_SHIFT_LEN bound to: 1 - type: integer Parameter RD_SHIFT_COMP_DELAY bound to: 5 - type: integer Parameter SR_VALID_DELAY bound to: 8 - type: integer Parameter PIPE_WAIT_CNT bound to: 16 - type: integer Parameter DETECT_EDGE_SAMPLE_CNT0 bound to: 12'b000000000001 Parameter DETECT_EDGE_SAMPLE_CNT1 bound to: 12'b000000000001 Parameter CAL1_IDLE bound to: 6'b000000 Parameter CAL1_NEW_DQS_WAIT bound to: 6'b000001 Parameter CAL1_STORE_FIRST_WAIT bound to: 6'b000010 Parameter CAL1_PAT_DETECT bound to: 6'b000011 Parameter CAL1_DQ_IDEL_TAP_INC bound to: 6'b000100 Parameter CAL1_DQ_IDEL_TAP_INC_WAIT bound to: 6'b000101 Parameter CAL1_DQ_IDEL_TAP_DEC bound to: 6'b000110 Parameter CAL1_DQ_IDEL_TAP_DEC_WAIT bound to: 6'b000111 Parameter CAL1_DETECT_EDGE bound to: 6'b001000 Parameter CAL1_IDEL_INC_CPT bound to: 6'b001001 Parameter CAL1_IDEL_INC_CPT_WAIT bound to: 6'b001010 Parameter CAL1_CALC_IDEL bound to: 6'b001011 Parameter CAL1_IDEL_DEC_CPT bound to: 6'b001100 Parameter CAL1_IDEL_DEC_CPT_WAIT bound to: 6'b001101 Parameter CAL1_NEXT_DQS bound to: 6'b001110 Parameter CAL1_DONE bound to: 6'b001111 Parameter CAL1_PB_STORE_FIRST_WAIT bound to: 6'b010000 Parameter CAL1_PB_DETECT_EDGE bound to: 6'b010001 Parameter CAL1_PB_INC_CPT bound to: 6'b010010 Parameter CAL1_PB_INC_CPT_WAIT bound to: 6'b010011 Parameter CAL1_PB_DEC_CPT_LEFT bound to: 6'b010100 Parameter CAL1_PB_DEC_CPT_LEFT_WAIT bound to: 6'b010101 Parameter CAL1_PB_DETECT_EDGE_DQ bound to: 6'b010110 Parameter CAL1_PB_INC_DQ bound to: 6'b010111 Parameter CAL1_PB_INC_DQ_WAIT bound to: 6'b011000 Parameter CAL1_PB_DEC_CPT bound to: 6'b011001 Parameter CAL1_PB_DEC_CPT_WAIT bound to: 6'b011010 Parameter CAL1_REGL_LOAD bound to: 6'b011011 Parameter CAL1_RDLVL_ERR bound to: 6'b011100 Parameter CAL1_MPR_NEW_DQS_WAIT bound to: 6'b011101 Parameter CAL1_VALID_WAIT bound to: 6'b011110 Parameter CAL1_MPR_PAT_DETECT bound to: 6'b011111 Parameter CAL1_NEW_DQS_PREWAIT bound to: 6'b100000 Parameter CAL1_RD_STOP_FOR_PI_INC bound to: 6'b100001 Parameter CAL1_CENTER_WAIT bound to: 6'b100010 INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2746] Parameter TCQ bound to: 100 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DRAM_WIDTH bound to: 8 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter PRBS_WIDTH bound to: 8 - type: integer Parameter FIXED_VICTIM bound to: FALSE - type: string Parameter FINE_PER_BIT bound to: ON - type: string Parameter CENTER_COMP_MODE bound to: ON - type: string Parameter PI_VAL_ADJ bound to: ON - type: string Parameter PRBS_IDLE bound to: 6'b000000 Parameter PRBS_NEW_DQS_WAIT bound to: 6'b000001 Parameter PRBS_PAT_COMPARE bound to: 6'b000010 Parameter PRBS_DEC_DQS bound to: 6'b000011 Parameter PRBS_DEC_DQS_WAIT bound to: 6'b000100 Parameter PRBS_INC_DQS bound to: 6'b000101 Parameter PRBS_INC_DQS_WAIT bound to: 6'b000110 Parameter PRBS_CALC_TAPS bound to: 6'b000111 Parameter PRBS_NEXT_DQS bound to: 6'b001000 Parameter PRBS_NEW_DQS_PREWAIT bound to: 6'b001001 Parameter PRBS_DONE bound to: 6'b001010 Parameter PRBS_CALC_TAPS_PRE bound to: 6'b001011 Parameter PRBS_CALC_TAPS_WAIT bound to: 6'b001100 Parameter FINE_PI_DEC bound to: 6'b001101 Parameter FINE_PI_DEC_WAIT bound to: 6'b001110 Parameter FINE_PI_INC bound to: 6'b001111 Parameter FINE_PI_INC_WAIT bound to: 6'b010000 Parameter FINE_PAT_COMPARE_PER_BIT bound to: 6'b010001 Parameter FINE_CALC_TAPS bound to: 6'b010010 Parameter FINE_CALC_TAPS_WAIT bound to: 6'b010011 Parameter RD_DONE_WAIT_FOR_PI_INC_INC bound to: 6'b010100 Parameter RD_DONE_WAIT_FOR_PI_INC_DEC bound to: 6'b010101 Parameter NUM_SAMPLES_CNT bound to: 12'b000000001100 Parameter NUM_SAMPLES_CNT1 bound to: 12'b000000010100 Parameter NUM_SAMPLES_CNT2 bound to: 12'b000000001010 Parameter MIN_WIN bound to: 8 - type: integer Parameter MATCH_ALL_ONE bound to: 8'b11111111 Parameter MIN_PASS bound to: 8'b00000000 Parameter MIN_LEFT bound to: 8'b10000000 INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:1152] Parameter TCQ bound to: 100 - type: integer Parameter PRBS_WIDTH bound to: 64 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter VCCO_PAT_EN bound to: 1 - type: integer Parameter VCCAUX_PAT_EN bound to: 1 - type: integer Parameter ISI_PAT_EN bound to: 1 - type: integer Parameter FIXED_VICTIM bound to: FALSE - type: string Parameter PRBS_SEQ_LEN_CYCLES bound to: 128 - type: integer Parameter PRBS_SEQ_LEN_CYCLES_BITS bound to: 7 - type: integer Parameter BRAM_ADDR_WIDTH bound to: 8 - type: integer Parameter BRAM_DATA_WIDTH bound to: 18 - type: integer Parameter BRAM_DEPTH bound to: 256 - type: integer Parameter tCK bound to: 1250 - type: integer Parameter TCQ bound to: 100 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter CLK_PERIOD bound to: 5000 - type: integer Parameter USE_ODT_PORT bound to: 1 - type: integer Parameter DDR3_VDD_OP_VOLT bound to: 150 - type: string Parameter VREF bound to: EXTERNAL - type: string Parameter PRBS_WIDTH bound to: 8 - type: integer Parameter BANK_WIDTH bound to: 3 - type: integer Parameter CA_MIRROR bound to: OFF - type: string Parameter COL_WIDTH bound to: 10 - type: integer Parameter nCS_PER_RANK bound to: 1 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter CS_WIDTH bound to: 1 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter CKE_WIDTH bound to: 1 - type: integer Parameter DRAM_TYPE bound to: DDR3 - type: string Parameter REG_CTRL bound to: OFF - type: string Parameter ADDR_CMD_MODE bound to: 1T - type: string Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 Parameter CALIB_COL_ADD bound to: 12'b000000000000 Parameter CALIB_BA_ADD bound to: 3'b000 Parameter AL bound to: 0 - type: string Parameter BURST_MODE bound to: 8 - type: string Parameter BURST_TYPE bound to: SEQ - type: string Parameter nCL bound to: 11 - type: integer Parameter nCWL bound to: 8 - type: integer Parameter tRFC bound to: 260000 - type: integer Parameter REFRESH_TIMER bound to: 12210 - type: integer Parameter REFRESH_TIMER_WIDTH bound to: 14 - type: integer Parameter OUTPUT_DRV bound to: HIGH - type: string Parameter RTT_NOM bound to: 40 - type: string Parameter RTT_WR bound to: OFF - type: string Parameter WRLVL bound to: ON - type: string Parameter DDR2_DQSN_ENABLE bound to: YES - type: string Parameter nSLOTS bound to: 1 - type: integer Parameter SIM_INIT_OPTION bound to: NONE - type: string Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter CKE_ODT_AUX bound to: FALSE - type: string Parameter PRE_REV3ES bound to: OFF - type: string Parameter TEST_AL bound to: 0 - type: string Parameter FIXED_VICTIM bound to: FALSE - type: string Parameter BYPASS_COMPLEX_OCAL bound to: TRUE - type: string Parameter SKIP_CALIB bound to: FALSE - type: string Parameter NUM_STG1_WR_RD bound to: 4 - type: integer Parameter ADDR_INC bound to: 8 - type: integer Parameter RTT_NOM2 bound to: 40 - type: string Parameter RTT_NOM3 bound to: 40 - type: string Parameter RTT_NOM_int bound to: 40 - type: string Parameter BURST4_FLAG bound to: 1'b0 Parameter CLK_MEM_PERIOD bound to: 1250 - type: integer Parameter DDR3_RESET_DELAY_NS bound to: 200000 - type: integer Parameter DDR3_CKE_DELAY_NS bound to: 700000 - type: integer Parameter DDR2_CKE_DELAY_NS bound to: 200000 - type: integer Parameter PWRON_RESET_DELAY_CNT bound to: 40 - type: integer Parameter PWRON_CKE_DELAY_CNT bound to: 140 - type: integer Parameter DDR2_INIT_PRE_DELAY_PS bound to: 400000 - type: integer Parameter DDR2_INIT_PRE_CNT bound to: 79 - type: integer Parameter TXPR_DELAY_CNT bound to: 64 - type: integer Parameter TDLLK_TZQINIT_DELAY_CNT bound to: 255 - type: integer Parameter TWR_CYC bound to: 12 - type: integer Parameter CNTNEXT_CMD bound to: 7'b1111111 Parameter INIT_CNT_MR2 bound to: 2'b00 Parameter INIT_CNT_MR3 bound to: 2'b01 Parameter INIT_CNT_MR1 bound to: 2'b10 Parameter INIT_CNT_MR0 bound to: 2'b11 Parameter INIT_CNT_MR_DONE bound to: 2'b11 Parameter REG_RC0 bound to: 8'b00000000 Parameter REG_RC1 bound to: 8'b00000001 Parameter REG_RC2 bound to: 8'b00000010 Parameter REG_RC3 bound to: 8'b00000011 Parameter REG_RC4 bound to: 8'b00000100 Parameter REG_RC5 bound to: 8'b00000101 Parameter FREQUENCY_ENCODING bound to: 4'b0011 Parameter REG_RC10 bound to: 8'b10011010 Parameter VREF_ENCODING bound to: 1'b0 Parameter DDR3_VOLTAGE_ENCODING bound to: 4'b0000 Parameter REG_RC11 bound to: 8'b10000011 Parameter nAL bound to: 0 - type: integer Parameter CWL_M bound to: 8 - type: integer Parameter PHASELOCKED_TIMEOUT bound to: 16383 - type: integer Parameter TG_TIMER_TIMEOUT bound to: 14'b11111111111111 Parameter DQ_PER_DQS bound to: 8 - type: integer Parameter COMPLEX_ROW_CNT_BYTE bound to: 16 - type: integer Parameter COMPLEX_RD bound to: 8 - type: integer Parameter INIT_IDLE bound to: 7'b0000000 Parameter INIT_WAIT_CKE_EXIT bound to: 7'b0000001 Parameter INIT_LOAD_MR bound to: 7'b0000010 Parameter INIT_LOAD_MR_WAIT bound to: 7'b0000011 Parameter INIT_ZQCL bound to: 7'b0000100 Parameter INIT_WAIT_DLLK_ZQINIT bound to: 7'b0000101 Parameter INIT_WRLVL_START bound to: 7'b0000110 Parameter INIT_WRLVL_WAIT bound to: 7'b0000111 Parameter INIT_WRLVL_LOAD_MR bound to: 7'b0001000 Parameter INIT_WRLVL_LOAD_MR_WAIT bound to: 7'b0001001 Parameter INIT_WRLVL_LOAD_MR2 bound to: 7'b0001010 Parameter INIT_WRLVL_LOAD_MR2_WAIT bound to: 7'b0001011 Parameter INIT_RDLVL_ACT bound to: 7'b0001100 Parameter INIT_RDLVL_ACT_WAIT bound to: 7'b0001101 Parameter INIT_RDLVL_STG1_WRITE bound to: 7'b0001110 Parameter INIT_RDLVL_STG1_WRITE_READ bound to: 7'b0001111 Parameter INIT_RDLVL_STG1_READ bound to: 7'b0010000 Parameter INIT_RDLVL_STG2_READ bound to: 7'b0010001 Parameter INIT_RDLVL_STG2_READ_WAIT bound to: 7'b0010010 Parameter INIT_PRECHARGE_PREWAIT bound to: 7'b0010011 Parameter INIT_PRECHARGE bound to: 7'b0010100 Parameter INIT_PRECHARGE_WAIT bound to: 7'b0010101 Parameter INIT_DONE bound to: 7'b0010110 Parameter INIT_DDR2_PRECHARGE bound to: 7'b0010111 Parameter INIT_DDR2_PRECHARGE_WAIT bound to: 7'b0011000 Parameter INIT_REFRESH bound to: 7'b0011001 Parameter INIT_REFRESH_WAIT bound to: 7'b0011010 Parameter INIT_REG_WRITE bound to: 7'b0011011 Parameter INIT_REG_WRITE_WAIT bound to: 7'b0011100 Parameter INIT_DDR2_MULTI_RANK bound to: 7'b0011101 Parameter INIT_DDR2_MULTI_RANK_WAIT bound to: 7'b0011110 Parameter INIT_WRCAL_ACT bound to: 7'b0011111 Parameter INIT_WRCAL_ACT_WAIT bound to: 7'b0100000 Parameter INIT_WRCAL_WRITE bound to: 7'b0100001 Parameter INIT_WRCAL_WRITE_READ bound to: 7'b0100010 Parameter INIT_WRCAL_READ bound to: 7'b0100011 Parameter INIT_WRCAL_READ_WAIT bound to: 7'b0100100 Parameter INIT_WRCAL_MULT_READS bound to: 7'b0100101 Parameter INIT_PI_PHASELOCK_READS bound to: 7'b0100110 Parameter INIT_MPR_RDEN bound to: 7'b0100111 Parameter INIT_MPR_WAIT bound to: 7'b0101000 Parameter INIT_MPR_READ bound to: 7'b0101001 Parameter INIT_MPR_DISABLE_PREWAIT bound to: 7'b0101010 Parameter INIT_MPR_DISABLE bound to: 7'b0101011 Parameter INIT_MPR_DISABLE_WAIT bound to: 7'b0101100 Parameter INIT_OCLKDELAY_ACT bound to: 7'b0101101 Parameter INIT_OCLKDELAY_ACT_WAIT bound to: 7'b0101110 Parameter INIT_OCLKDELAY_WRITE bound to: 7'b0101111 Parameter INIT_OCLKDELAY_WRITE_WAIT bound to: 7'b0110000 Parameter INIT_OCLKDELAY_READ bound to: 7'b0110001 Parameter INIT_OCLKDELAY_READ_WAIT bound to: 7'b0110010 Parameter INIT_REFRESH_RNK2_WAIT bound to: 7'b0110011 Parameter INIT_RDLVL_COMPLEX_PRECHARGE bound to: 7'b0110100 Parameter INIT_RDLVL_COMPLEX_PRECHARGE_WAIT bound to: 7'b0110101 Parameter INIT_RDLVL_COMPLEX_ACT bound to: 7'b0110110 Parameter INIT_RDLVL_COMPLEX_ACT_WAIT bound to: 7'b0110111 Parameter INIT_RDLVL_COMPLEX_READ bound to: 7'b0111000 Parameter INIT_RDLVL_COMPLEX_READ_WAIT bound to: 7'b0111001 Parameter INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT bound to: 7'b0111010 Parameter INIT_OCAL_COMPLEX_ACT bound to: 7'b0111011 Parameter INIT_OCAL_COMPLEX_ACT_WAIT bound to: 7'b0111100 Parameter INIT_OCAL_COMPLEX_WRITE_WAIT bound to: 7'b0111101 Parameter INIT_OCAL_COMPLEX_RESUME_WAIT bound to: 7'b0111110 Parameter INIT_OCAL_CENTER_ACT bound to: 7'b0111111 Parameter INIT_OCAL_CENTER_WRITE bound to: 7'b1000000 Parameter INIT_OCAL_CENTER_WRITE_WAIT bound to: 7'b1000001 Parameter INIT_OCAL_CENTER_ACT_WAIT bound to: 7'b1000010 Parameter INIT_RDLVL_COMPLEX_PI_WAIT bound to: 7'b1000011 Parameter INIT_SKIP_CALIB_WAIT bound to: 7'b1000100 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:5273] WARNING: [Synth 8-7071] port 'complex_oclk_prech_req' of module 'mig_7series_v4_2_ddr_phy_init' is unconnected for instance 'u_ddr_phy_init' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] WARNING: [Synth 8-7023] instance 'u_ddr_phy_init' of module 'mig_7series_v4_2_ddr_phy_init' has 131 connections declared, but only 130 given [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] Parameter TCQ bound to: 100 - type: integer Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter CLK_PERIOD bound to: 5000 - type: integer Parameter DQ_WIDTH bound to: 32 - type: integer Parameter DQS_CNT_WIDTH bound to: 2 - type: integer Parameter DQS_WIDTH bound to: 4 - type: integer Parameter DRAM_WIDTH bound to: 8 - type: integer Parameter PRE_REV3ES bound to: OFF - type: string Parameter SIM_CAL_OPTION bound to: NONE - type: string Parameter RD_SHIFT_LEN bound to: 1 - type: integer Parameter NUM_READS bound to: 2 - type: integer Parameter RDEN_WAIT_CNT bound to: 12 - type: integer Parameter COARSE_CNT bound to: 3 - type: integer Parameter FINE_CNT bound to: 22 - type: integer Parameter CAL2_IDLE bound to: 4'b0000 Parameter CAL2_READ_WAIT bound to: 4'b0001 Parameter CAL2_NEXT_DQS bound to: 4'b0010 Parameter CAL2_WRLVL_WAIT bound to: 4'b0011 Parameter CAL2_IFIFO_RESET bound to: 4'b0100 Parameter CAL2_DQ_IDEL_DEC bound to: 4'b0101 Parameter CAL2_DONE bound to: 4'b0110 Parameter CAL2_SANITY_WAIT bound to: 4'b0111 Parameter CAL2_ERR bound to: 4'b1000 INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1130] Parameter SKIP_CALIB bound to: FALSE - type: string Parameter TCQ bound to: 100 - type: integer Parameter TEMP_INCDEC bound to: 1465 - type: integer Parameter TEMP_HYST bound to: 1 - type: integer Parameter TEMP_MIN_LIMIT bound to: 12'b100010101100 Parameter TEMP_MAX_LIMIT bound to: 12'b110010100100 Parameter HYST_OFFSET bound to: 8 - type: integer Parameter TEMP_INCDEC_OFFSET bound to: 119 - type: integer Parameter IDLE bound to: 11'b00000000001 Parameter INIT bound to: 11'b00000000010 Parameter FOUR_INC bound to: 11'b00000000100 Parameter THREE_INC bound to: 11'b00000001000 Parameter TWO_INC bound to: 11'b00000010000 Parameter ONE_INC bound to: 11'b00000100000 Parameter NEUTRAL bound to: 11'b00001000000 Parameter ONE_DEC bound to: 11'b00010000000 Parameter TWO_DEC bound to: 11'b00100000000 Parameter THREE_DEC bound to: 11'b01000000000 Parameter FOUR_DEC bound to: 11'b10000000000 WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (8) of module 'mig_7series_v4_2_ddr_calib_top' [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:1340] Parameter TCQ bound to: 100 - type: integer Parameter APP_DATA_WIDTH bound to: 256 - type: integer Parameter APP_MASK_WIDTH bound to: 32 - type: integer Parameter BANK_WIDTH bound to: 3 - type: integer Parameter COL_WIDTH bound to: 10 - type: integer Parameter CWL bound to: 8 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter ECC bound to: OFF - type: string Parameter ECC_TEST bound to: OFF - type: string Parameter ORDERING bound to: NORM - type: string Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter REG_CTRL bound to: ON - type: string Parameter RANK_WIDTH bound to: 1 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string Parameter ADDR_WIDTH bound to: 29 - type: integer Parameter CWL_M bound to: 9 - type: integer Parameter TCQ bound to: 100 - type: integer Parameter ADDR_WIDTH bound to: 29 - type: integer Parameter BANK_WIDTH bound to: 3 - type: integer Parameter COL_WIDTH bound to: 10 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter RANK_WIDTH bound to: 1 - type: integer Parameter ROW_WIDTH bound to: 15 - type: integer Parameter RANKS bound to: 1 - type: integer Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string Parameter TCQ bound to: 100 - type: integer Parameter APP_DATA_WIDTH bound to: 256 - type: integer Parameter APP_MASK_WIDTH bound to: 32 - type: integer Parameter ECC bound to: OFF - type: string Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter ECC_TEST bound to: OFF - type: string Parameter CWL bound to: 9 - type: integer Parameter PNTR_RAM_CNT bound to: 2 - type: integer Parameter WR_BUF_WIDTH bound to: 288 - type: integer Parameter FULL_RAM_CNT bound to: 48 - type: integer Parameter REMAINDER bound to: 0 - type: integer Parameter RAM_CNT bound to: 48 - type: integer Parameter RAM_WIDTH bound to: 288 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:342] INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:380] Parameter TCQ bound to: 100 - type: integer Parameter APP_DATA_WIDTH bound to: 256 - type: integer Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer Parameter ECC bound to: OFF - type: string Parameter nCK_PER_CLK bound to: 4 - type: integer Parameter ORDERING bound to: NORM - type: string Parameter RD_BUF_WIDTH bound to: 256 - type: integer Parameter FULL_RAM_CNT bound to: 42 - type: integer Parameter REMAINDER bound to: 4 - type: integer Parameter RAM_CNT bound to: 43 - type: integer Parameter RAM_WIDTH bound to: 258 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406] WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_MC_ADDR_WIDTH bound to: 29 - type: integer Parameter C_MC_DATA_WIDTH bound to: 256 - type: integer Parameter C_MC_BURST_MODE bound to: 8 - type: string Parameter C_MC_nCK_PER_CLK bound to: 4 - type: integer Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000 Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000 Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string Parameter C_ECC bound to: OFF - type: string Parameter P_AXSIZE bound to: 5 - type: integer Parameter P_D1_REG_CONFIG_AW bound to: 0 - type: integer Parameter P_D1_REG_CONFIG_W bound to: 0 - type: integer Parameter P_D1_REG_CONFIG_B bound to: 0 - type: integer Parameter P_D1_REG_CONFIG_AR bound to: 0 - type: integer Parameter P_D1_REG_CONFIG_R bound to: 0 - type: integer Parameter P_USE_UPSIZER bound to: 1 - type: integer Parameter P_D2_REG_CONFIG_AW bound to: 1 - type: integer Parameter P_D2_REG_CONFIG_W bound to: 0 - type: integer Parameter P_D2_REG_CONFIG_AR bound to: 1 - type: integer Parameter P_D2_REG_CONFIG_R bound to: 0 - type: integer Parameter P_D3_REG_CONFIG_AW bound to: 0 - type: integer Parameter P_D3_REG_CONFIG_W bound to: 0 - type: integer Parameter P_D3_REG_CONFIG_B bound to: 0 - type: integer Parameter P_D3_REG_CONFIG_AR bound to: 0 - type: integer Parameter P_D3_REG_CONFIG_R bound to: 0 - type: integer Parameter P_UPSIZER_PACKING_LEVEL bound to: 2 - type: integer Parameter P_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter P_SINGLE_THREAD bound to: 0 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXI_AW_REGISTER bound to: 1 - type: integer Parameter C_M_AXI_W_REGISTER bound to: 0 - type: integer Parameter C_M_AXI_AR_REGISTER bound to: 1 - type: integer Parameter C_S_AXI_R_REGISTER bound to: 0 - type: integer Parameter C_M_AXI_R_REGISTER bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_WRITE bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_READ bound to: 1 - type: integer Parameter C_PACKING_LEVEL bound to: 2 - type: integer Parameter C_SUPPORT_BURSTS bound to: 1 - type: integer Parameter C_SINGLE_THREAD bound to: 0 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 5 - type: integer Parameter C_RATIO bound to: 4 - type: integer Parameter C_RATIO_LOG bound to: 2 - type: integer Parameter P_BYPASS bound to: 0 - type: integer Parameter P_LIGHTWT bound to: 7 - type: integer Parameter P_FWD_REV bound to: 1 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXI_REGISTER bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_CHANNEL bound to: 0 - type: integer Parameter C_PACKING_LEVEL bound to: 2 - type: integer Parameter C_SUPPORT_BURSTS bound to: 1 - type: integer Parameter C_SINGLE_THREAD bound to: 0 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 5 - type: integer Parameter C_S_AXI_NATIVE_SIZE bound to: 3'b011 Parameter C_M_AXI_NATIVE_SIZE bound to: 3'b101 Parameter C_DOUBLE_LEN bound to: 24'b000000000000000011111111 Parameter C_FIX_BURST bound to: 2'b00 Parameter C_INCR_BURST bound to: 2'b01 Parameter C_WRAP_BURST bound to: 2'b10 Parameter C_NEVER_PACK bound to: 0 - type: integer Parameter C_DEFAULT_PACK bound to: 1 - type: integer Parameter C_ALWAYS_PACK bound to: 2 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_BURST_BYTES_LOG bound to: 7 - type: integer Parameter C_SI_UNUSED_LOG bound to: 27 - type: integer Parameter C_MI_UNUSED_LOG bound to: 25 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter IS_SRI_INVERTED bound to: 1'b0 Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_ENABLE_S_VALID_CARRY bound to: 1 - type: integer Parameter C_ENABLE_REGISTERED_OUTPUT bound to: 1 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_FIFO_WIDTH bound to: 41 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter IS_SRI_INVERTED bound to: 1'b0 Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_R_INVERTED bound to: 1'b0 Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXI_REGISTER bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_PACKING_LEVEL bound to: 2 - type: integer Parameter C_SUPPORT_BURSTS bound to: 1 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 5 - type: integer Parameter C_RATIO bound to: 4 - type: integer Parameter C_RATIO_LOG bound to: 2 - type: integer Parameter C_NEVER_PACK bound to: 0 - type: integer Parameter C_DEFAULT_PACK bound to: 1 - type: integer Parameter C_ALWAYS_PACK bound to: 2 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_VALUE bound to: 5'b00000 Parameter C_DATA_WIDTH bound to: 5 - type: integer Parameter C_BITS_PER_LUT bound to: 2 - type: integer Parameter C_NUM_LUT bound to: 3 - type: integer Parameter C_FIX_DATA_WIDTH bound to: 6 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter INIT bound to: 64'b0101101001011010010110100110011011110000111100001111000011001100 Parameter INIT bound to: 64'b0011001100111100010101010101101011111111111100001111111111110000 Parameter INIT bound to: 16'b1100110011001010 Parameter INIT bound to: 64'b1010101010101100101010101010110010101010101011001010101010101100 Parameter INIT bound to: 1'b1 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter IS_S_INVERTED bound to: 1'b0 Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_VALUE bound to: 8'b00000000 Parameter C_DATA_WIDTH bound to: 8 - type: integer Parameter C_BITS_PER_LUT bound to: 2 - type: integer Parameter C_NUM_LUT bound to: 4 - type: integer Parameter C_FIX_DATA_WIDTH bound to: 8 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 5 - type: integer Parameter C_BITS_PER_LUT bound to: 1 - type: integer Parameter C_NUM_LUT bound to: 5 - type: integer Parameter C_FIX_DATA_WIDTH bound to: 5 - type: integer Parameter INIT bound to: 64'b1111000011110000111100001111000011001100110011000000000010101010 Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 256 - type: integer Parameter C_M_AXI_REGISTER bound to: 1 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_CHANNEL bound to: 1 - type: integer Parameter C_PACKING_LEVEL bound to: 2 - type: integer Parameter C_SUPPORT_BURSTS bound to: 1 - type: integer Parameter C_SINGLE_THREAD bound to: 0 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 5 - type: integer Parameter C_S_AXI_NATIVE_SIZE bound to: 3'b011 Parameter C_M_AXI_NATIVE_SIZE bound to: 3'b101 Parameter C_DOUBLE_LEN bound to: 24'b000000000000000011111111 Parameter C_FIX_BURST bound to: 2'b00 Parameter C_INCR_BURST bound to: 2'b01 Parameter C_WRAP_BURST bound to: 2'b10 Parameter C_NEVER_PACK bound to: 0 - type: integer Parameter C_DEFAULT_PACK bound to: 1 - type: integer Parameter C_ALWAYS_PACK bound to: 2 - type: integer Parameter C_FIFO_DEPTH_LOG bound to: 5 - type: integer Parameter C_BURST_BYTES_LOG bound to: 7 - type: integer Parameter C_SI_UNUSED_LOG bound to: 27 - type: integer Parameter C_MI_UNUSED_LOG bound to: 25 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_M_AXI_DATA_WIDTH bound to: 256 - type: integer Parameter C_S_AXI_REGISTER bound to: 0 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_PACKING_LEVEL bound to: 2 - type: integer Parameter C_SUPPORT_BURSTS bound to: 1 - type: integer Parameter C_S_AXI_BYTES_LOG bound to: 3 - type: integer Parameter C_M_AXI_BYTES_LOG bound to: 5 - type: integer Parameter C_RATIO bound to: 4 - type: integer Parameter C_RATIO_LOG bound to: 2 - type: integer Parameter C_NEVER_PACK bound to: 0 - type: integer Parameter C_DEFAULT_PACK bound to: 1 - type: integer Parameter C_ALWAYS_PACK bound to: 2 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_REG_CONFIG_AW bound to: 7 - type: integer Parameter C_REG_CONFIG_W bound to: 0 - type: integer Parameter C_REG_CONFIG_B bound to: 0 - type: integer Parameter C_REG_CONFIG_AR bound to: 7 - type: integer Parameter C_REG_CONFIG_R bound to: 0 - type: integer Parameter C_AWUSER_RIGHT bound to: 0 - type: integer Parameter C_AWUSER_LEN bound to: 0 - type: integer Parameter C_AWQOS_RIGHT bound to: 0 - type: integer Parameter C_AWQOS_LEN bound to: 4 - type: integer Parameter C_AWREGION_RIGHT bound to: 4 - type: integer Parameter C_AWREGION_LEN bound to: 4 - type: integer Parameter C_AWPROT_RIGHT bound to: 8 - type: integer Parameter C_AWPROT_LEN bound to: 3 - type: integer Parameter C_AWCACHE_RIGHT bound to: 11 - type: integer Parameter C_AWCACHE_LEN bound to: 4 - type: integer Parameter C_AWLOCK_RIGHT bound to: 15 - type: integer Parameter C_AWLOCK_LEN bound to: 2 - type: integer Parameter C_AWBURST_RIGHT bound to: 17 - type: integer Parameter C_AWBURST_LEN bound to: 2 - type: integer Parameter C_AWSIZE_RIGHT bound to: 19 - type: integer Parameter C_AWSIZE_LEN bound to: 3 - type: integer Parameter C_AWLEN_RIGHT bound to: 22 - type: integer Parameter C_AWLEN_LEN bound to: 8 - type: integer Parameter C_AWADDR_RIGHT bound to: 30 - type: integer Parameter C_AWADDR_LEN bound to: 30 - type: integer Parameter C_AWID_RIGHT bound to: 60 - type: integer Parameter C_AWID_LEN bound to: 5 - type: integer Parameter C_AW_SIZE bound to: 65 - type: integer Parameter C_WUSER_RIGHT bound to: 0 - type: integer Parameter C_WUSER_LEN bound to: 0 - type: integer Parameter C_WLAST_RIGHT bound to: 0 - type: integer Parameter C_WLAST_LEN bound to: 1 - type: integer Parameter C_WSTRB_RIGHT bound to: 1 - type: integer Parameter C_WSTRB_LEN bound to: 8 - type: integer Parameter C_WDATA_RIGHT bound to: 9 - type: integer Parameter C_WDATA_LEN bound to: 64 - type: integer Parameter C_WID_RIGHT bound to: 73 - type: integer Parameter C_WID_LEN bound to: 5 - type: integer Parameter C_W_SIZE bound to: 78 - type: integer Parameter C_BUSER_RIGHT bound to: 0 - type: integer Parameter C_BUSER_LEN bound to: 0 - type: integer Parameter C_BRESP_RIGHT bound to: 0 - type: integer Parameter C_BRESP_LEN bound to: 2 - type: integer Parameter C_BID_RIGHT bound to: 2 - type: integer Parameter C_BID_LEN bound to: 5 - type: integer Parameter C_B_SIZE bound to: 7 - type: integer Parameter C_ARUSER_RIGHT bound to: 0 - type: integer Parameter C_ARUSER_LEN bound to: 0 - type: integer Parameter C_ARQOS_RIGHT bound to: 0 - type: integer Parameter C_ARQOS_LEN bound to: 4 - type: integer Parameter C_ARREGION_RIGHT bound to: 4 - type: integer Parameter C_ARREGION_LEN bound to: 4 - type: integer Parameter C_ARPROT_RIGHT bound to: 8 - type: integer Parameter C_ARPROT_LEN bound to: 3 - type: integer Parameter C_ARCACHE_RIGHT bound to: 11 - type: integer Parameter C_ARCACHE_LEN bound to: 4 - type: integer Parameter C_ARLOCK_RIGHT bound to: 15 - type: integer Parameter C_ARLOCK_LEN bound to: 2 - type: integer Parameter C_ARBURST_RIGHT bound to: 17 - type: integer Parameter C_ARBURST_LEN bound to: 2 - type: integer Parameter C_ARSIZE_RIGHT bound to: 19 - type: integer Parameter C_ARSIZE_LEN bound to: 3 - type: integer Parameter C_ARLEN_RIGHT bound to: 22 - type: integer Parameter C_ARLEN_LEN bound to: 8 - type: integer Parameter C_ARADDR_RIGHT bound to: 30 - type: integer Parameter C_ARADDR_LEN bound to: 30 - type: integer Parameter C_ARID_RIGHT bound to: 60 - type: integer Parameter C_ARID_LEN bound to: 5 - type: integer Parameter C_AR_SIZE bound to: 65 - type: integer Parameter C_RUSER_RIGHT bound to: 0 - type: integer Parameter C_RUSER_LEN bound to: 0 - type: integer Parameter C_RLAST_RIGHT bound to: 0 - type: integer Parameter C_RLAST_LEN bound to: 1 - type: integer Parameter C_RRESP_RIGHT bound to: 1 - type: integer Parameter C_RRESP_LEN bound to: 2 - type: integer Parameter C_RDATA_RIGHT bound to: 3 - type: integer Parameter C_RDATA_LEN bound to: 64 - type: integer Parameter C_RID_RIGHT bound to: 67 - type: integer Parameter C_RID_LEN bound to: 5 - type: integer Parameter C_R_SIZE bound to: 72 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 65 - type: integer Parameter C_REG_CONFIG bound to: 7 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 78 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 7 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 72 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 256 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_REG_CONFIG_AW bound to: 0 - type: integer Parameter C_REG_CONFIG_W bound to: 0 - type: integer Parameter C_REG_CONFIG_B bound to: 0 - type: integer Parameter C_REG_CONFIG_AR bound to: 0 - type: integer Parameter C_REG_CONFIG_R bound to: 1 - type: integer Parameter C_AWUSER_RIGHT bound to: 0 - type: integer Parameter C_AWUSER_LEN bound to: 0 - type: integer Parameter C_AWQOS_RIGHT bound to: 0 - type: integer Parameter C_AWQOS_LEN bound to: 4 - type: integer Parameter C_AWREGION_RIGHT bound to: 4 - type: integer Parameter C_AWREGION_LEN bound to: 4 - type: integer Parameter C_AWPROT_RIGHT bound to: 8 - type: integer Parameter C_AWPROT_LEN bound to: 3 - type: integer Parameter C_AWCACHE_RIGHT bound to: 11 - type: integer Parameter C_AWCACHE_LEN bound to: 4 - type: integer Parameter C_AWLOCK_RIGHT bound to: 15 - type: integer Parameter C_AWLOCK_LEN bound to: 2 - type: integer Parameter C_AWBURST_RIGHT bound to: 17 - type: integer Parameter C_AWBURST_LEN bound to: 2 - type: integer Parameter C_AWSIZE_RIGHT bound to: 19 - type: integer Parameter C_AWSIZE_LEN bound to: 3 - type: integer Parameter C_AWLEN_RIGHT bound to: 22 - type: integer Parameter C_AWLEN_LEN bound to: 8 - type: integer Parameter C_AWADDR_RIGHT bound to: 30 - type: integer Parameter C_AWADDR_LEN bound to: 30 - type: integer Parameter C_AWID_RIGHT bound to: 60 - type: integer Parameter C_AWID_LEN bound to: 5 - type: integer Parameter C_AW_SIZE bound to: 65 - type: integer Parameter C_WUSER_RIGHT bound to: 0 - type: integer Parameter C_WUSER_LEN bound to: 0 - type: integer Parameter C_WLAST_RIGHT bound to: 0 - type: integer Parameter C_WLAST_LEN bound to: 1 - type: integer Parameter C_WSTRB_RIGHT bound to: 1 - type: integer Parameter C_WSTRB_LEN bound to: 32 - type: integer Parameter C_WDATA_RIGHT bound to: 33 - type: integer Parameter C_WDATA_LEN bound to: 256 - type: integer Parameter C_WID_RIGHT bound to: 289 - type: integer Parameter C_WID_LEN bound to: 5 - type: integer Parameter C_W_SIZE bound to: 294 - type: integer Parameter C_BUSER_RIGHT bound to: 0 - type: integer Parameter C_BUSER_LEN bound to: 0 - type: integer Parameter C_BRESP_RIGHT bound to: 0 - type: integer Parameter C_BRESP_LEN bound to: 2 - type: integer Parameter C_BID_RIGHT bound to: 2 - type: integer Parameter C_BID_LEN bound to: 5 - type: integer Parameter C_B_SIZE bound to: 7 - type: integer Parameter C_ARUSER_RIGHT bound to: 0 - type: integer Parameter C_ARUSER_LEN bound to: 0 - type: integer Parameter C_ARQOS_RIGHT bound to: 0 - type: integer Parameter C_ARQOS_LEN bound to: 4 - type: integer Parameter C_ARREGION_RIGHT bound to: 4 - type: integer Parameter C_ARREGION_LEN bound to: 4 - type: integer Parameter C_ARPROT_RIGHT bound to: 8 - type: integer Parameter C_ARPROT_LEN bound to: 3 - type: integer Parameter C_ARCACHE_RIGHT bound to: 11 - type: integer Parameter C_ARCACHE_LEN bound to: 4 - type: integer Parameter C_ARLOCK_RIGHT bound to: 15 - type: integer Parameter C_ARLOCK_LEN bound to: 2 - type: integer Parameter C_ARBURST_RIGHT bound to: 17 - type: integer Parameter C_ARBURST_LEN bound to: 2 - type: integer Parameter C_ARSIZE_RIGHT bound to: 19 - type: integer Parameter C_ARSIZE_LEN bound to: 3 - type: integer Parameter C_ARLEN_RIGHT bound to: 22 - type: integer Parameter C_ARLEN_LEN bound to: 8 - type: integer Parameter C_ARADDR_RIGHT bound to: 30 - type: integer Parameter C_ARADDR_LEN bound to: 30 - type: integer Parameter C_ARID_RIGHT bound to: 60 - type: integer Parameter C_ARID_LEN bound to: 5 - type: integer Parameter C_AR_SIZE bound to: 65 - type: integer Parameter C_RUSER_RIGHT bound to: 0 - type: integer Parameter C_RUSER_LEN bound to: 0 - type: integer Parameter C_RLAST_RIGHT bound to: 0 - type: integer Parameter C_RLAST_LEN bound to: 1 - type: integer Parameter C_RRESP_RIGHT bound to: 1 - type: integer Parameter C_RRESP_LEN bound to: 2 - type: integer Parameter C_RDATA_RIGHT bound to: 3 - type: integer Parameter C_RDATA_LEN bound to: 256 - type: integer Parameter C_RID_RIGHT bound to: 259 - type: integer Parameter C_RID_LEN bound to: 5 - type: integer Parameter C_R_SIZE bound to: 264 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 65 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 294 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 264 - type: integer Parameter C_REG_CONFIG bound to: 1 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:183] Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_REG_CONFIG_AW bound to: 0 - type: integer Parameter C_REG_CONFIG_W bound to: 0 - type: integer Parameter C_REG_CONFIG_B bound to: 0 - type: integer Parameter C_REG_CONFIG_AR bound to: 0 - type: integer Parameter C_REG_CONFIG_R bound to: 0 - type: integer Parameter C_AWUSER_RIGHT bound to: 0 - type: integer Parameter C_AWUSER_LEN bound to: 0 - type: integer Parameter C_AWQOS_RIGHT bound to: 0 - type: integer Parameter C_AWQOS_LEN bound to: 4 - type: integer Parameter C_AWREGION_RIGHT bound to: 4 - type: integer Parameter C_AWREGION_LEN bound to: 4 - type: integer Parameter C_AWPROT_RIGHT bound to: 8 - type: integer Parameter C_AWPROT_LEN bound to: 3 - type: integer Parameter C_AWCACHE_RIGHT bound to: 11 - type: integer Parameter C_AWCACHE_LEN bound to: 4 - type: integer Parameter C_AWLOCK_RIGHT bound to: 15 - type: integer Parameter C_AWLOCK_LEN bound to: 2 - type: integer Parameter C_AWBURST_RIGHT bound to: 17 - type: integer Parameter C_AWBURST_LEN bound to: 2 - type: integer Parameter C_AWSIZE_RIGHT bound to: 19 - type: integer Parameter C_AWSIZE_LEN bound to: 3 - type: integer Parameter C_AWLEN_RIGHT bound to: 22 - type: integer Parameter C_AWLEN_LEN bound to: 8 - type: integer Parameter C_AWADDR_RIGHT bound to: 30 - type: integer Parameter C_AWADDR_LEN bound to: 30 - type: integer Parameter C_AWID_RIGHT bound to: 60 - type: integer Parameter C_AWID_LEN bound to: 5 - type: integer Parameter C_AW_SIZE bound to: 65 - type: integer Parameter C_WUSER_RIGHT bound to: 0 - type: integer Parameter C_WUSER_LEN bound to: 0 - type: integer Parameter C_WLAST_RIGHT bound to: 0 - type: integer Parameter C_WLAST_LEN bound to: 1 - type: integer Parameter C_WSTRB_RIGHT bound to: 1 - type: integer Parameter C_WSTRB_LEN bound to: 8 - type: integer Parameter C_WDATA_RIGHT bound to: 9 - type: integer Parameter C_WDATA_LEN bound to: 64 - type: integer Parameter C_WID_RIGHT bound to: 73 - type: integer Parameter C_WID_LEN bound to: 5 - type: integer Parameter C_W_SIZE bound to: 78 - type: integer Parameter C_BUSER_RIGHT bound to: 0 - type: integer Parameter C_BUSER_LEN bound to: 0 - type: integer Parameter C_BRESP_RIGHT bound to: 0 - type: integer Parameter C_BRESP_LEN bound to: 2 - type: integer Parameter C_BID_RIGHT bound to: 2 - type: integer Parameter C_BID_LEN bound to: 5 - type: integer Parameter C_B_SIZE bound to: 7 - type: integer Parameter C_ARUSER_RIGHT bound to: 0 - type: integer Parameter C_ARUSER_LEN bound to: 0 - type: integer Parameter C_ARQOS_RIGHT bound to: 0 - type: integer Parameter C_ARQOS_LEN bound to: 4 - type: integer Parameter C_ARREGION_RIGHT bound to: 4 - type: integer Parameter C_ARREGION_LEN bound to: 4 - type: integer Parameter C_ARPROT_RIGHT bound to: 8 - type: integer Parameter C_ARPROT_LEN bound to: 3 - type: integer Parameter C_ARCACHE_RIGHT bound to: 11 - type: integer Parameter C_ARCACHE_LEN bound to: 4 - type: integer Parameter C_ARLOCK_RIGHT bound to: 15 - type: integer Parameter C_ARLOCK_LEN bound to: 2 - type: integer Parameter C_ARBURST_RIGHT bound to: 17 - type: integer Parameter C_ARBURST_LEN bound to: 2 - type: integer Parameter C_ARSIZE_RIGHT bound to: 19 - type: integer Parameter C_ARSIZE_LEN bound to: 3 - type: integer Parameter C_ARLEN_RIGHT bound to: 22 - type: integer Parameter C_ARLEN_LEN bound to: 8 - type: integer Parameter C_ARADDR_RIGHT bound to: 30 - type: integer Parameter C_ARADDR_LEN bound to: 30 - type: integer Parameter C_ARID_RIGHT bound to: 60 - type: integer Parameter C_ARID_LEN bound to: 5 - type: integer Parameter C_AR_SIZE bound to: 65 - type: integer Parameter C_RUSER_RIGHT bound to: 0 - type: integer Parameter C_RUSER_LEN bound to: 0 - type: integer Parameter C_RLAST_RIGHT bound to: 0 - type: integer Parameter C_RLAST_LEN bound to: 1 - type: integer Parameter C_RRESP_RIGHT bound to: 1 - type: integer Parameter C_RRESP_LEN bound to: 2 - type: integer Parameter C_RDATA_RIGHT bound to: 3 - type: integer Parameter C_RDATA_LEN bound to: 64 - type: integer Parameter C_RID_RIGHT bound to: 67 - type: integer Parameter C_RID_LEN bound to: 5 - type: integer Parameter C_R_SIZE bound to: 72 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 65 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 78 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 7 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 72 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_AXI_ID_WIDTH bound to: 5 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_AXI_DATA_WIDTH bound to: 256 - type: integer Parameter C_AXI_SUPPORTS_USER_SIGNALS bound to: 0 - type: integer Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer Parameter C_REG_CONFIG_AW bound to: 0 - type: integer Parameter C_REG_CONFIG_W bound to: 0 - type: integer Parameter C_REG_CONFIG_B bound to: 0 - type: integer Parameter C_REG_CONFIG_AR bound to: 0 - type: integer Parameter C_REG_CONFIG_R bound to: 0 - type: integer Parameter C_AWUSER_RIGHT bound to: 0 - type: integer Parameter C_AWUSER_LEN bound to: 0 - type: integer Parameter C_AWQOS_RIGHT bound to: 0 - type: integer Parameter C_AWQOS_LEN bound to: 4 - type: integer Parameter C_AWREGION_RIGHT bound to: 4 - type: integer Parameter C_AWREGION_LEN bound to: 4 - type: integer Parameter C_AWPROT_RIGHT bound to: 8 - type: integer Parameter C_AWPROT_LEN bound to: 3 - type: integer Parameter C_AWCACHE_RIGHT bound to: 11 - type: integer Parameter C_AWCACHE_LEN bound to: 4 - type: integer Parameter C_AWLOCK_RIGHT bound to: 15 - type: integer Parameter C_AWLOCK_LEN bound to: 2 - type: integer Parameter C_AWBURST_RIGHT bound to: 17 - type: integer Parameter C_AWBURST_LEN bound to: 2 - type: integer Parameter C_AWSIZE_RIGHT bound to: 19 - type: integer Parameter C_AWSIZE_LEN bound to: 3 - type: integer Parameter C_AWLEN_RIGHT bound to: 22 - type: integer Parameter C_AWLEN_LEN bound to: 8 - type: integer Parameter C_AWADDR_RIGHT bound to: 30 - type: integer Parameter C_AWADDR_LEN bound to: 30 - type: integer Parameter C_AWID_RIGHT bound to: 60 - type: integer Parameter C_AWID_LEN bound to: 5 - type: integer Parameter C_AW_SIZE bound to: 65 - type: integer Parameter C_WUSER_RIGHT bound to: 0 - type: integer Parameter C_WUSER_LEN bound to: 0 - type: integer Parameter C_WLAST_RIGHT bound to: 0 - type: integer Parameter C_WLAST_LEN bound to: 1 - type: integer Parameter C_WSTRB_RIGHT bound to: 1 - type: integer Parameter C_WSTRB_LEN bound to: 32 - type: integer Parameter C_WDATA_RIGHT bound to: 33 - type: integer Parameter C_WDATA_LEN bound to: 256 - type: integer Parameter C_WID_RIGHT bound to: 289 - type: integer Parameter C_WID_LEN bound to: 5 - type: integer Parameter C_W_SIZE bound to: 294 - type: integer Parameter C_BUSER_RIGHT bound to: 0 - type: integer Parameter C_BUSER_LEN bound to: 0 - type: integer Parameter C_BRESP_RIGHT bound to: 0 - type: integer Parameter C_BRESP_LEN bound to: 2 - type: integer Parameter C_BID_RIGHT bound to: 2 - type: integer Parameter C_BID_LEN bound to: 5 - type: integer Parameter C_B_SIZE bound to: 7 - type: integer Parameter C_ARUSER_RIGHT bound to: 0 - type: integer Parameter C_ARUSER_LEN bound to: 0 - type: integer Parameter C_ARQOS_RIGHT bound to: 0 - type: integer Parameter C_ARQOS_LEN bound to: 4 - type: integer Parameter C_ARREGION_RIGHT bound to: 4 - type: integer Parameter C_ARREGION_LEN bound to: 4 - type: integer Parameter C_ARPROT_RIGHT bound to: 8 - type: integer Parameter C_ARPROT_LEN bound to: 3 - type: integer Parameter C_ARCACHE_RIGHT bound to: 11 - type: integer Parameter C_ARCACHE_LEN bound to: 4 - type: integer Parameter C_ARLOCK_RIGHT bound to: 15 - type: integer Parameter C_ARLOCK_LEN bound to: 2 - type: integer Parameter C_ARBURST_RIGHT bound to: 17 - type: integer Parameter C_ARBURST_LEN bound to: 2 - type: integer Parameter C_ARSIZE_RIGHT bound to: 19 - type: integer Parameter C_ARSIZE_LEN bound to: 3 - type: integer Parameter C_ARLEN_RIGHT bound to: 22 - type: integer Parameter C_ARLEN_LEN bound to: 8 - type: integer Parameter C_ARADDR_RIGHT bound to: 30 - type: integer Parameter C_ARADDR_LEN bound to: 30 - type: integer Parameter C_ARID_RIGHT bound to: 60 - type: integer Parameter C_ARID_LEN bound to: 5 - type: integer Parameter C_AR_SIZE bound to: 65 - type: integer Parameter C_RUSER_RIGHT bound to: 0 - type: integer Parameter C_RUSER_LEN bound to: 0 - type: integer Parameter C_RLAST_RIGHT bound to: 0 - type: integer Parameter C_RLAST_LEN bound to: 1 - type: integer Parameter C_RRESP_RIGHT bound to: 1 - type: integer Parameter C_RRESP_LEN bound to: 2 - type: integer Parameter C_RDATA_RIGHT bound to: 3 - type: integer Parameter C_RDATA_LEN bound to: 256 - type: integer Parameter C_RID_RIGHT bound to: 259 - type: integer Parameter C_RID_LEN bound to: 5 - type: integer Parameter C_R_SIZE bound to: 264 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 294 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer Parameter C_FAMILY bound to: virtex7 - type: string Parameter C_DATA_WIDTH bound to: 264 - type: integer Parameter C_REG_CONFIG bound to: 0 - type: integer Parameter C_ID_WIDTH bound to: 5 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_MC_ADDR_WIDTH bound to: 29 - type: integer Parameter C_DATA_WIDTH bound to: 256 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_MC_nCK_PER_CLK bound to: 4 - type: integer Parameter C_AXSIZE bound to: 5 - type: integer Parameter C_ECC bound to: OFF - type: string Parameter P_CMD_WRITE bound to: 3'b000 Parameter P_CMD_READ bound to: 3'b001 Parameter P_CMD_WRITE_BYTES bound to: 3'b011 Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_MC_ADDR_WIDTH bound to: 29 - type: integer Parameter C_DATA_WIDTH bound to: 256 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_MC_nCK_PER_CLK bound to: 4 - type: integer Parameter C_AXSIZE bound to: 5 - type: integer Parameter C_MC_RD_INST bound to: 0 - type: integer Parameter P_MC_BURST_MASK bound to: 29'b11111111111111111111111111000 Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_MC_ADDR_WIDTH bound to: 29 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_DATA_WIDTH bound to: 256 - type: integer Parameter C_AXSIZE bound to: 5 - type: integer Parameter C_MC_RD_INST bound to: 0 - type: integer Parameter P_AXLEN_WIDTH bound to: 8 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_MC_ADDR_WIDTH bound to: 29 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_DATA_WIDTH bound to: 256 - type: integer Parameter C_AXSIZE bound to: 5 - type: integer Parameter C_MC_RD_INST bound to: 0 - type: integer Parameter P_AXLEN_WIDTH bound to: 4 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_MC_RD_INST bound to: 0 - type: integer Parameter C_DATA_WIDTH bound to: 256 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_ECC bound to: OFF - type: string Parameter SM_FIRST_DATA bound to: 1'b0 Parameter SM_SECOND_DATA bound to: 1'b1 Parameter C_ID_WIDTH bound to: 5 - type: integer Parameter P_WIDTH bound to: 5 - type: integer Parameter P_DEPTH bound to: 8 - type: integer Parameter P_AWIDTH bound to: 3 - type: integer Parameter P_OKAY bound to: 2'b00 Parameter P_EXOKAY bound to: 2'b01 Parameter P_SLVERR bound to: 2'b10 Parameter P_DECERR bound to: 2'b11 Parameter B_RESP_PERF bound to: 1'b1 Parameter C_WIDTH bound to: 5 - type: integer Parameter C_AWIDTH bound to: 3 - type: integer Parameter C_DEPTH bound to: 8 - type: integer Parameter C_EMPTY bound to: 4'b1111 Parameter C_EMPTY_PRE bound to: 3'b000 Parameter C_FULL bound to: 3'b111 Parameter C_FULL_PRE bound to: 3'b110 Parameter C_ID_WIDTH bound to: 5 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_MC_ADDR_WIDTH bound to: 29 - type: integer Parameter C_DATA_WIDTH bound to: 256 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_MC_nCK_PER_CLK bound to: 4 - type: integer Parameter C_AXSIZE bound to: 5 - type: integer Parameter P_CMD_WRITE bound to: 3'b000 Parameter P_CMD_READ bound to: 3'b001 Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_MC_ADDR_WIDTH bound to: 29 - type: integer Parameter C_DATA_WIDTH bound to: 256 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_MC_nCK_PER_CLK bound to: 4 - type: integer Parameter C_AXSIZE bound to: 5 - type: integer Parameter C_MC_RD_INST bound to: 1 - type: integer Parameter P_MC_BURST_MASK bound to: 29'b11111111111111111111111111000 Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_MC_ADDR_WIDTH bound to: 29 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_DATA_WIDTH bound to: 256 - type: integer Parameter C_AXSIZE bound to: 5 - type: integer Parameter C_MC_RD_INST bound to: 1 - type: integer Parameter P_AXLEN_WIDTH bound to: 8 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_MC_ADDR_WIDTH bound to: 29 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_DATA_WIDTH bound to: 256 - type: integer Parameter C_AXSIZE bound to: 5 - type: integer Parameter C_MC_RD_INST bound to: 1 - type: integer Parameter P_AXLEN_WIDTH bound to: 4 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_MC_RD_INST bound to: 1 - type: integer Parameter C_ID_WIDTH bound to: 5 - type: integer Parameter C_DATA_WIDTH bound to: 256 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_AXI_ADDR_WIDTH bound to: 30 - type: integer Parameter C_MC_nCK_PER_CLK bound to: 2 - type: integer Parameter C_MC_BURST_MODE bound to: 8 - type: string Parameter P_WIDTH bound to: 8 - type: integer Parameter P_DEPTH bound to: 30 - type: integer Parameter P_AWIDTH bound to: 5 - type: integer Parameter P_D_WIDTH bound to: 257 - type: integer Parameter P_D_DEPTH bound to: 32 - type: integer Parameter P_D_AWIDTH bound to: 5 - type: integer Parameter P_OKAY bound to: 2'b00 Parameter P_EXOKAY bound to: 2'b01 Parameter P_SLVERR bound to: 2'b10 Parameter P_DECERR bound to: 2'b11 Parameter ZERO bound to: 2'b10 Parameter ONE bound to: 2'b11 Parameter TWO bound to: 2'b01 WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:189] Parameter C_WIDTH bound to: 257 - type: integer Parameter C_AWIDTH bound to: 5 - type: integer Parameter C_DEPTH bound to: 32 - type: integer Parameter C_EMPTY bound to: 6'b111111 Parameter C_EMPTY_PRE bound to: 5'b00000 Parameter C_FULL bound to: 5'b11111 Parameter C_FULL_PRE bound to: 5'b11110 Parameter C_WIDTH bound to: 8 - type: integer Parameter C_AWIDTH bound to: 5 - type: integer Parameter C_DEPTH bound to: 30 - type: integer Parameter C_EMPTY bound to: 6'b111111 Parameter C_EMPTY_PRE bound to: 5'b00000 Parameter C_FULL bound to: 5'b11101 Parameter C_FULL_PRE bound to: 5'b11100 INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:315] Parameter C_MC_ADDR_WIDTH bound to: 29 - type: integer Parameter C_MC_BURST_LEN bound to: 1 - type: integer Parameter C_AXI_WR_STARVE_LIMIT bound to: 256 - type: integer Parameter C_AXI_STARVE_CNT_WIDTH bound to: 8 - type: integer Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2508.285 ; gain = 383.828 ; free physical = 14877 ; free virtual = 36817 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2526.098 ; gain = 401.641 ; free physical = 14939 ; free virtual = 36879 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2526.098 ; gain = 401.641 ; free physical = 14939 ; free virtual = 36879 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2529.066 ; gain = 0.000 ; free physical = 14891 ; free virtual = 36831 INFO: [Netlist 29-17] Analyzing 442 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3_ooc.xdc] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3_ooc.xdc] Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc:544] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc:551] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/xlnx_mig_7_ddr3_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/xlnx_mig_7_ddr3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Timing 38-2] Deriving generated clocks Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2702.723 ; gain = 0.000 ; free physical = 14729 ; free virtual = 36669 INFO: [Project 1-111] Unisim Transformation Summary: A total of 159 instances were transformed. IBUFGDS => IBUFDS: 1 instance IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 26 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 96 instances Constraint Validation Runtime : Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2702.723 ; gain = 0.000 ; free physical = 14728 ; free virtual = 36668 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:52 ; elapsed = 00:00:53 . Memory (MB): peak = 2702.723 ; gain = 578.266 ; free physical = 14921 ; free virtual = 36861 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mig_7series_v4_2_axi_mc_r_channel' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- INIT_IDLE | 0001 | 000 REQUEST_READ_TEMP | 1000 | 001 WAIT_FOR_READ | 0100 | 010 READ | 0010 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'xadc_supplied_temperature.tempmon_state_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_tempmon' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- WL_IDLE | 01110 | 00000 WL_INIT | 10010 | 00001 WL_INIT_FINE_INC | 01100 | 00010 WL_INIT_FINE_INC_WAIT1 | 01000 | 00011 WL_INIT_FINE_INC_WAIT | 01001 | 00100 WL_INIT_FINE_DEC | 11001 | 00101 WL_INIT_FINE_DEC_WAIT1 | 10111 | 11001 WL_INIT_FINE_DEC_WAIT | 11000 | 00110 WL_WAIT | 00110 | 01000 WL_EDGE_CHECK | 11011 | 01001 WL_DQS_CNT | 10100 | 01011 WL_FINE_DEC | 00000 | 01110 WL_FINE_DEC_WAIT1 | 00001 | 11010 WL_FINE_DEC_WAIT | 10001 | 01111 WL_CORSE_DEC | 10110 | 10100 WL_CORSE_DEC_WAIT | 11010 | 10101 WL_CORSE_DEC_WAIT1 | 10101 | 10110 WL_2RANK_DQS_CNT | 00010 | 01101 WL_DQS_CHECK | 00011 | 01010 WL_FINE_INC | 01101 | 00111 WL_FINE_INC_WAIT | 10011 | 10111 WL_2RANK_FINAL_TAP | 01111 | 11000 WL_CORSE_INC | 01011 | 10000 WL_CORSE_INC_WAIT_TMP | 10000 | 11011 WL_CORSE_INC_WAIT | 01010 | 10001 WL_CORSE_INC_WAIT1 | 00111 | 10010 WL_CORSE_INC_WAIT2 | 00101 | 10011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'wl_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_wrlvl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 0001 | 00 iSTATE0 | 0010 | 01 iSTATE1 | 0100 | 10 iSTATE2 | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sm_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_poc_tap_base' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 000 | 000 iSTATE5 | 001 | 001 iSTATE0 | 010 | 010 iSTATE1 | 011 | 011 iSTATE2 | 100 | 100 iSTATE3 | 101 | 101 iSTATE4 | 110 | 110 iSTATE6 | 111 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'sm_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_ocd_cntlr' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FINE_ADJ_IDLE | 0000 | 0000 RST_WAIT | 0001 | 0011 FINE_ADJ_DONE | 0010 | 1111 RST_POSTWAIT | 0011 | 0001 RST_POSTWAIT1 | 0100 | 0010 FINE_ADJ_INIT | 0101 | 0100 FINE_INC | 0110 | 0101 FINE_INC_WAIT | 0111 | 0110 FINE_INC_PREWAIT | 1000 | 0111 DETECT_PREWAIT | 1001 | 1000 DETECT_DQSFOUND | 1010 | 1001 FINE_DEC | 1011 | 1011 FINE_DEC_WAIT | 1100 | 1100 FINE_DEC_PREWAIT | 1101 | 1101 FINAL_WAIT | 1110 | 1110 PRECH_WAIT | 1111 | 1010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fine_adj_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- CAL1_IDLE | 000000000000000000000000000000000100 | 000000 CAL1_NEW_DQS_WAIT | 000000000000000000000100000000000000 | 000001 CAL1_STORE_FIRST_WAIT | 000000000000000000100000000000000000 | 000010 CAL1_PAT_DETECT | 000000000000001000000000000000000000 | 000011 CAL1_DQ_IDEL_TAP_INC | 000000000000000000000000000000100000 | 000100 CAL1_DQ_IDEL_TAP_INC_WAIT | 000000000000000000000000000001000000 | 000101 CAL1_MPR_PAT_DETECT | 000000000000000000000000100000000000 | 011111 CAL1_VALID_WAIT | 100000000000000000000000000000000000 | 011110 CAL1_DETECT_EDGE | 000100000000000000000000000000000000 | 001000 CAL1_CALC_IDEL | 000000100000000000000000000000000000 | 001011 CAL1_CENTER_WAIT | 000000000000000000000000000000001000 | 100010 CAL1_IDEL_DEC_CPT | 000000000000000000000000000000010000 | 001100 CAL1_DQ_IDEL_TAP_DEC | 000000000000000000010000000000000000 | 000110 CAL1_DQ_IDEL_TAP_DEC_WAIT | 001000000000000000000000000000000000 | 000111 CAL1_NEXT_DQS | 000000000000000000000000000010000000 | 001110 CAL1_REGL_LOAD | 000000000000000000000000000100000000 | 011011 CAL1_DONE | 000000000000000000000000000000000001 | 001111 iSTATE | 000000000000000000000000000000000010 | 111111 CAL1_NEW_DQS_PREWAIT | 000000000000000000000000001000000000 | 100000 CAL1_MPR_NEW_DQS_WAIT | 000000000000000000000000010000000000 | 011101 CAL1_IDEL_DEC_CPT_WAIT | 000000000000000000001000000000000000 | 001101 CAL1_RD_STOP_FOR_PI_INC | 000000000000000000000001000000000000 | 100001 CAL1_IDEL_INC_CPT | 000000000000000000000010000000000000 | 001001 CAL1_IDEL_INC_CPT_WAIT | 000010000000000000000000000000000000 | 001010 CAL1_RDLVL_ERR | 000000000000010000000000000000000000 | 011100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'cal1_state_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_ddr_phy_rdlvl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- * IDLE | 00000000001 | 00000000001 INIT | 00000000010 | 00000000010 NEUTRAL | 00001000000 | 00001000000 ONE_DEC | 00010000000 | 00010000000 TWO_DEC | 00100000000 | 00100000000 THREE_DEC | 01000000000 | 01000000000 FOUR_DEC | 10000000000 | 10000000000 ONE_INC | 00000100000 | 00000100000 TWO_INC | 00000010000 | 00000010000 THREE_INC | 00000001000 | 00000001000 FOUR_INC | 00000000100 | 00000000100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- ZERO | 11 | 10 ONE | 01 | 11 TWO | 00 | 01 iSTATE | 10 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:24 ; elapsed = 00:01:31 . Memory (MB): peak = 2702.723 ; gain = 578.266 ; free physical = 11572 ; free virtual = 33518 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 2 3 Input 32 Bit Adders := 5 2 Input 30 Bit Adders := 2 3 Input 18 Bit Adders := 1 2 Input 18 Bit Adders := 1 2 Input 17 Bit Adders := 1 2 Input 13 Bit Adders := 1 2 Input 12 Bit Adders := 16 2 Input 11 Bit Adders := 2 2 Input 10 Bit Adders := 10 2 Input 9 Bit Adders := 4 2 Input 8 Bit Adders := 16 3 Input 8 Bit Adders := 2 2 Input 7 Bit Adders := 11 3 Input 7 Bit Adders := 4 2 Input 6 Bit Adders := 60 3 Input 6 Bit Adders := 34 4 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 50 2 Input 4 Bit Adders := 40 2 Input 3 Bit Adders := 34 3 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 57 4 Input 2 Bit Adders := 5 8 Input 2 Bit Adders := 1 3 Input 2 Bit Adders := 3 5 Input 2 Bit Adders := 1 2 Input 1 Bit Adders := 4 3 Input 1 Bit Adders := 1 4 Input 1 Bit Adders := 1 5 Input 1 Bit Adders := 1 6 Input 1 Bit Adders := 1 7 Input 1 Bit Adders := 1 8 Input 1 Bit Adders := 1 9 Input 1 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 22 +---Registers : 288 Bit Registers := 1 264 Bit Registers := 2 256 Bit Registers := 6 160 Bit Registers := 1 88 Bit Registers := 1 80 Bit Registers := 4 65 Bit Registers := 2 64 Bit Registers := 4 60 Bit Registers := 1 32 Bit Registers := 8 30 Bit Registers := 11 29 Bit Registers := 2 24 Bit Registers := 10 18 Bit Registers := 2 17 Bit Registers := 1 16 Bit Registers := 9 15 Bit Registers := 11 14 Bit Registers := 1 13 Bit Registers := 1 12 Bit Registers := 32 11 Bit Registers := 2 10 Bit Registers := 8 9 Bit Registers := 18 8 Bit Registers := 43 7 Bit Registers := 9 6 Bit Registers := 156 5 Bit Registers := 69 4 Bit Registers := 106 3 Bit Registers := 80 2 Bit Registers := 85 1 Bit Registers := 2040 +---ROMs : ROMs := 1 +---Muxes : 4 Input 800 Bit Muxes := 2 2 Input 800 Bit Muxes := 1 2 Input 264 Bit Muxes := 1 2 Input 256 Bit Muxes := 11 4 Input 256 Bit Muxes := 1 2 Input 255 Bit Muxes := 1 2 Input 80 Bit Muxes := 12 2 Input 64 Bit Muxes := 2 4 Input 64 Bit Muxes := 2 2 Input 60 Bit Muxes := 1 2 Input 41 Bit Muxes := 2 24 Input 36 Bit Muxes := 1 2 Input 36 Bit Muxes := 23 2 Input 32 Bit Muxes := 9 2 Input 30 Bit Muxes := 40 4 Input 30 Bit Muxes := 8 2 Input 29 Bit Muxes := 1 2 Input 24 Bit Muxes := 26 10 Input 24 Bit Muxes := 2 2 Input 22 Bit Muxes := 8 4 Input 18 Bit Muxes := 1 4 Input 17 Bit Muxes := 1 3 Input 16 Bit Muxes := 1 3 Input 15 Bit Muxes := 1 2 Input 15 Bit Muxes := 8 4 Input 15 Bit Muxes := 1 8 Input 15 Bit Muxes := 1 2 Input 14 Bit Muxes := 1 15 Input 14 Bit Muxes := 1 3 Input 13 Bit Muxes := 2 2 Input 12 Bit Muxes := 3 3 Input 12 Bit Muxes := 2 7 Input 11 Bit Muxes := 1 6 Input 11 Bit Muxes := 1 5 Input 11 Bit Muxes := 1 12 Input 11 Bit Muxes := 1 2 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 8 3 Input 10 Bit Muxes := 1 4 Input 10 Bit Muxes := 1 4 Input 9 Bit Muxes := 11 2 Input 9 Bit Muxes := 35 2 Input 8 Bit Muxes := 138 5 Input 8 Bit Muxes := 1 6 Input 8 Bit Muxes := 1 4 Input 8 Bit Muxes := 1 8 Input 8 Bit Muxes := 2 2 Input 7 Bit Muxes := 72 3 Input 7 Bit Muxes := 2 4 Input 7 Bit Muxes := 4 5 Input 7 Bit Muxes := 3 2 Input 6 Bit Muxes := 151 4 Input 6 Bit Muxes := 19 3 Input 6 Bit Muxes := 4 5 Input 6 Bit Muxes := 2 23 Input 6 Bit Muxes := 6 25 Input 6 Bit Muxes := 5 16 Input 6 Bit Muxes := 1 27 Input 6 Bit Muxes := 6 2 Input 5 Bit Muxes := 47 8 Input 5 Bit Muxes := 9 4 Input 5 Bit Muxes := 5 5 Input 5 Bit Muxes := 2 3 Input 5 Bit Muxes := 7 25 Input 5 Bit Muxes := 1 27 Input 5 Bit Muxes := 1 58 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 87 7 Input 4 Bit Muxes := 1 10 Input 4 Bit Muxes := 1 3 Input 4 Bit Muxes := 3 8 Input 4 Bit Muxes := 1 5 Input 4 Bit Muxes := 1 32 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 106 4 Input 3 Bit Muxes := 15 10 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 2 9 Input 3 Bit Muxes := 2 8 Input 3 Bit Muxes := 2 23 Input 3 Bit Muxes := 1 25 Input 3 Bit Muxes := 1 27 Input 3 Bit Muxes := 11 2 Input 2 Bit Muxes := 100 3 Input 2 Bit Muxes := 13 8 Input 2 Bit Muxes := 9 4 Input 2 Bit Muxes := 5 5 Input 2 Bit Muxes := 2 10 Input 2 Bit Muxes := 2 23 Input 2 Bit Muxes := 6 25 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 922 3 Input 1 Bit Muxes := 38 4 Input 1 Bit Muxes := 173 8 Input 1 Bit Muxes := 19 10 Input 1 Bit Muxes := 39 15 Input 1 Bit Muxes := 28 5 Input 1 Bit Muxes := 2 23 Input 1 Bit Muxes := 33 7 Input 1 Bit Muxes := 1 25 Input 1 Bit Muxes := 30 16 Input 1 Bit Muxes := 21 27 Input 1 Bit Muxes := 35 12 Input 1 Bit Muxes := 4 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 840 (col length:140) BRAMs: 890 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:04:22 ; elapsed = 00:04:42 . Memory (MB): peak = 2895.871 ; gain = 771.414 ; free physical = 11455 ; free virtual = 33440 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +------------------------------------+-------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------------------------------+-------------+---------------+----------------+ |mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | |mig_7series_v4_2_ddr_phy_prbs_rdlvl | dec_cnt_reg | 4096x6 | Block RAM | |mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | +------------------------------------+-------------+---------------+----------------+ Distributed RAM: Preliminary Mapping Report (see note below) +--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+ |xlnx_mig_7_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |xlnx_mig_7_ddr3 | ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |xlnx_mig_7_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |xlnx_mig_7_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_A.ddr_byte_lane_A | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_A.ddr_byte_lane_A | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_B.ddr_byte_lane_B | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_B.ddr_byte_lane_B | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_C.ddr_byte_lane_C | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_C.ddr_byte_lane_C | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_D.ddr_byte_lane_D | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_D.ddr_byte_lane_D | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 557 of /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc:557] --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:04:30 ; elapsed = 00:04:51 . Memory (MB): peak = 2895.871 ; gain = 771.414 ; free physical = 11366 ; free virtual = 33351 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:04:35 ; elapsed = 00:04:57 . Memory (MB): peak = 2895.871 ; gain = 771.414 ; free physical = 11357 ; free virtual = 33342 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+ |xlnx_mig_7_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |xlnx_mig_7_ddr3 | ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |xlnx_mig_7_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |xlnx_mig_7_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_A.ddr_byte_lane_A | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_A.ddr_byte_lane_A | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_B.ddr_byte_lane_B | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_B.ddr_byte_lane_B | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_C.ddr_byte_lane_C | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_C.ddr_byte_lane_C | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_D.ddr_byte_lane_D | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | |u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_D.ddr_byte_lane_D | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-7052] The timing for the instance u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/dec_cnt_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:04:49 ; elapsed = 00:05:10 . Memory (MB): peak = 2895.871 ; gain = 771.414 ; free physical = 11381 ; free virtual = 33366 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:04:54 ; elapsed = 00:05:16 . Memory (MB): peak = 2895.871 ; gain = 771.414 ; free physical = 11381 ; free virtual = 33366 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:04:54 ; elapsed = 00:05:16 . Memory (MB): peak = 2895.871 ; gain = 771.414 ; free physical = 11381 ; free virtual = 33366 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:04:58 ; elapsed = 00:05:20 . Memory (MB): peak = 2895.871 ; gain = 771.414 ; free physical = 11381 ; free virtual = 33366 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:04:58 ; elapsed = 00:05:20 . Memory (MB): peak = 2895.871 ; gain = 771.414 ; free physical = 11381 ; free virtual = 33366 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:04:59 ; elapsed = 00:05:21 . Memory (MB): peak = 2895.871 ; gain = 771.414 ; free physical = 11380 ; free virtual = 33365 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:04:59 ; elapsed = 00:05:21 . Memory (MB): peak = 2895.871 ; gain = 771.414 ; free physical = 11380 ; free virtual = 33365 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] | 3 | 4 | NO | NO | YES | 4 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r7_reg | 6 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclkdelay_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_reg | 17 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14] | 15 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_too_small_r3_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_end_r3_reg | 4 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/init_dqsfound_done_r5_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r5_reg | 5 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r9_reg | 9 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/rst_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | |xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 | +----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ Dynamic Shift Register Report: +------------+----------------+--------+------------+--------+---------+--------+--------+--------+ |Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | +------------+----------------+--------+------------+--------+---------+--------+--------+--------+ |dsrl | memory_reg[7] | 5 | 5 | 5 | 0 | 0 | 0 | 0 | |dsrl__1 | memory_reg[31] | 257 | 257 | 0 | 257 | 0 | 0 | 0 | |dsrl__2 | memory_reg[29] | 8 | 8 | 0 | 8 | 0 | 0 | 0 | +------------+----------------+--------+------------+--------+---------+--------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----------------------+------+ | |Cell |Count | +------+-----------------------+------+ |1 |AND2B1L | 12| |2 |BUFG | 5| |3 |BUFH | 1| |4 |BUFIO | 2| |5 |CARRY4 | 298| |6 |IDDR | 4| |7 |IDELAYCTRL | 2| |8 |IDELAYE2_FINEDELAY | 32| |9 |IN_FIFO | 4| |10 |ISERDESE2 | 32| |11 |LUT1 | 491| |12 |LUT2 | 982| |13 |LUT3 | 2292| |14 |LUT4 | 1637| |15 |LUT5 | 2332| |16 |LUT6 | 3416| |18 |MMCME2_ADV | 2| |19 |MUXCY | 147| |20 |MUXF7 | 19| |21 |ODDR | 9| |22 |OR2L | 2| |23 |OSERDESE2 | 64| |26 |OUT_FIFO | 8| |28 |PHASER_IN_PHY | 4| |29 |PHASER_OUT_PHY | 8| |31 |PHASER_REF | 2| |32 |PHY_CONTROL | 2| |33 |PLLE2_ADV | 1| |34 |RAM32M | 221| |35 |RAMB36E1 | 1| |36 |SRL16E | 24| |37 |SRLC32E | 338| |38 |XADC | 1| |39 |XORCY | 62| |40 |FDCE | 3| |41 |FDPE | 96| |42 |FDRE | 8162| |43 |FDSE | 336| |44 |IBUFGDS | 1| |45 |IOBUFDS_DIFF_OUT_DCIEN | 4| |46 |IOBUF_DCIEN | 32| |47 |OBUF | 25| |48 |OBUFDS | 1| |49 |OBUFT | 4| +------+-----------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:04:59 ; elapsed = 00:05:21 . Memory (MB): peak = 2895.871 ; gain = 771.414 ; free physical = 11380 ; free virtual = 33365 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:04:48 ; elapsed = 00:05:13 . Memory (MB): peak = 2899.781 ; gain = 598.699 ; free physical = 14831 ; free virtual = 36816 Synthesis Optimization Complete : Time (s): cpu = 00:05:05 ; elapsed = 00:05:26 . Memory (MB): peak = 2899.781 ; gain = 775.324 ; free physical = 14831 ; free virtual = 36816 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2899.781 ; gain = 0.000 ; free physical = 14820 ; free virtual = 36805 INFO: [Netlist 29-17] Analyzing 861 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 4 inverter(s) to 32 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2935.891 ; gain = 0.000 ; free physical = 14770 ; free virtual = 36755 INFO: [Project 1-111] Unisim Transformation Summary: A total of 330 instances were transformed. (MUXCY,XORCY) => CARRY4: 45 instances IBUFGDS => IBUFDS: 1 instance IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 26 instances OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 221 instances INFO: [Common 17-83] Releasing license: Synthesis 253 Infos, 34 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:05:18 ; elapsed = 00:05:42 . Memory (MB): peak = 2935.891 ; gain = 819.438 ; free physical = 14924 ; free virtual = 36909 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2967.906 ; gain = 32.016 ; free physical = 14919 ; free virtual = 36908 WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_mig_7_ddr3, cache-ID = a106d510a77f751f INFO: [Coretcl 2-1174] Renamed 216 cell refs. WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2967.906 ; gain = 0.000 ; free physical = 14900 ; free virtual = 36913 INFO: [runtcl-4] Executing : report_utilization -file xlnx_mig_7_ddr3_utilization_synth.rpt -pb xlnx_mig_7_ddr3_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:58:51 2023... [Tue Oct 10 08:59:02 2023] xlnx_mig_7_ddr3_synth_1 finished wait_on_run: Time (s): cpu = 00:05:56 ; elapsed = 00:06:28 . Memory (MB): peak = 2197.680 ; gain = 6.453 ; free physical = 16031 ; free virtual = 38017 INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 08:59:02 2023... #vivado -mode batch -source tcl/run.tcl make[2]: Leaving directory '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3' mkdir -p work-fpga vivado -nojournal -mode batch -source scripts/prologue.tcl -source scripts/run.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source scripts/prologue.tcl # set project ariane # create_project $project . -force -part $::env(XILINX_PART) # set_property board_part $::env(XILINX_BOARD) [current_project] # set_param general.maxThreads 20 # set_msg_config -id {[Synth 8-5858]} -new_severity "info" # set_msg_config -id {[Synth 8-4480]} -limit 1000 source scripts/run.tcl # if {$::env(BOARD) eq "genesys2"} { # add_files -fileset constrs_1 -norecurse constraints/genesys-2.xdc # } elseif {$::env(BOARD) eq "kc705"} { # add_files -fileset constrs_1 -norecurse constraints/kc705.xdc # } elseif {$::env(BOARD) eq "vc707"} { # add_files -fileset constrs_1 -norecurse constraints/vc707.xdc # } else { # exit 1 # } # read_ip { \ # "xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci" \ # "xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci" \ # "xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.xci" \ # "xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci" \ # "xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.xci" \ # "xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xci" \ # "xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xci" \ # "xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xci" \ # } INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.1/data/ip'. # set_property include_dirs { "src/axi_sd_bridge/include" "../../vendor/pulp-platform/common_cells/include" "../../vendor/pulp-platform/axi/include" "../register_interface/include"} [current_fileset] # source scripts/add_sources.tcl ## read_vhdl {/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd /home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_transmitter.vhd /home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_interrupt.vhd /home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_mv_filter.vhd /home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd /home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_counter.vhd /home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd /home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd /home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd /home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_clock_div.vhd /home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd /home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_baudgen.vhd} ## read_verilog -sv {/home/darshak/cva6/corev_apu/register_interface/src/reg_intf.sv /home/darshak/cva6/corev_apu/tb/ariane_soc_pkg.sv /home/darshak/cva6/corev_apu/riscv-dbg/src/dm_pkg.sv /home/darshak/cva6/corev_apu/tb/ariane_axi_soc_pkg.sv} ## read_verilog -sv {/home/darshak/cva6/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv /home/darshak/cva6/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv /home/darshak/cva6/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv /home/darshak/cva6/core/include/cv64a6_imafdc_sv39_config_pkg.sv /home/darshak/cva6/core/include/riscv_pkg.sv /home/darshak/cva6/common/local/rvfi/rvfi_pkg.sv /home/darshak/cva6/core/include/ariane_dm_pkg.sv /home/darshak/cva6/core/include/ariane_pkg.sv /home/darshak/cva6/vendor/pulp-platform/axi/src/axi_pkg.sv /home/darshak/cva6/core/include/ariane_axi_pkg.sv /home/darshak/cva6/core/include/wt_cache_pkg.sv /home/darshak/cva6/core/include/std_cache_pkg.sv /home/darshak/cva6/core/include/axi_intf.sv /home/darshak/cva6/core/include/cvxif_pkg.sv /home/darshak/cva6/core/cvxif_example/include/cvxif_instr_pkg.sv /home/darshak/cva6/core/cvxif_fu.sv /home/darshak/cva6/core/cvxif_example/cvxif_example_coprocessor.sv /home/darshak/cva6/core/cvxif_example/instr_decoder.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/stream_mux.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/stream_demux.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/shift_reg.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/unread.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/popcount.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/exp_backoff.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/counter.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_cast_multi.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_classifier.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_divsqrt_multi.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_fma_multi.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_fma.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_noncomp.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_block.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_fmt_slice.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_opgroup_multifmt_slice.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_top.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv /home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv /home/darshak/cva6/core/cva6.sv /home/darshak/cva6/core/alu.sv /home/darshak/cva6/core/fpu_wrap.sv /home/darshak/cva6/core/branch_unit.sv /home/darshak/cva6/core/compressed_decoder.sv /home/darshak/cva6/core/controller.sv /home/darshak/cva6/core/csr_buffer.sv /home/darshak/cva6/core/csr_regfile.sv /home/darshak/cva6/core/decoder.sv /home/darshak/cva6/core/ex_stage.sv /home/darshak/cva6/core/instr_realign.sv /home/darshak/cva6/core/id_stage.sv /home/darshak/cva6/core/issue_read_operands.sv /home/darshak/cva6/core/issue_stage.sv /home/darshak/cva6/core/load_unit.sv /home/darshak/cva6/core/load_store_unit.sv /home/darshak/cva6/core/lsu_bypass.sv /home/darshak/cva6/core/mult.sv /home/darshak/cva6/core/multiplier.sv /home/darshak/cva6/core/serdiv.sv /home/darshak/cva6/core/perf_counters.sv /home/darshak/cva6/core/ariane_regfile_ff.sv /home/darshak/cva6/core/ariane_regfile_fpga.sv /home/darshak/cva6/core/re_name.sv /home/darshak/cva6/core/scoreboard.sv /home/darshak/cva6/core/store_buffer.sv /home/darshak/cva6/core/amo_buffer.sv /home/darshak/cva6/core/store_unit.sv /home/darshak/cva6/core/commit_stage.sv /home/darshak/cva6/core/axi_shim.sv /home/darshak/cva6/core/frontend/btb.sv /home/darshak/cva6/core/frontend/bht.sv /home/darshak/cva6/core/frontend/ras.sv /home/darshak/cva6/core/frontend/instr_scan.sv /home/darshak/cva6/core/frontend/instr_queue.sv /home/darshak/cva6/core/frontend/frontend.sv /home/darshak/cva6/core/cache_subsystem/wt_dcache_ctrl.sv /home/darshak/cva6/core/cache_subsystem/wt_dcache_mem.sv /home/darshak/cva6/core/cache_subsystem/wt_dcache_missunit.sv /home/darshak/cva6/core/cache_subsystem/wt_dcache_wbuffer.sv /home/darshak/cva6/core/cache_subsystem/wt_dcache.sv /home/darshak/cva6/core/cache_subsystem/cva6_icache.sv /home/darshak/cva6/core/cache_subsystem/wt_cache_subsystem.sv /home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv /home/darshak/cva6/core/cache_subsystem/tag_cmp.sv /home/darshak/cva6/core/cache_subsystem/axi_adapter.sv /home/darshak/cva6/core/cache_subsystem/miss_handler.sv /home/darshak/cva6/core/cache_subsystem/cache_ctrl.sv /home/darshak/cva6/core/cache_subsystem/cva6_icache_axi_wrapper.sv /home/darshak/cva6/core/cache_subsystem/std_cache_subsystem.sv /home/darshak/cva6/core/cache_subsystem/std_nbdcache.sv /home/darshak/cva6/core/pmp/src/pmp.sv /home/darshak/cva6/core/pmp/src/pmp_entry.sv /home/darshak/cva6/common/local/util/sram.sv /home/darshak/cva6/core/mmu_sv39/mmu.sv /home/darshak/cva6/core/mmu_sv39/ptw.sv /home/darshak/cva6/core/mmu_sv39/tlb.sv /home/darshak/cva6/core/mmu_sv32/cva6_mmu_sv32.sv /home/darshak/cva6/core/mmu_sv32/cva6_ptw_sv32.sv /home/darshak/cva6/core/mmu_sv32/cva6_tlb_sv32.sv /home/darshak/cva6/core/mmu_sv32/cva6_shared_tlb_sv32.sv} ## read_verilog -sv {/home/darshak/cva6/core/include/cv64a6_imafdc_sv39_config_pkg.sv /home/darshak/cva6/corev_apu/src/ariane.sv /home/darshak/cva6/corev_apu/clint/axi_lite_interface.sv /home/darshak/cva6/corev_apu/clint/clint.sv /home/darshak/cva6/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv /home/darshak/cva6/corev_apu/fpga/src/axi2apb/src/axi2apb.sv /home/darshak/cva6/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv /home/darshak/cva6/corev_apu/fpga/src/apb_timer/apb_timer.sv /home/darshak/cva6/corev_apu/fpga/src/apb_timer/timer.sv /home/darshak/cva6/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv /home/darshak/cva6/corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv /home/darshak/cva6/corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv /home/darshak/cva6/corev_apu/fpga/src/axi_slice/src/axi_slice.sv /home/darshak/cva6/corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv /home/darshak/cva6/corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv /home/darshak/cva6/corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv /home/darshak/cva6/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv /home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv /home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics.sv /home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_res_tbl.sv /home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv /home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv /home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv /home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv /home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv /home/darshak/cva6/corev_apu/rv_plic/rtl/rv_plic_target.sv /home/darshak/cva6/corev_apu/rv_plic/rtl/rv_plic_gateway.sv /home/darshak/cva6/corev_apu/rv_plic/rtl/plic_regmap.sv /home/darshak/cva6/corev_apu/rv_plic/rtl/plic_top.sv /home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_cdc.sv /home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv /home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv /home/darshak/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv /home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv /home/darshak/cva6/corev_apu/riscv-dbg/src/dm_sba.sv /home/darshak/cva6/corev_apu/riscv-dbg/src/dm_top.sv /home/darshak/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom.sv /home/darshak/cva6/corev_apu/register_interface/src/apb_to_reg.sv /home/darshak/cva6/vendor/pulp-platform/axi/src/axi_multicut.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/rstgen.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/addr_decode.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/stream_register.sv /home/darshak/cva6/vendor/pulp-platform/axi/src/axi_cut.sv /home/darshak/cva6/vendor/pulp-platform/axi/src/axi_join.sv /home/darshak/cva6/vendor/pulp-platform/axi/src/axi_delayer.sv /home/darshak/cva6/vendor/pulp-platform/axi/src/axi_to_axi_lite.sv /home/darshak/cva6/vendor/pulp-platform/axi/src/axi_id_prepend.sv /home/darshak/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv /home/darshak/cva6/vendor/pulp-platform/axi/src/axi_err_slv.sv /home/darshak/cva6/vendor/pulp-platform/axi/src/axi_mux.sv /home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv /home/darshak/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/stream_delay.sv /home/darshak/cva6/vendor/pulp-platform/common_cells/src/lfsr_16bit.sv /home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv /home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv /home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv /home/darshak/cva6/corev_apu/tb/ariane_testharness.sv /home/darshak/cva6/corev_apu/tb/ariane_peripherals.sv /home/darshak/cva6/corev_apu/tb/rvfi_tracer.sv /home/darshak/cva6/corev_apu/tb/common/uart.sv /home/darshak/cva6/corev_apu/tb/common/SimDTM.sv /home/darshak/cva6/corev_apu/tb/common/SimJTAG.sv} WARNING: [filemgmt 56-12] File '/home/darshak/cva6/core/include/cv64a6_imafdc_sv39_config_pkg.sv' cannot be added to the project because it already exists in the project, skipping this file ## read_verilog -sv {/home/darshak/cva6/corev_apu/fpga/src/ariane_peripherals_xilinx.sv /home/darshak/cva6/corev_apu/fpga/src/fan_ctrl.sv /home/darshak/cva6/corev_apu/fpga/src/ariane_xilinx.sv /home/darshak/cva6/corev_apu/fpga/src/bootrom/bootrom_32.sv /home/darshak/cva6/corev_apu/fpga/src/bootrom/bootrom_64.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/ssio_ddr_in.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/rgmii_soc.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/axis_gmii_rx.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/oddr.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/axis_gmii_tx.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/dualmem_widen8.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/eth_mac_1g_rgmii.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/dualmem_widen.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/rgmii_lfsr.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/rgmii_core.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/eth_mac_1g.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/rgmii_phy_if.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/eth_mac_1g_rgmii_fifo.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/iddr.sv /home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/framing_top.sv /home/darshak/cva6/common/local/util/tc_sram_fpga_wrapper.sv /home/darshak/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv} # set_property top ${project}_xilinx [current_fileset] # if {$::env(BOARD) eq "genesys2"} { # read_verilog -sv {src/genesysii.svh ../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh} # set file "src/genesysii.svh" # set registers "../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh" # } elseif {$::env(BOARD) eq "kc705"} { # read_verilog -sv {src/kc705.svh ../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh} # set file "src/kc705.svh" # set registers "../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh" # } elseif {$::env(BOARD) eq "vc707"} { # read_verilog -sv {src/vc707.svh ../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh} # set file "src/vc707.svh" # set registers "../../vendor/pulp-platform/common_cells/include/common_cells/registers.svh" # } else { # exit 1 # } # set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file" "$registers"]] # set_property -dict { file_type {Verilog Header} is_global_include 1} -objects $file_obj # update_compile_order -fileset sources_1 # add_files -fileset constrs_1 -norecurse constraints/$project.xdc # synth_design -rtl -name rtl_1 Command: synth_design -rtl -name rtl_1 Starting synth_design Using part: xc7k325tffg900-2 Top: ariane_xilinx INFO: [Device 21-403] Loading part xc7k325tffg900-2 WARNING: [Synth 8-2507] parameter declaration becomes local in miss_handler with formal parameter declaration list [/home/darshak/cva6/core/cache_subsystem/miss_handler.sv:69] WARNING: [Synth 8-2507] parameter declaration becomes local in rgmii_lfsr with formal parameter declaration list [/home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/rgmii_lfsr.sv:364] --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2205.152 ; gain = 19.637 ; free physical = 15964 ; free virtual = 37951 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'ariane_xilinx' [/home/darshak/cva6/corev_apu/fpga/src/ariane_xilinx.sv:14] Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 2 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter NumWords bound to: 3145728 - type: integer Parameter NBSlave bound to: 2 - type: integer Parameter AxiAddrWidth bound to: 64 - type: integer Parameter AxiDataWidth bound to: 64 - type: integer Parameter AxiIdWidthMaster bound to: 4 - type: integer Parameter AxiIdWidthSlaves bound to: 5 - type: integer Parameter AxiUserWidth bound to: 64 - type: integer Parameter AXI_XBAR_CFG[NoSlvPorts] bound to: 2 - type: integer Parameter AXI_XBAR_CFG[NoMstPorts] bound to: 10 - type: integer Parameter AXI_XBAR_CFG[MaxMstTrans] bound to: 1 - type: integer Parameter AXI_XBAR_CFG[MaxSlvTrans] bound to: 1 - type: integer Parameter AXI_XBAR_CFG[FallThrough] bound to: 1'b0 Parameter AXI_XBAR_CFG[LatencyMode] bound to: 10'b1111111111 Parameter AXI_XBAR_CFG[AxiIdWidthSlvPorts] bound to: 4 - type: integer Parameter AXI_XBAR_CFG[AxiIdUsedSlvPorts] bound to: 4 - type: integer Parameter AXI_XBAR_CFG[UniqueIds] bound to: 1'b0 Parameter AXI_XBAR_CFG[AxiAddrWidth] bound to: 64 - type: integer Parameter AXI_XBAR_CFG[AxiDataWidth] bound to: 64 - type: integer Parameter AXI_XBAR_CFG[NoAddrRules] bound to: 10 - type: integer INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 4 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 4 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'bootrom_64' [/home/darshak/cva6/corev_apu/fpga/src/bootrom/bootrom_64.sv:17] Parameter RomSize bound to: 32'sb00000000000000000000001101111111 INFO: [Synth 8-6155] done synthesizing module 'bootrom_64' (1#1) [/home/darshak/cva6/corev_apu/fpga/src/bootrom/bootrom_64.sv:17] INFO: [Synth 8-6157] synthesizing module 'rstgen' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rstgen.sv:13] INFO: [Synth 8-6157] synthesizing module 'rstgen_bypass' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv:15] Parameter NumRegs bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6155] done synthesizing module 'rstgen_bypass' (2#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv:15] INFO: [Synth 8-6155] done synthesizing module 'rstgen' (3#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rstgen.sv:13] INFO: [Synth 8-6157] synthesizing module 'axi_xbar_intf' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv:242] Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter Cfg[NoSlvPorts] bound to: 2 - type: integer Parameter Cfg[NoMstPorts] bound to: 10 - type: integer Parameter Cfg[MaxMstTrans] bound to: 1 - type: integer Parameter Cfg[MaxSlvTrans] bound to: 1 - type: integer Parameter Cfg[FallThrough] bound to: 1'b0 Parameter Cfg[LatencyMode] bound to: 10'b1111111111 Parameter Cfg[AxiIdWidthSlvPorts] bound to: 4 - type: integer Parameter Cfg[AxiIdUsedSlvPorts] bound to: 4 - type: integer Parameter Cfg[UniqueIds] bound to: 1'b0 Parameter Cfg[AxiAddrWidth] bound to: 64 - type: integer Parameter Cfg[AxiDataWidth] bound to: 64 - type: integer Parameter Cfg[NoAddrRules] bound to: 10 - type: integer Parameter AxiIdWidthMstPorts bound to: 32'b00000000000000000000000000000101 INFO: [Synth 8-6157] synthesizing module 'axi_xbar' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv:18] Parameter Cfg[NoSlvPorts] bound to: 2 - type: integer Parameter Cfg[NoMstPorts] bound to: 10 - type: integer Parameter Cfg[MaxMstTrans] bound to: 1 - type: integer Parameter Cfg[MaxSlvTrans] bound to: 1 - type: integer Parameter Cfg[FallThrough] bound to: 1'b0 Parameter Cfg[LatencyMode] bound to: 10'b1111111111 Parameter Cfg[AxiIdWidthSlvPorts] bound to: 4 - type: integer Parameter Cfg[AxiIdUsedSlvPorts] bound to: 4 - type: integer Parameter Cfg[UniqueIds] bound to: 1'b0 Parameter Cfg[AxiAddrWidth] bound to: 64 - type: integer Parameter Cfg[AxiDataWidth] bound to: 64 - type: integer Parameter Cfg[NoAddrRules] bound to: 10 - type: integer Parameter ATOPs bound to: 1'b1 Parameter cfg_NoMstPorts bound to: 10 - type: integer INFO: [Synth 8-6157] synthesizing module 'addr_decode' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/addr_decode.sv:30] Parameter NoIndices bound to: 10 - type: integer Parameter NoRules bound to: 10 - type: integer Parameter IdxWidth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6155] done synthesizing module 'addr_decode' (4#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/addr_decode.sv:30] INFO: [Synth 8-6157] synthesizing module 'axi_demux' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:19] Parameter AxiIdWidth bound to: 4 - type: integer Parameter NoMstPorts bound to: 32'b00000000000000000000000000001011 Parameter MaxTrans bound to: 1 - type: integer Parameter AxiLookBits bound to: 4 - type: integer Parameter UniqueIds bound to: 1'b0 Parameter FallThrough bound to: 1'b0 Parameter SpillAw bound to: 1'b1 Parameter SpillW bound to: 1'b1 Parameter SpillB bound to: 1'b1 Parameter SpillAr bound to: 1'b1 Parameter SpillR bound to: 1'b1 Parameter SelectWidth bound to: 32'b00000000000000000000000000000100 Parameter IdCounterWidth bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6157] synthesizing module 'axi_demux_id_counters' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:576] Parameter AxiIdBits bound to: 4 - type: integer Parameter CounterWidth bound to: 32'b00000000000000000000000000000001 Parameter NoCounters bound to: 32'b00000000000000000000000000010000 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-6157] synthesizing module 'delta_counter' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] Parameter WIDTH bound to: 32'b00000000000000000000000000000001 Parameter STICKY_OVERFLOW bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'delta_counter' (5#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-6155] done synthesizing module 'axi_demux_id_counters' (6#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:576] INFO: [Synth 8-6157] synthesizing module 'spill_register' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable' (7#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register' (8#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'fifo_v3' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 1 - type: integer Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'fifo_v3' (9#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized0' (9#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized0' (9#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized1' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized1' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized1' (9#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized1' (9#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] Parameter NumIn bound to: 32'b00000000000000000000000000001011 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6157] synthesizing module 'lzc' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] Parameter WIDTH bound to: 32'b00000000000000000000000000001011 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6155] done synthesizing module 'lzc' (10#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree' (11#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized2' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized2' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized2' (11#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized2' (11#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized3' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized3' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized3' (11#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized3' (11#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] Parameter NumIn bound to: 32'b00000000000000000000000000001011 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized0' (11#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6155] done synthesizing module 'axi_demux' (12#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:19] INFO: [Synth 8-6157] synthesizing module 'axi_err_slv' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_err_slv.sv:19] Parameter AxiIdWidth bound to: 4 - type: integer Parameter Resp bound to: 2'b11 Parameter RespWidth bound to: 64 - type: integer Parameter RespData bound to: 64'b1100101000010001101010110001111010111010110111001010101100011110 Parameter ATOPs bound to: 1'b1 Parameter MaxTrans bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6157] synthesizing module 'axi_atop_filter' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv:37] Parameter AxiIdWidth bound to: 4 - type: integer Parameter AxiMaxWriteTxns bound to: 32'b00000000000000000000000000000100 Parameter COUNTER_WIDTH bound to: 32'b00000000000000000000000000000011 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv:118] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv:268] INFO: [Synth 8-6157] synthesizing module 'stream_register' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/stream_register.sv:14] INFO: [Synth 8-6157] synthesizing module 'fifo_v2' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 Parameter ALM_EMPTY_TH bound to: 32'b00000000000000000000000000000001 Parameter ALM_FULL_TH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized0' (12#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6155] done synthesizing module 'fifo_v2' (13#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] INFO: [Synth 8-6155] done synthesizing module 'stream_register' (14#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/stream_register.sv:14] INFO: [Synth 8-6155] done synthesizing module 'axi_atop_filter' (15#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv:37] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized1' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b1 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized1' (15#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized2' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized2' (15#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized3' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized3' (15#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'counter' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/counter.sv:14] Parameter WIDTH bound to: 32'b00000000000000000000000000001000 Parameter STICKY_OVERFLOW bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'delta_counter__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] Parameter WIDTH bound to: 32'b00000000000000000000000000001000 Parameter STICKY_OVERFLOW bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'delta_counter__parameterized0' (15#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] INFO: [Synth 8-6155] done synthesizing module 'counter' (16#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/counter.sv:14] INFO: [Synth 8-6155] done synthesizing module 'axi_err_slv' (17#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_err_slv.sv:19] INFO: [Synth 8-6157] synthesizing module 'axi_mux' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_mux.sv:27] Parameter SlvAxiIDWidth bound to: 4 - type: integer Parameter NoSlvPorts bound to: 2 - type: integer Parameter MaxWTrans bound to: 1 - type: integer Parameter FallThrough bound to: 1'b0 Parameter SpillAw bound to: 1'b1 Parameter SpillW bound to: 1'b1 Parameter SpillB bound to: 1'b1 Parameter SpillAr bound to: 1'b1 Parameter SpillR bound to: 1'b1 Parameter MstIdxBits bound to: 32'b00000000000000000000000000000001 Parameter MstAxiIDWidth bound to: 32'b00000000000000000000000000000101 INFO: [Synth 8-6157] synthesizing module 'axi_id_prepend' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_id_prepend.sv:18] Parameter NoBus bound to: 1 - type: integer Parameter AxiIdWidthSlvPort bound to: 4 - type: integer Parameter AxiIdWidthMstPort bound to: 32'b00000000000000000000000000000101 Parameter PreIdWidth bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6155] done synthesizing module 'axi_id_prepend' (18#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_id_prepend.sv:18] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized1' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] Parameter NumIn bound to: 2 - type: integer Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] Parameter WIDTH bound to: 2 - type: integer Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized0' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized1' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized4' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 1 - type: integer Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized4' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized4' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized4' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized4' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized4' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized5' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized5' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized5' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized5' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized2' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] Parameter NumIn bound to: 2 - type: integer Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized2' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized6' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized6' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized6' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized6' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized7' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized7' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized7' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized7' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6155] done synthesizing module 'axi_mux' (19#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_mux.sv:27] INFO: [Synth 8-6155] done synthesizing module 'axi_xbar' (20#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv:18] INFO: [Synth 8-6155] done synthesizing module 'axi_xbar_intf' (21#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv:242] INFO: [Synth 8-6157] synthesizing module 'dmi_jtag' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv:19] Parameter IdcodeValue bound to: 1 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv:101] INFO: [Synth 8-6157] synthesizing module 'dmi_jtag_tap' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv:19] Parameter IrLength bound to: 32'b00000000000000000000000000000101 Parameter IdcodeValue bound to: 1 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv:186] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv:207] INFO: [Synth 8-6157] synthesizing module 'cluster_clock_inverter' [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv:54] INFO: [Synth 8-6157] synthesizing module 'tc_clk_inverter' [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv:55] INFO: [Synth 8-6155] done synthesizing module 'tc_clk_inverter' (22#1) [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv:55] INFO: [Synth 8-6155] done synthesizing module 'cluster_clock_inverter' (23#1) [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv:54] INFO: [Synth 8-6157] synthesizing module 'pulp_clock_mux2' [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv:66] INFO: [Synth 8-6157] synthesizing module 'tc_clk_mux2' [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv:64] INFO: [Synth 8-6155] done synthesizing module 'tc_clk_mux2' (24#1) [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv:64] INFO: [Synth 8-6155] done synthesizing module 'pulp_clock_mux2' (25#1) [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv:66] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv:260] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv:260] INFO: [Synth 8-6155] done synthesizing module 'dmi_jtag_tap' (26#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv:19] INFO: [Synth 8-6157] synthesizing module 'dmi_cdc' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_cdc.sv:19] INFO: [Synth 8-6157] synthesizing module 'cdc_2phase' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:19] INFO: [Synth 8-6157] synthesizing module 'cdc_2phase_src' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:68] INFO: [Synth 8-6155] done synthesizing module 'cdc_2phase_src' (27#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:68] INFO: [Synth 8-6157] synthesizing module 'cdc_2phase_dst' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:118] INFO: [Synth 8-6155] done synthesizing module 'cdc_2phase_dst' (28#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:118] INFO: [Synth 8-6155] done synthesizing module 'cdc_2phase' (29#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:19] INFO: [Synth 8-6157] synthesizing module 'cdc_2phase__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:19] INFO: [Synth 8-6157] synthesizing module 'cdc_2phase_src__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:68] INFO: [Synth 8-6155] done synthesizing module 'cdc_2phase_src__parameterized0' (29#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:68] INFO: [Synth 8-6157] synthesizing module 'cdc_2phase_dst__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:118] INFO: [Synth 8-6155] done synthesizing module 'cdc_2phase_dst__parameterized0' (29#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:118] INFO: [Synth 8-6155] done synthesizing module 'cdc_2phase__parameterized0' (29#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:19] INFO: [Synth 8-6155] done synthesizing module 'dmi_cdc' (30#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_cdc.sv:19] INFO: [Synth 8-6155] done synthesizing module 'dmi_jtag' (31#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv:19] INFO: [Synth 8-6157] synthesizing module 'dm_top' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_top.sv:20] Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter DmBaseAddress bound to: 32'b00000000000000000001000000000000 Parameter SelectableHarts bound to: 1'b1 Parameter ReadByteEnable bound to: 1'b1 INFO: [Synth 8-6157] synthesizing module 'dm_csrs' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv:18] Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 Parameter HartSelLen bound to: 32'b00000000000000000000000000000001 Parameter NrHartsAligned bound to: 32'b00000000000000000000000000000010 Parameter DataEnd bound to: 8'b00000101 Parameter ProgBufEnd bound to: 8'b00100111 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv:294] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv:360] INFO: [Synth 8-6157] synthesizing module 'fifo_v2__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ALM_EMPTY_TH bound to: 32'b00000000000000000000000000000001 Parameter ALM_FULL_TH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized5' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized5' (31#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6155] done synthesizing module 'fifo_v2__parameterized0' (31#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] INFO: [Synth 8-6155] done synthesizing module 'dm_csrs' (32#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv:18] INFO: [Synth 8-6157] synthesizing module 'dm_sba' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_sba.sv:18] Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter ReadByteEnable bound to: 1'b1 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_sba.sv:72] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_sba.sv:101] INFO: [Synth 8-6155] done synthesizing module 'dm_sba' (33#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_sba.sv:18] INFO: [Synth 8-6157] synthesizing module 'dm_mem' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:19] Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 Parameter DmBaseAddress bound to: 32'b00000000000000000001000000000000 Parameter DbgAddressBits bound to: 32'b00000000000000000000000000001100 Parameter HartSelLen bound to: 32'b00000000000000000000000000000001 Parameter NrHartsAligned bound to: 32'b00000000000000000000000000000010 Parameter MaxAar bound to: 32'b00000000000000000000000000000100 Parameter HasSndScratch bound to: 1'b1 Parameter LoadBaseAddr bound to: 5'b01010 Parameter DataBaseAddr bound to: 12'b001110000000 Parameter DataEndAddr bound to: 12'b001110000111 Parameter ProgBufBaseAddr bound to: 12'b001101100000 Parameter ProgBufEndAddr bound to: 12'b001101111111 Parameter AbstractCmdBaseAddr bound to: 12'b001100111000 Parameter AbstractCmdEndAddr bound to: 12'b001101011111 Parameter WhereToAddr bound to: 12'b001100000000 Parameter FlagsBaseAddr bound to: 12'b010000000000 Parameter FlagsEndAddr bound to: 12'b011111111111 Parameter HaltedAddr bound to: 12'b000100000000 Parameter GoingAddr bound to: 12'b000100000100 Parameter ResumingAddr bound to: 12'b000100001000 Parameter ExceptionAddr bound to: 12'b000100001100 INFO: [Synth 8-6157] synthesizing module 'debug_rom' [/home/darshak/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom.sv:17] Parameter RomSize bound to: 32'b00000000000000000000000000010011 INFO: [Synth 8-6155] done synthesizing module 'debug_rom' (34#1) [/home/darshak/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom.sv:17] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:144] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:144] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:242] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:272] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:351] INFO: [Synth 8-6155] done synthesizing module 'dm_mem' (35#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:19] INFO: [Synth 8-6155] done synthesizing module 'dm_top' (36#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_top.sv:20] INFO: [Synth 8-6157] synthesizing module 'axi2mem' [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:20] Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_ADDR_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter LOG_NR_BYTES bound to: 3 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:192] INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:234] INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:122] INFO: [Synth 8-6155] done synthesizing module 'axi2mem' (37#1) [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:20] INFO: [Synth 8-6157] synthesizing module 'axi_adapter' [/home/darshak/cva6/core/cache_subsystem/axi_adapter.sv:19] Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter CRITICAL_WORD_FIRST bound to: 1'b0 Parameter CACHELINE_BYTE_OFFSET bound to: 32'b00000000000000000000000000001000 Parameter AXI_ADDR_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_ID_WIDTH bound to: 32'b00000000000000000000000000000100 Parameter BURST_SIZE bound to: 0 - type: integer Parameter ADDR_INDEX bound to: 1 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/axi_adapter.sv:430] WARNING: [Synth 8-2898] ignoring assertion [/home/darshak/cva6/core/cache_subsystem/axi_adapter.sv:169] WARNING: [Synth 8-2898] ignoring assertion [/home/darshak/cva6/core/cache_subsystem/axi_adapter.sv:197] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/axi_adapter.sv:430] INFO: [Synth 8-6155] done synthesizing module 'axi_adapter' (38#1) [/home/darshak/cva6/core/cache_subsystem/axi_adapter.sv:19] INFO: [Synth 8-6157] synthesizing module 'ariane' [/home/darshak/cva6/corev_apu/src/ariane.sv:16] Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter AxiAddrWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6157] synthesizing module 'cvxif_example_coprocessor' [/home/darshak/cva6/core/cvxif_example/cvxif_example_coprocessor.sv:12] INFO: [Synth 8-6157] synthesizing module 'instr_decoder' [/home/darshak/cva6/core/cvxif_example/instr_decoder.sv:10] Parameter NbInstr bound to: 32'sb00000000000000000000000000000010 Parameter CoproInstr bound to: 140'b00000000000000000000000000101011000000000000000000000000011111111000000000000000000000000000000101101100000000000000000000000001111111110000 INFO: [Synth 8-6155] done synthesizing module 'instr_decoder' (39#1) [/home/darshak/cva6/core/cvxif_example/instr_decoder.sv:10] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized6' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b1 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter DEPTH bound to: 32'b00000000000000000000000000001000 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000011 Parameter FifoDepth bound to: 32'b00000000000000000000000000001000 INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized6' (39#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'counter__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/counter.sv:14] Parameter WIDTH bound to: 32'b00000000000000000000000000000100 Parameter STICKY_OVERFLOW bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'delta_counter__parameterized1' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] Parameter WIDTH bound to: 32'b00000000000000000000000000000100 Parameter STICKY_OVERFLOW bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'delta_counter__parameterized1' (39#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] INFO: [Synth 8-6155] done synthesizing module 'counter__parameterized0' (39#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/counter.sv:14] INFO: [Synth 8-6155] done synthesizing module 'cvxif_example_coprocessor' (40#1) [/home/darshak/cva6/core/cvxif_example/cvxif_example_coprocessor.sv:12] INFO: [Synth 8-6157] synthesizing module 'cva6' [/home/darshak/cva6/core/cva6.sv:16] Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter AxiAddrWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter NumPorts bound to: 3 - type: integer INFO: [Synth 8-6157] synthesizing module 'perf_counters' [/home/darshak/cva6/core/perf_counters.sv:16] Parameter NumPorts bound to: 3 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/perf_counters.sv:119] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/perf_counters.sv:143] INFO: [Synth 8-6155] done synthesizing module 'perf_counters' (41#1) [/home/darshak/cva6/core/perf_counters.sv:16] INFO: [Synth 8-6157] synthesizing module 'wt_cache_subsystem' [/home/darshak/cva6/core/cache_subsystem/wt_cache_subsystem.sv:22] Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter NumPorts bound to: 3 - type: integer Parameter AxiAddrWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6157] synthesizing module 'cva6_icache' [/home/darshak/cva6/core/cache_subsystem/cva6_icache.sv:28] Parameter RdTxId bound to: 2'b00 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'sram' [/home/darshak/cva6/common/local/util/sram.sv:21] Parameter DATA_WIDTH bound to: 45 - type: integer Parameter USER_WIDTH bound to: 1 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer Parameter SIM_INIT bound to: none - type: string Parameter OUT_REGS bound to: 0 - type: integer Parameter DATA_WIDTH_ALIGNED bound to: 64 - type: integer Parameter USER_WIDTH_ALIGNED bound to: 64 - type: integer Parameter BE_WIDTH_ALIGNED bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'tc_sram_wrapper' [/home/darshak/cva6/common/local/util/tc_sram_fpga_wrapper.sv:10] Parameter NumWords bound to: 256 - type: integer Parameter DataWidth bound to: 32'b00000000000000000000000001000000 Parameter ByteWidth bound to: 8 - type: integer Parameter NumPorts bound to: 1 - type: integer Parameter Latency bound to: 1 - type: integer Parameter SimInit bound to: none - type: string Parameter PrintSimCfg bound to: 1'b0 Parameter AddrWidth bound to: 32'b00000000000000000000000000001000 Parameter BeWidth bound to: 32'b00000000000000000000000000001000 INFO: [Synth 8-6157] synthesizing module 'SyncSpRamBeNx64' [/home/darshak/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv:28] Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter DATA_DEPTH bound to: 256 - type: integer Parameter OUT_REGS bound to: 0 - type: integer Parameter SIM_INIT bound to: 1 - type: integer Parameter DATA_BYTES bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'SyncSpRamBeNx64' (42#1) [/home/darshak/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv:28] INFO: [Synth 8-6155] done synthesizing module 'tc_sram_wrapper' (43#1) [/home/darshak/cva6/common/local/util/tc_sram_fpga_wrapper.sv:10] INFO: [Synth 8-6155] done synthesizing module 'sram' (44#1) [/home/darshak/cva6/common/local/util/sram.sv:21] INFO: [Synth 8-6157] synthesizing module 'sram__parameterized0' [/home/darshak/cva6/common/local/util/sram.sv:21] Parameter DATA_WIDTH bound to: 128 - type: integer Parameter USER_WIDTH bound to: 128 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer Parameter SIM_INIT bound to: none - type: string Parameter OUT_REGS bound to: 0 - type: integer Parameter DATA_WIDTH_ALIGNED bound to: 128 - type: integer Parameter USER_WIDTH_ALIGNED bound to: 128 - type: integer Parameter BE_WIDTH_ALIGNED bound to: 16 - type: integer INFO: [Synth 8-6155] done synthesizing module 'sram__parameterized0' (44#1) [/home/darshak/cva6/common/local/util/sram.sv:21] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/cva6_icache.sv:182] INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized1' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] Parameter WIDTH bound to: 32'b00000000000000000000000000000100 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized1' (44#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6157] synthesizing module 'lfsr' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv:22] Parameter LfsrWidth bound to: 32'b00000000000000000000000000001000 Parameter OutWidth bound to: 32'b00000000000000000000000000000010 Parameter RstVal bound to: 8'b11111111 Parameter CipherLayers bound to: 32'b00000000000000000000000000000000 Parameter CipherReg bound to: 1'b1 Parameter Masks bound to: 3904'b0000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000001111000000000000000000000000000000000000000000000000000000000001110010000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001111101000000000000000000000000000000000000000000000000000000001111111010000000000000000000000000000000000000000000000000000001111111100000000000000000000000000000000000000000000000000000001100100101100000000000000000000000000000000000000000000000000001101100011110000000000000000000000000000000000000000000000000001001010010110000000000000000000000000000000000000000000000000001001001001011000000000000000000000000000000000000000000000000001000011010101110000000000000000000000000000000000000000000000001000011001111001000000000000000000000000000000000000000000000001000000110000111000000000000000000000000000000000000000000000001000000110110011010000000000000000000000000000000000000000000001000000001111111110000000000000000000000000000000000000000000001000000001111011100000000000000000000000000000000000000000000001000000000100101100100000000000000000000000000000000000000000001000000000011010101000000000000000000000000000000000000000000001000000000001001011001000000000000000000000000000000000000000001000000000001011100001110000000000000000000000000000000000000001000000000000010011110011000000000000000000000000000000000000001000000000000001110010110100000000000000000000000000000000000001000000000000000110101011100000000000000000000000000000000000001000000000000000100111100011000000000000000000000000000000000001000000000000000001011000001100000000000000000000000000000000001000000000000000001100100100100000000000000000000000000000000001000000000000000000010110110110000000000000000000000000000000001000000000000000000011101010011000000000000000000000000000000001000000000000000000000111101000110000000000000000000000000000001000000000000000000000101010111111000000000000000000000000000001000000000000000000000010000100001000000000000000000000000000001000000000000000000000010010001111100000000000000000000000000001000000000000000000000000011101001110000000000000000000000000001000000000000000000000000010101110100100000000000000000000000001000000000000000000000000001000011010100000000000000000000000001000000000000000000000000001001000010011000000000000000000000001000000000000000000000000000001110111111000000000000000000000001000000000000000000000000000010010001110110000000000000000000001000000000000000000000000000000100001110111000000000000000000001000000000000000000000000000000100001000110100000000000000000001000000000000000000000000000000001010111010010000000000000000001000000000000000000000000000000000111010011111000000000000000001000000000000000000000000000000000010001010011000000000000000001000000000000000000000000000000000011001000111100000000000000001000000000000000000000000000000000000100100001110000000000000001000000000000000000000000000000000000011111011001100000000000001000000000000000000000000000000000000001101011111010000000000001000000000000000000000000000000000000001011010100101000000000001000000000000000000000000000000000000000010110100101100000000001000000000000000000000000000000000000000010000101011110000000001000000000000000000000000000000000000000000110111011110000000001000000000000000000000000000000000000000000110000001101000000001000000000000000000000000000000000000000000001011011001010000001000000000000000000000000000000000000000000001000000101101000001000000000000000000000000000000000000000000000011001101010100001000000000000000000000000000000000000000000000100100110000010001000000000000000000000000000000000000000000000000111011110110001000000000000000000000000000000000000000000000000100110110001101000000000000000000000000000000000000000000000000001111110011011000000000000000000000000000000000000000000000000001100111100010 Parameter Sbox4 bound to: 64'b0010000101110100100011111110001111011010000010011011011001011100 Parameter Perm bound to: 384'b111111101111011111001111111110101110011110001110111101101101011101001101111100101100011100001100111011101011011011001011111010101010011010001010111001101001011001001001111000101000011000001000110111100111010111000111110110100110010110000110110101100101010101000101110100100100010100000100110011100011010011000011110010100010010010000010110001100001010001000001110000100000010000000000 INFO: [Synth 8-6155] done synthesizing module 'lfsr' (45#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv:22] INFO: [Synth 8-6155] done synthesizing module 'cva6_icache' (46#1) [/home/darshak/cva6/core/cache_subsystem/cva6_icache.sv:28] INFO: [Synth 8-6157] synthesizing module 'wt_dcache' [/home/darshak/cva6/core/cache_subsystem/wt_dcache.sv:16] INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter NumPorts bound to: 32'b00000000000000000000000000000011 Parameter RdAmoTxId bound to: 2'b01 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter RdTxId bound to: 2'b01 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_dcache_ctrl.sv:114] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/core/cache_subsystem/wt_dcache_ctrl.sv:114] INFO: [Synth 8-6155] done synthesizing module 'wt_dcache_ctrl' (47#1) [/home/darshak/cva6/core/cache_subsystem/wt_dcache_ctrl.sv:16] Parameter AxiCompliant bound to: 1'b1 Parameter AmoTxId bound to: 2'b01 Parameter NumPorts bound to: 32'b00000000000000000000000000000011 Parameter AxiDataWidth bound to: 32'sb00000000000000000000000001000000 Parameter WIDTH bound to: 32'b00000000000000000000000000000011 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized2' (47#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] Parameter WIDTH bound to: 32'b00000000000000000000000000001000 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000011 INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized3' (47#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] Parameter LfsrWidth bound to: 32'b00000000000000000000000000001000 Parameter OutWidth bound to: 32'b00000000000000000000000000000011 Parameter RstVal bound to: 8'b11111111 Parameter CipherLayers bound to: 32'b00000000000000000000000000000000 Parameter CipherReg bound to: 1'b1 Parameter Masks bound to: 3904'b0000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000001111000000000000000000000000000000000000000000000000000000000001110010000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001111101000000000000000000000000000000000000000000000000000000001111111010000000000000000000000000000000000000000000000000000001111111100000000000000000000000000000000000000000000000000000001100100101100000000000000000000000000000000000000000000000000001101100011110000000000000000000000000000000000000000000000000001001010010110000000000000000000000000000000000000000000000000001001001001011000000000000000000000000000000000000000000000000001000011010101110000000000000000000000000000000000000000000000001000011001111001000000000000000000000000000000000000000000000001000000110000111000000000000000000000000000000000000000000000001000000110110011010000000000000000000000000000000000000000000001000000001111111110000000000000000000000000000000000000000000001000000001111011100000000000000000000000000000000000000000000001000000000100101100100000000000000000000000000000000000000000001000000000011010101000000000000000000000000000000000000000000001000000000001001011001000000000000000000000000000000000000000001000000000001011100001110000000000000000000000000000000000000001000000000000010011110011000000000000000000000000000000000000001000000000000001110010110100000000000000000000000000000000000001000000000000000110101011100000000000000000000000000000000000001000000000000000100111100011000000000000000000000000000000000001000000000000000001011000001100000000000000000000000000000000001000000000000000001100100100100000000000000000000000000000000001000000000000000000010110110110000000000000000000000000000000001000000000000000000011101010011000000000000000000000000000000001000000000000000000000111101000110000000000000000000000000000001000000000000000000000101010111111000000000000000000000000000001000000000000000000000010000100001000000000000000000000000000001000000000000000000000010010001111100000000000000000000000000001000000000000000000000000011101001110000000000000000000000000001000000000000000000000000010101110100100000000000000000000000001000000000000000000000000001000011010100000000000000000000000001000000000000000000000000001001000010011000000000000000000000001000000000000000000000000000001110111111000000000000000000000001000000000000000000000000000010010001110110000000000000000000001000000000000000000000000000000100001110111000000000000000000001000000000000000000000000000000100001000110100000000000000000001000000000000000000000000000000001010111010010000000000000000001000000000000000000000000000000000111010011111000000000000000001000000000000000000000000000000000010001010011000000000000000001000000000000000000000000000000000011001000111100000000000000001000000000000000000000000000000000000100100001110000000000000001000000000000000000000000000000000000011111011001100000000000001000000000000000000000000000000000000001101011111010000000000001000000000000000000000000000000000000001011010100101000000000001000000000000000000000000000000000000000010110100101100000000001000000000000000000000000000000000000000010000101011110000000001000000000000000000000000000000000000000000110111011110000000001000000000000000000000000000000000000000000110000001101000000001000000000000000000000000000000000000000000001011011001010000001000000000000000000000000000000000000000000001000000101101000001000000000000000000000000000000000000000000000011001101010100001000000000000000000000000000000000000000000000100100110000010001000000000000000000000000000000000000000000000000111011110110001000000000000000000000000000000000000000000000000100110110001101000000000000000000000000000000000000000000000000001111110011011000000000000000000000000000000000000000000000000001100111100010 Parameter Sbox4 bound to: 64'b0010000101110100100011111110001111011010000010011011011001011100 Parameter Perm bound to: 384'b111111101111011111001111111110101110011110001110111101101101011101001101111100101100011100001100111011101011011011001011111010101010011010001010111001101001011001001001111000101000011000001000110111100111010111000111110110100110010110000110110101100101010101000101110100100100010100000100110011100011010011000011110010100010010010000010110001100001010001000001110000100000010000000000 INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized0' (47#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv:22] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/wt_cache_pkg.sv:398] Parameter Seed bound to: 32'b00000000000000000000000000000011 Parameter MaxExp bound to: 32'b00000000000000000000000000010000 Parameter WIDTH bound to: 32'b00000000000000000000000000010000 WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/exp_backoff.sv:59] INFO: [Synth 8-6155] done synthesizing module 'exp_backoff' (48#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/exp_backoff.sv:23] INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_dcache_missunit.sv:297] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_dcache_missunit.sv:397] Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000001000 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000011 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/wt_cache_pkg.sv:364] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/wt_cache_pkg.sv:334] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/wt_cache_pkg.sv:304] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000000010 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 Parameter NumIn bound to: 32'b00000000000000000000000000000100 Parameter DataWidth bound to: 32'b00000000000000000000000000000001 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b0 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000010 Parameter NumIn bound to: 32'b00000000000000000000000000001000 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b0 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000011 Parameter NumIn bound to: 32'b00000000000000000000000000001000 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b0 Parameter LockIn bound to: 1'b0 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000011 Parameter AxiCompliant bound to: 1'b1 Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter NumPorts bound to: 32'b00000000000000000000000000000011 Parameter AXI_OFFSET_WIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 512 - type: integer Parameter USER_WIDTH bound to: 512 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer Parameter SIM_INIT bound to: none - type: string Parameter OUT_REGS bound to: 0 - type: integer Parameter DATA_WIDTH_ALIGNED bound to: 512 - type: integer Parameter USER_WIDTH_ALIGNED bound to: 512 - type: integer Parameter BE_WIDTH_ALIGNED bound to: 64 - type: integer Parameter NumIn bound to: 32'b00000000000000000000000000000011 Parameter DataWidth bound to: 32'b00000000000000000000000000000001 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b0 Parameter LockIn bound to: 1'b0 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000010 Parameter ReqFifoDepth bound to: 32'b00000000000000000000000000000010 Parameter MetaFifoDepth bound to: 32'b00000000000000000000000000000100 Parameter AxiAddrWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter AxiNumWords bound to: 2 - type: integer Parameter NumIn bound to: 32'b00000000000000000000000000000010 Parameter DataWidth bound to: 32'b00000000000000000000000000000001 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000001 WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv:149] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv:151] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv:184] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv:193] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv:210] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv:220] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000000010 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 Parameter FALL_THROUGH bound to: 1'b1 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000000101 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 Parameter AxiUserWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiNumWords bound to: 2 - type: integer Parameter AxiAddrWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter AddrIndex bound to: 1 - type: integer Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter DEPTH bound to: 2 - type: integer Parameter NR_ENTRIES bound to: 32 - type: integer Parameter OFFSET bound to: 1 - type: integer Parameter NR_ROWS bound to: 16 - type: integer Parameter ROW_ADDR_BITS bound to: 1 - type: integer Parameter ROW_INDEX_BITS bound to: 1 - type: integer Parameter PREDICTION_BITS bound to: 6 - type: integer Parameter ANTIALIAS_BITS bound to: 8 - type: integer Parameter BRAM_WORD_BITS bound to: 65 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/btb.sv:54] Parameter NR_ENTRIES bound to: 128 - type: integer Parameter OFFSET bound to: 1 - type: integer Parameter NR_ROWS bound to: 64 - type: integer Parameter ROW_ADDR_BITS bound to: 1 - type: integer Parameter ROW_INDEX_BITS bound to: 1 - type: integer Parameter PREDICTION_BITS bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/bht.sv:43] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/frontend/frontend.sv:180] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/frontend/frontend.sv:180] Parameter WIDTH bound to: 32'b00000000000000000000000000000010 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000001 Parameter INPUT_WIDTH bound to: 32'b00000000000000000000000000000010 Parameter PopcountWidth bound to: 32'b00000000000000000000000000000010 Parameter PaddedWidth bound to: 32'b00000000000000000000000000000010 WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/frontend/instr_queue.sv:280] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/frontend/instr_queue.sv:280] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/instr_queue.sv:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/instr_queue.sv:392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/instr_queue.sv:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/instr_queue.sv:394] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/instr_queue.sv:395] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/compressed_decoder.sv:41] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/compressed_decoder.sv:44] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/compressed_decoder.sv:106] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/compressed_decoder.sv:149] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/compressed_decoder.sv:163] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/compressed_decoder.sv:220] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/core/compressed_decoder.sv:220] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:99] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:488] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:513] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:559] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:574] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:600] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:676] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:694] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:729] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:745] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:768] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:791] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:822] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:830] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/core/decoder.sv:830] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:841] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:846] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:853] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:874] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:922] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:977] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/core/decoder.sv:977] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:988] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:993] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:1000] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:1025] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:1044] Parameter NR_ENTRIES bound to: 32'b00000000000000000000000000001000 Parameter NR_WB_PORTS bound to: 32'b00000000000000000000000000000101 Parameter NR_COMMIT_PORTS bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:619] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:590] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:607] Parameter NR_ENTRIES bound to: 32'b00000000000000000000000000001000 Parameter NR_WB_PORTS bound to: 32'b00000000000000000000000000000101 Parameter NR_COMMIT_PORTS bound to: 32'b00000000000000000000000000000010 Parameter BITS_ENTRIES bound to: 32'b00000000000000000000000000000011 Parameter NumIn bound to: 32'b00000000000000000000000000001001 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b1 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b0 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:590] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:607] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:590] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:607] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:590] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:607] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:590] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:607] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:590] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:607] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Common 17-14] Message 'Synth 8-294' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter NumIn bound to: 32'b00000000000000000000000000001101 Parameter DataWidth bound to: 32'b00000000000000000000000001000000 Parameter ExtPrio bound to: 1'b1 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b0 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000100 Parameter NR_COMMIT_PORTS bound to: 32'b00000000000000000000000000000010 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter NR_READ_PORTS bound to: 32'b00000000000000000000000000000010 Parameter NR_WRITE_PORTS bound to: 32'b00000000000000000000000000000010 Parameter ZERO_REG_ZERO bound to: 1'b1 Parameter ADDR_WIDTH bound to: 5 - type: integer Parameter NUM_WORDS bound to: 32 - type: integer Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter NR_READ_PORTS bound to: 32'b00000000000000000000000000000011 Parameter NR_WRITE_PORTS bound to: 32'b00000000000000000000000000000010 Parameter ZERO_REG_ZERO bound to: 1'b0 Parameter ADDR_WIDTH bound to: 5 - type: integer Parameter NUM_WORDS bound to: 32 - type: integer WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/issue_read_operands.sv:222] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/issue_read_operands.sv:237] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/issue_read_operands.sv:242] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/issue_read_operands.sv:496] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/issue_read_operands.sv:497] Parameter ASID_WIDTH bound to: 32'b00000000000000000000000000010000 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/core/fpu_wrap.sv:428] Parameter Features[Width] bound to: 64 - type: integer Parameter Features[EnableVectors] bound to: 1'b0 Parameter Features[EnableNanBox] bound to: 1'b1 Parameter Features[FpFmtMask] bound to: 5'b11000 Parameter Features[IntFmtMask] bound to: 4'b0011 Parameter Implementation[PipeRegs][0][0] bound to: 2 - type: integer Parameter Implementation[PipeRegs][0][1] bound to: 3 - type: integer Parameter Implementation[PipeRegs][0][2] bound to: 1 - type: integer Parameter Implementation[PipeRegs][0][3] bound to: 1 - type: integer Parameter Implementation[PipeRegs][0][4] bound to: 1 - type: integer Parameter Implementation[PipeRegs][1][0] bound to: 2 - type: integer Parameter Implementation[PipeRegs][1][1] bound to: 2 - type: integer Parameter Implementation[PipeRegs][1][2] bound to: 2 - type: integer Parameter Implementation[PipeRegs][1][3] bound to: 2 - type: integer Parameter Implementation[PipeRegs][1][4] bound to: 2 - type: integer Parameter Implementation[PipeRegs][2][0] bound to: 1 - type: integer Parameter Implementation[PipeRegs][2][1] bound to: 1 - type: integer Parameter Implementation[PipeRegs][2][2] bound to: 1 - type: integer Parameter Implementation[PipeRegs][2][3] bound to: 1 - type: integer Parameter Implementation[PipeRegs][2][4] bound to: 1 - type: integer Parameter Implementation[PipeRegs][3][0] bound to: 2 - type: integer Parameter Implementation[PipeRegs][3][1] bound to: 2 - type: integer Parameter Implementation[PipeRegs][3][2] bound to: 2 - type: integer Parameter Implementation[PipeRegs][3][3] bound to: 2 - type: integer Parameter Implementation[PipeRegs][3][4] bound to: 2 - type: integer Parameter Implementation[UnitTypes][0][0] bound to: 2'b01 Parameter Implementation[UnitTypes][0][1] bound to: 2'b01 Parameter Implementation[UnitTypes][0][2] bound to: 2'b01 Parameter Implementation[UnitTypes][0][3] bound to: 2'b01 Parameter Implementation[UnitTypes][0][4] bound to: 2'b01 Parameter Implementation[UnitTypes][1][0] bound to: 2'b10 Parameter Implementation[UnitTypes][1][1] bound to: 2'b10 Parameter Implementation[UnitTypes][1][2] bound to: 2'b10 Parameter Implementation[UnitTypes][1][3] bound to: 2'b10 Parameter Implementation[UnitTypes][1][4] bound to: 2'b10 Parameter Implementation[UnitTypes][2][0] bound to: 2'b01 Parameter Implementation[UnitTypes][2][1] bound to: 2'b01 Parameter Implementation[UnitTypes][2][2] bound to: 2'b01 Parameter Implementation[UnitTypes][2][3] bound to: 2'b01 Parameter Implementation[UnitTypes][2][4] bound to: 2'b01 Parameter Implementation[UnitTypes][3][0] bound to: 2'b10 Parameter Implementation[UnitTypes][3][1] bound to: 2'b10 Parameter Implementation[UnitTypes][3][2] bound to: 2'b10 Parameter Implementation[UnitTypes][3][3] bound to: 2'b10 Parameter Implementation[UnitTypes][3][4] bound to: 2'b10 Parameter Implementation[PipeConfig] bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter EnableSIMDMask bound to: 32'b00000000000000000000000000000000 Parameter NumLanes bound to: 32'b00000000000000000000000000000001 Parameter WIDTH bound to: 64 - type: integer Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000011 Parameter NUM_OPGROUPS bound to: 32'b00000000000000000000000000000100 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter OpGroup bound to: 2'b00 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter FpFmtMask bound to: 5'b11000 Parameter IntFmtMask bound to: 4'b0011 Parameter FmtPipeRegs bound to: 160'b0000000000000000000000000000001000000000000000000000000000000011000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001 Parameter FmtUnitTypes bound to: 10'b0101010101 Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000011 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter OpGroup bound to: 2'b00 Parameter FpFormat bound to: 3'b000 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter NumPipeRegs bound to: 2 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000011 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter FP_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SIMD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter CLASS_VEC_BITS bound to: 32'b00000000000000000000000000001000 Parameter FpFormat bound to: 3'b000 Parameter NumPipeRegs bound to: 2 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter EXP_BITS bound to: 8 - type: integer Parameter MAN_BITS bound to: 23 - type: integer Parameter BIAS bound to: 32'b00000000000000000000000001111111 Parameter PRECISION_BITS bound to: 32'b00000000000000000000000000011000 Parameter LOWER_SUM_WIDTH bound to: 32'b00000000000000000000000000110011 Parameter LZC_RESULT_WIDTH bound to: 32'b00000000000000000000000000000110 Parameter EXP_WIDTH bound to: 32'b00000000000000000000000000001010 Parameter SHIFT_AMOUNT_WIDTH bound to: 32'b00000000000000000000000000000111 Parameter NUM_INP_REGS bound to: 1 - type: integer Parameter NUM_MID_REGS bound to: 1 - type: integer Parameter NUM_OUT_REGS bound to: 0 - type: integer Parameter FpFormat bound to: 3'b000 Parameter NumOperands bound to: 32'b00000000000000000000000000000011 Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter EXP_BITS bound to: 8 - type: integer Parameter MAN_BITS bound to: 23 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000110011 Parameter MODE bound to: 1'b1 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000110 Parameter AbsWidth bound to: 32'b00000000000000000000000000011111 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv:48] Parameter OpGroup bound to: 2'b00 Parameter FpFormat bound to: 3'b001 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter NumPipeRegs bound to: 3 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000011 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter FP_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter SIMD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter CLASS_VEC_BITS bound to: 32'b00000000000000000000000000001000 Parameter FpFormat bound to: 3'b001 Parameter NumPipeRegs bound to: 3 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter EXP_BITS bound to: 11 - type: integer Parameter MAN_BITS bound to: 52 - type: integer Parameter BIAS bound to: 32'b00000000000000000000001111111111 Parameter PRECISION_BITS bound to: 32'b00000000000000000000000000110101 Parameter LOWER_SUM_WIDTH bound to: 32'b00000000000000000000000001101101 Parameter LZC_RESULT_WIDTH bound to: 32'b00000000000000000000000000000111 Parameter EXP_WIDTH bound to: 32'b00000000000000000000000000001101 Parameter SHIFT_AMOUNT_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter NUM_INP_REGS bound to: 1 - type: integer Parameter NUM_MID_REGS bound to: 1 - type: integer Parameter NUM_OUT_REGS bound to: 1 - type: integer Parameter FpFormat bound to: 3'b001 Parameter NumOperands bound to: 32'b00000000000000000000000000000011 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter EXP_BITS bound to: 11 - type: integer Parameter MAN_BITS bound to: 52 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000001101101 Parameter MODE bound to: 1'b1 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000111 Parameter AbsWidth bound to: 32'b00000000000000000000000000111111 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv:48] Parameter NumIn bound to: 32'b00000000000000000000000000000101 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b0 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000011 Parameter WIDTH bound to: 32'b00000000000000000000000000000101 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000011 Parameter OpGroup bound to: 2'b01 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter FpFmtMask bound to: 5'b11000 Parameter IntFmtMask bound to: 4'b0011 Parameter FmtPipeRegs bound to: 160'b0000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010 Parameter FmtUnitTypes bound to: 10'b1010101010 Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000010 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter OpGroup bound to: 2'b01 Parameter Width bound to: 64 - type: integer Parameter FpFmtConfig bound to: 5'b11000 Parameter IntFmtConfig bound to: 4'b0011 Parameter EnableVectors bound to: 1'b0 Parameter NumPipeRegs bound to: 2 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000010 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_SIMD_LANES bound to: 32'b00000000000000000000000000000001 Parameter MAX_FP_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter MAX_INT_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000010 Parameter NUM_INT_FORMATS bound to: 32'b00000000000000000000000000000100 Parameter FMT_BITS bound to: 32'b00000000000000000000000000000011 Parameter AUX_BITS bound to: 32'b00000000000000000000000000000101 Parameter FpFmtConfig bound to: 5'b11000 Parameter NumPipeRegs bound to: 2 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_INP_REGS bound to: 1 - type: integer Parameter NUM_OUT_REGS bound to: 1 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000110101 Parameter MODE bound to: 1'b1 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000110 Parameter WIDTH bound to: 58 - type: integer Parameter OpGroup bound to: 2'b10 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter FpFmtMask bound to: 5'b11000 Parameter IntFmtMask bound to: 4'b0011 Parameter FmtPipeRegs bound to: 160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001 Parameter FmtUnitTypes bound to: 10'b0101010101 Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000010 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter OpGroup bound to: 2'b10 Parameter FpFormat bound to: 3'b000 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter NumPipeRegs bound to: 1 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000010 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter FP_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SIMD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter CLASS_VEC_BITS bound to: 32'b00000000000000000000000000001000 Parameter FpFormat bound to: 3'b000 Parameter NumPipeRegs bound to: 1 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter EXP_BITS bound to: 8 - type: integer Parameter MAN_BITS bound to: 23 - type: integer Parameter NUM_INP_REGS bound to: 1 - type: integer Parameter NUM_OUT_REGS bound to: 0 - type: integer Parameter FpFormat bound to: 3'b000 Parameter NumOperands bound to: 32'b00000000000000000000000000000010 Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter EXP_BITS bound to: 8 - type: integer Parameter MAN_BITS bound to: 23 - type: integer Parameter OpGroup bound to: 2'b10 Parameter FpFormat bound to: 3'b001 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter NumPipeRegs bound to: 1 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000010 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter FP_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter SIMD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter CLASS_VEC_BITS bound to: 32'b00000000000000000000000000001000 Parameter FpFormat bound to: 3'b001 Parameter NumPipeRegs bound to: 1 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter EXP_BITS bound to: 11 - type: integer Parameter MAN_BITS bound to: 52 - type: integer Parameter NUM_INP_REGS bound to: 1 - type: integer Parameter NUM_OUT_REGS bound to: 0 - type: integer Parameter FpFormat bound to: 3'b001 Parameter NumOperands bound to: 32'b00000000000000000000000000000010 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter EXP_BITS bound to: 11 - type: integer Parameter MAN_BITS bound to: 52 - type: integer Parameter OpGroup bound to: 2'b11 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter FpFmtMask bound to: 5'b11000 Parameter IntFmtMask bound to: 4'b0011 Parameter FmtPipeRegs bound to: 160'b0000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010 Parameter FmtUnitTypes bound to: 10'b1010101010 Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000011 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter OpGroup bound to: 2'b11 Parameter Width bound to: 64 - type: integer Parameter FpFmtConfig bound to: 5'b11000 Parameter IntFmtConfig bound to: 4'b0011 Parameter EnableVectors bound to: 1'b0 Parameter NumPipeRegs bound to: 2 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000011 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_SIMD_LANES bound to: 32'b00000000000000000000000000000001 Parameter MAX_FP_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter MAX_INT_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000010 Parameter NUM_INT_FORMATS bound to: 32'b00000000000000000000000000000100 Parameter FMT_BITS bound to: 32'b00000000000000000000000000000011 Parameter AUX_BITS bound to: 32'b00000000000000000000000000000101 Parameter FpFmtConfig bound to: 5'b11000 Parameter IntFmtConfig bound to: 4'b0011 Parameter NumPipeRegs bound to: 2 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_INT_FORMATS bound to: 32'b00000000000000000000000000000100 Parameter MAX_INT_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter SUPER_FORMAT[exp_bits] bound to: 11 - type: integer Parameter SUPER_FORMAT[man_bits] bound to: 52 - type: integer Parameter SUPER_EXP_BITS bound to: 11 - type: integer Parameter SUPER_MAN_BITS bound to: 52 - type: integer Parameter SUPER_BIAS bound to: 32'b00000000000000000000001111111111 Parameter INT_MAN_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter LZC_RESULT_WIDTH bound to: 32'b00000000000000000000000000000110 Parameter INT_EXP_WIDTH bound to: 32'b00000000000000000000000000001100 Parameter NUM_INP_REGS bound to: 1 - type: integer Parameter NUM_MID_REGS bound to: 1 - type: integer Parameter NUM_OUT_REGS bound to: 0 - type: integer Parameter NUM_FP_STICKY bound to: 75 - type: integer Parameter NUM_INT_STICKY bound to: 64 - type: integer Parameter FpFormat bound to: 3'b000 Parameter NumOperands bound to: 32'b00000000000000000000000000000001 Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter EXP_BITS bound to: 8 - type: integer Parameter MAN_BITS bound to: 23 - type: integer Parameter FpFormat bound to: 3'b001 Parameter NumOperands bound to: 32'b00000000000000000000000000000001 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter EXP_BITS bound to: 11 - type: integer Parameter MAN_BITS bound to: 52 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter MODE bound to: 1'b1 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000110 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv:89] Parameter AbsWidth bound to: 32'b00000000000000000000000001000000 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv:48] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv:89] Parameter NumIn bound to: 32'b00000000000000000000000000000100 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b0 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000010 Parameter INPUT_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter PopcountWidth bound to: 32'b00000000000000000000000000000111 Parameter PaddedWidth bound to: 32'b00000000000000000000000001000000 Parameter INPUT_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter PopcountWidth bound to: 32'b00000000000000000000000000000110 Parameter PaddedWidth bound to: 32'b00000000000000000000000000100000 Parameter INPUT_WIDTH bound to: 32'b00000000000000000000000000010000 Parameter PopcountWidth bound to: 32'b00000000000000000000000000000101 Parameter PaddedWidth bound to: 32'b00000000000000000000000000010000 Parameter INPUT_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter PopcountWidth bound to: 32'b00000000000000000000000000000100 Parameter PaddedWidth bound to: 32'b00000000000000000000000000001000 Parameter INPUT_WIDTH bound to: 32'b00000000000000000000000000000100 Parameter PopcountWidth bound to: 32'b00000000000000000000000000000011 Parameter PaddedWidth bound to: 32'b00000000000000000000000000000100 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter MODE bound to: 1'b1 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000110 Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter MODE bound to: 1'b1 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000101 WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/branch_unit.sv:90] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/ex_stage.sv:216] Parameter WIDTH bound to: 64 - type: integer Parameter ASID_WIDTH bound to: 32'b00000000000000000000000000010000 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter INSTR_TLB_ENTRIES bound to: 32'b00000000000000000000000000010000 Parameter DATA_TLB_ENTRIES bound to: 32'b00000000000000000000000000010000 Parameter ASID_WIDTH bound to: 32'b00000000000000000000000000010000 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter PPNWMin bound to: 29 - type: integer Parameter TLB_ENTRIES bound to: 32'b00000000000000000000000000010000 Parameter ASID_WIDTH bound to: 32'b00000000000000000000000000010000 Parameter ASID_WIDTH bound to: 32'sb00000000000000000000000000010000 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/ptw.sv:120] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/ptw.sv:121] Parameter PLEN bound to: 32'b00000000000000000000000000111000 Parameter PMP_LEN bound to: 32'b00000000000000000000000000110110 Parameter NR_ENTRIES bound to: 8 - type: integer Parameter PLEN bound to: 32'b00000000000000000000000000111000 Parameter PMP_LEN bound to: 32'b00000000000000000000000000110110 Parameter WIDTH bound to: 32'b00000000000000000000000000111000 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000110 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/core/pmp/src/pmp_entry.sv:40] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:221] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:246] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:257] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:363] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:373] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:392] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:394] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:403] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:405] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/amo_buffer.sv:52] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000001 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter Depth bound to: 32'b00000000000000000000000000000001 Parameter Depth bound to: 32'b00000000000000000000000000000000 WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/load_store_unit.sv:433] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/load_store_unit.sv:440] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/load_store_unit.sv:451] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/load_store_unit.sv:458] Parameter NR_COMMIT_PORTS bound to: 32'b00000000000000000000000000000010 Parameter DmBaseAddress bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter AsidWidth bound to: 32'sb00000000000000000000000000010000 Parameter NrCommitPorts bound to: 32'b00000000000000000000000000000010 Parameter NrPMPEntries bound to: 8 - type: integer Parameter MHPMCounterNum bound to: 32'b00000000000000000000000000000110 WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:505] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:601] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:601] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:636] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:647] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:902] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:921] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:970] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:978] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:993] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:996] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:1002] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter NR_CORES bound to: 32'b00000000000000000000000000000001 Parameter MSIP_BASE bound to: 16'b0000000000000000 Parameter MTIMECMP_BASE bound to: 16'b0100000000000000 Parameter MTIME_BASE bound to: 16'b1011111111111000 Parameter AddrSelWidth bound to: 1 - type: integer Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/clint/axi_lite_interface.sv:78] Parameter STAGES bound to: 32'b00000000000000000000000000000010 Parameter STAGES bound to: 32'b00000000000000000000000000000010 Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter LOG_NR_BYTES bound to: 3 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:192] INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:234] INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:122] Parameter AxiAddrWidth bound to: 64 - type: integer Parameter AxiDataWidth bound to: 64 - type: integer Parameter AxiIdWidth bound to: 5 - type: integer Parameter AxiUserWidth bound to: 64 - type: integer Parameter InclUART bound to: 1'b1 Parameter InclSPI bound to: 1'b1 Parameter InclEthernet bound to: 1'b1 Parameter InclGPIO bound to: 1'b1 Parameter InclTimer bound to: 1'b1 INFO: [Synth 8-638] synthesizing module 'apb_uart' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:66] INFO: [Synth 8-3491] module 'slib_input_sync' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:28' bound to instance 'UART_IS_SIN' of component 'slib_input_sync' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:396] INFO: [Synth 8-638] synthesizing module 'slib_input_sync' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:37] INFO: [Synth 8-256] done synthesizing module 'slib_input_sync' (119#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:37] INFO: [Synth 8-3491] module 'slib_input_sync' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:28' bound to instance 'UART_IS_CTS' of component 'slib_input_sync' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:397] INFO: [Synth 8-3491] module 'slib_input_sync' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:28' bound to instance 'UART_IS_DSR' of component 'slib_input_sync' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:398] INFO: [Synth 8-3491] module 'slib_input_sync' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:28' bound to instance 'UART_IS_DCD' of component 'slib_input_sync' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:399] INFO: [Synth 8-3491] module 'slib_input_sync' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:28' bound to instance 'UART_IS_RI' of component 'slib_input_sync' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:400] Parameter SIZE bound to: 2 - type: integer INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:28' bound to instance 'UART_IF_CTS' of component 'slib_input_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:403] INFO: [Synth 8-638] synthesizing module 'slib_input_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:41] Parameter SIZE bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_input_filter' (120#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:41] Parameter SIZE bound to: 2 - type: integer INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:28' bound to instance 'UART_IF_DSR' of component 'slib_input_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:404] Parameter SIZE bound to: 2 - type: integer INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:28' bound to instance 'UART_IF_DCD' of component 'slib_input_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:405] Parameter SIZE bound to: 2 - type: integer INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:28' bound to instance 'UART_IF_RI' of component 'slib_input_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:406] INFO: [Synth 8-3491] module 'uart_interrupt' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_interrupt.vhd:33' bound to instance 'UART_IIC' of component 'uart_interrupt' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:444] INFO: [Synth 8-638] synthesizing module 'uart_interrupt' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_interrupt.vhd:49] INFO: [Synth 8-256] done synthesizing module 'uart_interrupt' (121#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_interrupt.vhd:49] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_IIC_THRE_ED' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:457] INFO: [Synth 8-638] synthesizing module 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:38] INFO: [Synth 8-256] done synthesizing module 'slib_edge_detect' (122#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:38] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_PEDET' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:657] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_FEDET' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:658] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_BIDET' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:659] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_ED_CTS' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:683] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_ED_DSR' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:684] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_ED_RI' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:685] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_ED_DCD' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:686] INFO: [Synth 8-3491] module 'uart_baudgen' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_baudgen.vhd:29' bound to instance 'UART_BG16' of component 'uart_baudgen' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:747] INFO: [Synth 8-638] synthesizing module 'uart_baudgen' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_baudgen.vhd:40] INFO: [Synth 8-256] done synthesizing module 'uart_baudgen' (123#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_baudgen.vhd:40] Parameter RATIO bound to: 8 - type: integer INFO: [Synth 8-3491] module 'slib_clock_div' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_clock_div.vhd:29' bound to instance 'UART_BG2' of component 'slib_clock_div' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:754] INFO: [Synth 8-638] synthesizing module 'slib_clock_div' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_clock_div.vhd:41] Parameter RATIO bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_clock_div' (124#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_clock_div.vhd:41] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_RCLK' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:760] Parameter WIDTH bound to: 8 - type: integer Parameter SIZE_E bound to: 6 - type: integer INFO: [Synth 8-3491] module 'slib_fifo' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd:29' bound to instance 'UART_TXFF' of component 'slib_fifo' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:767] INFO: [Synth 8-638] synthesizing module 'slib_fifo' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd:48] Parameter WIDTH bound to: 8 - type: integer Parameter SIZE_E bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_fifo' (125#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd:48] Parameter WIDTH bound to: 11 - type: integer Parameter SIZE_E bound to: 6 - type: integer INFO: [Synth 8-3491] module 'slib_fifo' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd:29' bound to instance 'UART_RXFF' of component 'slib_fifo' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:786] INFO: [Synth 8-638] synthesizing module 'slib_fifo__parameterized1' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd:48] Parameter WIDTH bound to: 11 - type: integer Parameter SIZE_E bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_fifo__parameterized1' (125#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd:48] INFO: [Synth 8-3491] module 'uart_transmitter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_transmitter.vhd:29' bound to instance 'UART_TX' of component 'uart_transmitter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:822] INFO: [Synth 8-638] synthesizing module 'uart_transmitter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_transmitter.vhd:48] INFO: [Synth 8-256] done synthesizing module 'uart_transmitter' (126#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_transmitter.vhd:48] INFO: [Synth 8-3491] module 'uart_receiver' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd:29' bound to instance 'UART_RX' of component 'uart_receiver' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:840] INFO: [Synth 8-638] synthesizing module 'uart_receiver' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd:49] Parameter WIDTH bound to: 4 - type: integer INFO: [Synth 8-3491] module 'slib_counter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_counter.vhd:29' bound to instance 'RX_BRC' of component 'slib_counter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd:122] INFO: [Synth 8-638] synthesizing module 'slib_counter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_counter.vhd:46] Parameter WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_counter' (127#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_counter.vhd:46] Parameter WIDTH bound to: 4 - type: integer Parameter THRESHOLD bound to: 10 - type: integer INFO: [Synth 8-3491] module 'slib_mv_filter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_mv_filter.vhd:29' bound to instance 'RX_MVF' of component 'slib_mv_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd:137] INFO: [Synth 8-638] synthesizing module 'slib_mv_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_mv_filter.vhd:44] Parameter WIDTH bound to: 4 - type: integer Parameter THRESHOLD bound to: 10 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_mv_filter' (128#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_mv_filter.vhd:44] Parameter SIZE bound to: 4 - type: integer INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:28' bound to instance 'RX_IFSB' of component 'slib_input_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd:150] INFO: [Synth 8-638] synthesizing module 'slib_input_filter__parameterized2' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:41] Parameter SIZE bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_input_filter__parameterized2' (128#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:41] INFO: [Synth 8-256] done synthesizing module 'uart_receiver' (129#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd:49] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:880] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:919] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:1006] INFO: [Synth 8-256] done synthesizing module 'apb_uart' (130#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:66] Parameter dly bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 9'b000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SRVAL_A bound to: 9'b000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/rgmii_soc.sv:86] Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter CINVCTRL_SEL bound to: FALSE - type: string Parameter DELAY_SRC bound to: IDATAIN - type: string Parameter HIGH_PERFORMANCE_MODE bound to: FALSE - type: string Parameter IDELAY_TYPE bound to: FIXED - type: string Parameter IDELAY_VALUE bound to: 0 - type: integer Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_DATAIN_INVERTED bound to: 1'b0 Parameter IS_IDATAIN_INVERTED bound to: 1'b0 Parameter PIPE_SEL bound to: FALSE - type: string Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: double Parameter SIGNAL_PATTERN bound to: DATA - type: string Parameter SIM_DELAY_D bound to: 0 - type: integer Parameter TARGET bound to: XILINX - type: string Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string Parameter USE_CLK90 bound to: TRUE - type: string Parameter ENABLE_PADDING bound to: 1 - type: integer Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer Parameter TX_FIFO_ADDR_WIDTH bound to: 12 - type: integer Parameter TX_FRAME_FIFO bound to: 1 - type: integer Parameter TX_DROP_BAD_FRAME bound to: 1 - type: integer Parameter TX_DROP_WHEN_FULL bound to: 0 - type: integer Parameter RX_FIFO_ADDR_WIDTH bound to: 12 - type: integer Parameter RX_FRAME_FIFO bound to: 1 - type: integer Parameter RX_DROP_BAD_FRAME bound to: 1 - type: integer Parameter RX_DROP_WHEN_FULL bound to: 1 - type: integer Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string Parameter USE_CLK90 bound to: TRUE - type: string Parameter ENABLE_PADDING bound to: 1 - type: integer Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string Parameter USE_CLK90 bound to: TRUE - type: string Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string Parameter WIDTH bound to: 5 - type: integer Parameter BUFR_DIVIDE bound to: BYPASS - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter WIDTH bound to: 5 - type: integer Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string Parameter INIT_Q1 bound to: 1'b0 Parameter INIT_Q2 bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter SRTYPE bound to: ASYNC - type: string Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter WIDTH bound to: 1 - type: integer Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D1_INVERTED bound to: 1'b0 Parameter IS_D2_INVERTED bound to: 1'b0 Parameter SRTYPE bound to: ASYNC - type: string Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter WIDTH bound to: 5 - type: integer Parameter ENABLE_PADDING bound to: 1 - type: integer Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer Parameter ETH_PRE bound to: 8'b01010101 Parameter ETH_SFD bound to: 8'b11010101 Parameter STATE_IDLE bound to: 3'b000 Parameter STATE_PAYLOAD bound to: 3'b001 Parameter STATE_WAIT_LAST bound to: 3'b010 Parameter STATE_CRC bound to: 3'b011 Parameter LFSR_WIDTH bound to: 32 - type: integer Parameter LFSR_POLY bound to: 79764919 - type: integer Parameter LFSR_CONFIG bound to: GALOIS - type: string Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer Parameter REVERSE bound to: 1 - type: integer Parameter DATA_WIDTH bound to: 8 - type: integer Parameter STYLE bound to: AUTO - type: string Parameter STYLE_INT bound to: LOOP - type: string Parameter ENABLE_PADDING bound to: 1 - type: integer Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer Parameter ETH_PRE bound to: 8'b01010101 Parameter ETH_SFD bound to: 8'b11010101 Parameter STATE_IDLE bound to: 3'b000 Parameter STATE_PREAMBLE bound to: 3'b001 Parameter STATE_PAYLOAD bound to: 3'b010 Parameter STATE_LAST bound to: 3'b011 Parameter STATE_PAD bound to: 3'b100 Parameter STATE_FCS bound to: 3'b101 Parameter STATE_WAIT_END bound to: 3'b110 Parameter STATE_IFG bound to: 3'b111 Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter AXI4_ADDRESS_WIDTH bound to: 64 - type: integer Parameter AXI4_RDATA_WIDTH bound to: 64 - type: integer Parameter AXI4_WDATA_WIDTH bound to: 64 - type: integer Parameter AXI4_ID_WIDTH bound to: 5 - type: integer Parameter AXI4_USER_WIDTH bound to: 64 - type: integer Parameter AXI_NUMBYTES bound to: 32'b00000000000000000000000000001000 Parameter BUFF_DEPTH_SLAVE bound to: 32'b00000000000000000000000000000010 Parameter APB_NUM_SLAVES bound to: 32'b00000000000000000000000000001000 Parameter APB_ADDR_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter ID_WIDTH bound to: 5 - type: integer Parameter ADDR_WIDTH bound to: 64 - type: integer Parameter USER_WIDTH bound to: 64 - type: integer Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000010100010 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010100010 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter THRESHOLD bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010100010 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ALM_EMPTY_TH bound to: 32'b00000000000000000000000000000001 Parameter ALM_FULL_TH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010100010 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 Parameter ID_WIDTH bound to: 5 - type: integer Parameter ADDR_WIDTH bound to: 64 - type: integer Parameter USER_WIDTH bound to: 64 - type: integer Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter DATA_WIDTH bound to: 64 - type: integer Parameter USER_WIDTH bound to: 64 - type: integer Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter STRB_WIDTH bound to: 32'sb00000000000000000000000000001000 Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000010001001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010001001 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter THRESHOLD bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010001001 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ALM_EMPTY_TH bound to: 32'b00000000000000000000000000000001 Parameter ALM_FULL_TH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010001001 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 Parameter ID_WIDTH bound to: 5 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter USER_WIDTH bound to: 64 - type: integer Parameter BUFFER_DEPTH bound to: 2 - type: integer Parameter STRB_WIDTH bound to: 8 - type: integer Parameter BUFFER_DEPTH bound to: 2 - type: integer Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000010001000 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010001000 Parameter DEPTH bound to: 2 - type: integer Parameter THRESHOLD bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010001000 Parameter DEPTH bound to: 2 - type: integer Parameter ALM_EMPTY_TH bound to: 32'b00000000000000000000000000000001 Parameter ALM_FULL_TH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010001000 Parameter DEPTH bound to: 2 - type: integer Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 2 - type: integer Parameter ID_WIDTH bound to: 5 - type: integer Parameter USER_WIDTH bound to: 64 - type: integer Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000001000111 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000111 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter THRESHOLD bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000111 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ALM_EMPTY_TH bound to: 32'b00000000000000000000000000000001 Parameter ALM_FULL_TH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000111 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 Parameter APB_ADDR_WIDTH bound to: 32 - type: integer Parameter TIMER_CNT bound to: 2 - type: integer Parameter APB_ADDR_WIDTH bound to: 32 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/src/apb_timer/timer.sv:92] INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/src/apb_timer/timer.sv:116] Parameter ADDR_WIDTH bound to: 32'sb00000000000000000000000000100000 Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000000100000 Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 Parameter N_TARGET bound to: 32'sb00000000000000000000000000000010 Parameter MAX_PRIO bound to: 32'sb00000000000000000000000000000111 Parameter SRCW bound to: 32'sb00000000000000000000000000000101 Parameter PRIOW bound to: 3 - type: integer Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 Parameter MAX_PRIO bound to: 32'sb00000000000000000000000000000111 Parameter ALGORITHM bound to: SEQUENTIAL - type: string Parameter SRCW bound to: 32'b00000000000000000000000000000101 Parameter PRIOW bound to: 32'b00000000000000000000000000000011 Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_MAX_WRITE_TXNS bound to: 32'b00000000000000000000000000000001 Parameter RISCV_WORD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_STRB_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_MAX_WRITE_TXNS bound to: 32'b00000000000000000000000000000001 Parameter RISCV_WORD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_STRB_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter ADDR_BEGIN bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ADDR_END bound to: 64'b1111111111111111111111111111111111111111111111111111111111111111 Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_MAX_WRITE_TXNS bound to: 32'b00000000000000000000000000000001 Parameter RISCV_WORD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_STRB_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter OUTSTND_BURSTS_WIDTH bound to: 32'b00000000000000000000000000000001 Parameter AXI_ALU_RATIO bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv:580] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv:809] Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv:39] Parameter ADDR_BEGIN bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ADDR_END bound to: 64'b1111111111111111111111111111111111111111111111111111111111111111 Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter N_IDS bound to: 32 - type: integer Parameter N_INP bound to: 2 - type: integer Parameter ARBITER bound to: rr - type: string Parameter N_INP bound to: 2 - type: integer Parameter ARBITER bound to: rr - type: string Parameter NumIn bound to: 2 - type: integer Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000001 --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:54 ; elapsed = 00:00:59 . Memory (MB): peak = 2918.309 ; gain = 732.793 ; free physical = 15381 ; free virtual = 37380 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:01:04 ; elapsed = 00:01:10 . Memory (MB): peak = 2927.215 ; gain = 741.699 ; free physical = 15506 ; free virtual = 37506 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:01:04 ; elapsed = 00:01:10 . Memory (MB): peak = 2927.215 ; gain = 741.699 ; free physical = 15506 ; free virtual = 37506 --------------------------------------------------------------------------------- INFO: [Project 1-454] Reading design checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.dcp' for cell 'i_xlnx_axi_clock_converter_ddr' INFO: [Project 1-454] Reading design checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.dcp' for cell 'i_xlnx_clk_gen' INFO: [Project 1-454] Reading design checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.dcp' for cell 'i_ddr' INFO: [Project 1-454] Reading design checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.dcp' for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi' INFO: [Project 1-454] Reading design checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.dcp' for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi' INFO: [Project 1-454] Reading design checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.dcp' for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_gpio' Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2967.043 ; gain = 0.000 ; free physical = 15235 ; free virtual = 37234 INFO: [Netlist 29-17] Analyzing 871 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.1 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. i_xlnx_clk_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. INFO: [Opt 31-140] Inserted 16 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 17 OBUFs to IO ports without IO buffers. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'i_xlnx_clk_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc] for cell 'i_ddr' WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc:544] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc:551] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc] for cell 'i_ddr' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen_board.xdc] for cell 'i_xlnx_clk_gen/inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen_board.xdc] for cell 'i_xlnx_clk_gen/inst' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc] for cell 'i_xlnx_clk_gen/inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc] for cell 'i_xlnx_clk_gen/inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_gpio/U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_gpio/U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_gpio/U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_gpio/U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_board.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_board.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0' INFO: [Timing 38-2] Deriving generated clocks Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc] CRITICAL WARNING: [Vivado 12-1815] Setting property 'IOSTANDARD' is not allowed for GT terminals. [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:16] CRITICAL WARNING: [Vivado 12-1815] Setting property 'IOSTANDARD' is not allowed for GT terminals. [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:17] CRITICAL WARNING: [Vivado 12-1815] Setting property 'IOSTANDARD' is not allowed for GT terminals. [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:18] CRITICAL WARNING: [Vivado 12-1815] Setting property 'IOSTANDARD' is not allowed for GT terminals. [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:19] CRITICAL WARNING: [Common 17-69] Command failed: 'E6' is not a valid site or package pin name. [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:20] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/constraints/ariane.xdc] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/darshak/cva6/corev_apu/fpga/constraints/ariane.xdc:19] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/constraints/ariane.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/darshak/cva6/corev_apu/fpga/constraints/ariane.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_clocks.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_clocks.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'rtl_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'rtl_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'rtl_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'rtl_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'rtl_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'rtl_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'rtl_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'rtl_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3593.867 ; gain = 0.000 ; free physical = 14990 ; free virtual = 36989 INFO: [Project 1-111] Unisim Transformation Summary: A total of 380 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 26 instances OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 306 instances RAMB16_S9_S36 => RAMB36E1: 10 instances RTL Elaboration Complete: : Time (s): cpu = 00:02:35 ; elapsed = 00:01:58 . Memory (MB): peak = 3593.867 ; gain = 1408.352 ; free physical = 15198 ; free virtual = 37198 418 Infos, 65 Warnings, 5 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:02:43 ; elapsed = 00:02:11 . Memory (MB): peak = 3593.867 ; gain = 1408.352 ; free physical = 15198 ; free virtual = 37198 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads # set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] # launch_runs synth_1 INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.xci' is already up-to-date [Tue Oct 10 09:01:44 2023] Launched synth_1... Run output will be captured here: /home/darshak/cva6/corev_apu/fpga/ariane.runs/synth_1/runme.log # wait_on_run synth_1 [Tue Oct 10 09:01:44 2023] Waiting for synth_1 to finish... *** Running vivado with args -log ariane_xilinx.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ariane_xilinx.tcl ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source ariane_xilinx.tcl -notrace Command: synth_design -top ariane_xilinx -part xc7k325tffg900-2 -retiming Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t' INFO: [Device 21-403] Loading part xc7k325tffg900-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 1629619 WARNING: [Synth 8-2507] parameter declaration becomes local in miss_handler with formal parameter declaration list [/home/darshak/cva6/core/cache_subsystem/miss_handler.sv:69] WARNING: [Synth 8-2507] parameter declaration becomes local in rgmii_lfsr with formal parameter declaration list [/home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/rgmii_lfsr.sv:364] --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2160.328 ; gain = 35.875 ; free physical = 14150 ; free virtual = 36150 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'ariane_xilinx' [/home/darshak/cva6/corev_apu/fpga/src/ariane_xilinx.sv:14] Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 2 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter NumWords bound to: 3145728 - type: integer Parameter NBSlave bound to: 2 - type: integer Parameter AxiAddrWidth bound to: 64 - type: integer Parameter AxiDataWidth bound to: 64 - type: integer Parameter AxiIdWidthMaster bound to: 4 - type: integer Parameter AxiIdWidthSlaves bound to: 5 - type: integer Parameter AxiUserWidth bound to: 64 - type: integer Parameter AXI_XBAR_CFG[NoSlvPorts] bound to: 2 - type: integer Parameter AXI_XBAR_CFG[NoMstPorts] bound to: 10 - type: integer Parameter AXI_XBAR_CFG[MaxMstTrans] bound to: 1 - type: integer Parameter AXI_XBAR_CFG[MaxSlvTrans] bound to: 1 - type: integer Parameter AXI_XBAR_CFG[FallThrough] bound to: 1'b0 Parameter AXI_XBAR_CFG[LatencyMode] bound to: 10'b1111111111 Parameter AXI_XBAR_CFG[AxiIdWidthSlvPorts] bound to: 4 - type: integer Parameter AXI_XBAR_CFG[AxiIdUsedSlvPorts] bound to: 4 - type: integer Parameter AXI_XBAR_CFG[UniqueIds] bound to: 1'b0 Parameter AXI_XBAR_CFG[AxiAddrWidth] bound to: 64 - type: integer Parameter AXI_XBAR_CFG[AxiDataWidth] bound to: 64 - type: integer Parameter AXI_XBAR_CFG[NoAddrRules] bound to: 10 - type: integer INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 4 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'AXI_BUS' [/home/darshak/cva6/core/include/axi_intf.sv:19] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 4 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'AXI_BUS' (0#1) [/home/darshak/cva6/core/include/axi_intf.sv:19] INFO: [Synth 8-6157] synthesizing module 'bootrom_64' [/home/darshak/cva6/corev_apu/fpga/src/bootrom/bootrom_64.sv:17] Parameter RomSize bound to: 32'sb00000000000000000000001101111111 INFO: [Synth 8-6155] done synthesizing module 'bootrom_64' (1#1) [/home/darshak/cva6/corev_apu/fpga/src/bootrom/bootrom_64.sv:17] INFO: [Synth 8-6157] synthesizing module 'rstgen' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rstgen.sv:13] INFO: [Synth 8-6157] synthesizing module 'rstgen_bypass' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv:15] Parameter NumRegs bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6155] done synthesizing module 'rstgen_bypass' (2#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv:15] INFO: [Synth 8-6155] done synthesizing module 'rstgen' (3#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rstgen.sv:13] INFO: [Synth 8-6157] synthesizing module 'axi_xbar_intf' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv:242] Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter Cfg[NoSlvPorts] bound to: 2 - type: integer Parameter Cfg[NoMstPorts] bound to: 10 - type: integer Parameter Cfg[MaxMstTrans] bound to: 1 - type: integer Parameter Cfg[MaxSlvTrans] bound to: 1 - type: integer Parameter Cfg[FallThrough] bound to: 1'b0 Parameter Cfg[LatencyMode] bound to: 10'b1111111111 Parameter Cfg[AxiIdWidthSlvPorts] bound to: 4 - type: integer Parameter Cfg[AxiIdUsedSlvPorts] bound to: 4 - type: integer Parameter Cfg[UniqueIds] bound to: 1'b0 Parameter Cfg[AxiAddrWidth] bound to: 64 - type: integer Parameter Cfg[AxiDataWidth] bound to: 64 - type: integer Parameter Cfg[NoAddrRules] bound to: 10 - type: integer Parameter AxiIdWidthMstPorts bound to: 32'b00000000000000000000000000000101 INFO: [Synth 8-6157] synthesizing module 'axi_xbar' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv:18] Parameter Cfg[NoSlvPorts] bound to: 2 - type: integer Parameter Cfg[NoMstPorts] bound to: 10 - type: integer Parameter Cfg[MaxMstTrans] bound to: 1 - type: integer Parameter Cfg[MaxSlvTrans] bound to: 1 - type: integer Parameter Cfg[FallThrough] bound to: 1'b0 Parameter Cfg[LatencyMode] bound to: 10'b1111111111 Parameter Cfg[AxiIdWidthSlvPorts] bound to: 4 - type: integer Parameter Cfg[AxiIdUsedSlvPorts] bound to: 4 - type: integer Parameter Cfg[UniqueIds] bound to: 1'b0 Parameter Cfg[AxiAddrWidth] bound to: 64 - type: integer Parameter Cfg[AxiDataWidth] bound to: 64 - type: integer Parameter Cfg[NoAddrRules] bound to: 10 - type: integer Parameter ATOPs bound to: 1'b1 Parameter cfg_NoMstPorts bound to: 10 - type: integer INFO: [Synth 8-6157] synthesizing module 'addr_decode' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/addr_decode.sv:30] Parameter NoIndices bound to: 10 - type: integer Parameter NoRules bound to: 10 - type: integer Parameter IdxWidth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6155] done synthesizing module 'addr_decode' (4#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/addr_decode.sv:30] INFO: [Synth 8-6157] synthesizing module 'axi_demux' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:19] Parameter AxiIdWidth bound to: 4 - type: integer Parameter NoMstPorts bound to: 32'b00000000000000000000000000001011 Parameter MaxTrans bound to: 1 - type: integer Parameter AxiLookBits bound to: 4 - type: integer Parameter UniqueIds bound to: 1'b0 Parameter FallThrough bound to: 1'b0 Parameter SpillAw bound to: 1'b1 Parameter SpillW bound to: 1'b1 Parameter SpillB bound to: 1'b1 Parameter SpillAr bound to: 1'b1 Parameter SpillR bound to: 1'b1 Parameter SelectWidth bound to: 32'b00000000000000000000000000000100 Parameter IdCounterWidth bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6157] synthesizing module 'axi_demux_id_counters' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:576] Parameter AxiIdBits bound to: 4 - type: integer Parameter CounterWidth bound to: 32'b00000000000000000000000000000001 Parameter NoCounters bound to: 32'b00000000000000000000000000010000 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-6157] synthesizing module 'delta_counter' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] Parameter WIDTH bound to: 32'b00000000000000000000000000000001 Parameter STICKY_OVERFLOW bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'delta_counter' (5#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:626] INFO: [Synth 8-6155] done synthesizing module 'axi_demux_id_counters' (6#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:576] INFO: [Synth 8-6157] synthesizing module 'spill_register' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable' (7#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register' (8#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'fifo_v3' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 1 - type: integer Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'fifo_v3' (9#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized0' (9#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized0' (9#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized1' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized1' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized1' (9#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized1' (9#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] Parameter NumIn bound to: 32'b00000000000000000000000000001011 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6157] synthesizing module 'lzc' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] Parameter WIDTH bound to: 32'b00000000000000000000000000001011 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6155] done synthesizing module 'lzc' (10#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree' (11#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized2' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized2' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized2' (11#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized2' (11#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized3' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized3' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized3' (11#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized3' (11#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] Parameter NumIn bound to: 32'b00000000000000000000000000001011 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized0' (11#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6155] done synthesizing module 'axi_demux' (12#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_demux.sv:19] INFO: [Synth 8-6157] synthesizing module 'axi_err_slv' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_err_slv.sv:19] Parameter AxiIdWidth bound to: 4 - type: integer Parameter Resp bound to: 2'b11 Parameter RespWidth bound to: 64 - type: integer Parameter RespData bound to: 64'b1100101000010001101010110001111010111010110111001010101100011110 Parameter ATOPs bound to: 1'b1 Parameter MaxTrans bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6157] synthesizing module 'axi_atop_filter' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv:37] Parameter AxiIdWidth bound to: 4 - type: integer Parameter AxiMaxWriteTxns bound to: 32'b00000000000000000000000000000100 Parameter COUNTER_WIDTH bound to: 32'b00000000000000000000000000000011 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv:118] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv:268] INFO: [Synth 8-6157] synthesizing module 'stream_register' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/stream_register.sv:14] INFO: [Synth 8-6157] synthesizing module 'fifo_v2' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 Parameter ALM_EMPTY_TH bound to: 32'b00000000000000000000000000000001 Parameter ALM_FULL_TH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized0' (12#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6155] done synthesizing module 'fifo_v2' (13#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] INFO: [Synth 8-6155] done synthesizing module 'stream_register' (14#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/stream_register.sv:14] INFO: [Synth 8-6155] done synthesizing module 'axi_atop_filter' (15#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_atop_filter.sv:37] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized1' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b1 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized1' (15#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized2' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized2' (15#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized3' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized3' (15#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'counter' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/counter.sv:14] Parameter WIDTH bound to: 32'b00000000000000000000000000001000 Parameter STICKY_OVERFLOW bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'delta_counter__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] Parameter WIDTH bound to: 32'b00000000000000000000000000001000 Parameter STICKY_OVERFLOW bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'delta_counter__parameterized0' (15#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] INFO: [Synth 8-6155] done synthesizing module 'counter' (16#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/counter.sv:14] INFO: [Synth 8-6155] done synthesizing module 'axi_err_slv' (17#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_err_slv.sv:19] INFO: [Synth 8-6157] synthesizing module 'axi_mux' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_mux.sv:27] Parameter SlvAxiIDWidth bound to: 4 - type: integer Parameter NoSlvPorts bound to: 2 - type: integer Parameter MaxWTrans bound to: 1 - type: integer Parameter FallThrough bound to: 1'b0 Parameter SpillAw bound to: 1'b1 Parameter SpillW bound to: 1'b1 Parameter SpillB bound to: 1'b1 Parameter SpillAr bound to: 1'b1 Parameter SpillR bound to: 1'b1 Parameter MstIdxBits bound to: 32'b00000000000000000000000000000001 Parameter MstAxiIDWidth bound to: 32'b00000000000000000000000000000101 INFO: [Synth 8-6157] synthesizing module 'axi_id_prepend' [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_id_prepend.sv:18] Parameter NoBus bound to: 1 - type: integer Parameter AxiIdWidthSlvPort bound to: 4 - type: integer Parameter AxiIdWidthMstPort bound to: 32'b00000000000000000000000000000101 Parameter PreIdWidth bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6155] done synthesizing module 'axi_id_prepend' (18#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_id_prepend.sv:18] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized1' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] Parameter NumIn bound to: 2 - type: integer Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] Parameter WIDTH bound to: 2 - type: integer Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized0' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized1' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized4' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 1 - type: integer Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 1 - type: integer INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized4' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized4' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized4' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized4' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized4' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized5' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized5' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized5' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized5' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'rr_arb_tree__parameterized2' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] Parameter NumIn bound to: 2 - type: integer Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6155] done synthesizing module 'rr_arb_tree__parameterized2' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv:47] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized6' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized6' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized6' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized6' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6157] synthesizing module 'spill_register__parameterized7' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'spill_register_flushable__parameterized7' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] Parameter Bypass bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'spill_register_flushable__parameterized7' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv:17] INFO: [Synth 8-6155] done synthesizing module 'spill_register__parameterized7' (18#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/spill_register.sv:17] INFO: [Synth 8-6155] done synthesizing module 'axi_mux' (19#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_mux.sv:27] INFO: [Synth 8-6155] done synthesizing module 'axi_xbar' (20#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv:18] INFO: [Synth 8-6155] done synthesizing module 'axi_xbar_intf' (21#1) [/home/darshak/cva6/vendor/pulp-platform/axi/src/axi_xbar.sv:242] INFO: [Synth 8-6157] synthesizing module 'dmi_jtag' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv:19] Parameter IdcodeValue bound to: 1 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv:101] INFO: [Synth 8-6157] synthesizing module 'dmi_jtag_tap' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv:19] Parameter IrLength bound to: 32'b00000000000000000000000000000101 Parameter IdcodeValue bound to: 1 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv:186] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv:207] INFO: [Synth 8-6157] synthesizing module 'cluster_clock_inverter' [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv:54] INFO: [Synth 8-6157] synthesizing module 'tc_clk_inverter' [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv:55] INFO: [Synth 8-6155] done synthesizing module 'tc_clk_inverter' (22#1) [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv:55] INFO: [Synth 8-6155] done synthesizing module 'cluster_clock_inverter' (23#1) [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv:54] INFO: [Synth 8-6157] synthesizing module 'pulp_clock_mux2' [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv:66] INFO: [Synth 8-6157] synthesizing module 'tc_clk_mux2' [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv:64] INFO: [Synth 8-6155] done synthesizing module 'tc_clk_mux2' (24#1) [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv:64] INFO: [Synth 8-6155] done synthesizing module 'pulp_clock_mux2' (25#1) [/home/darshak/cva6/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv:66] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv:260] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv:260] INFO: [Synth 8-6155] done synthesizing module 'dmi_jtag_tap' (26#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv:19] INFO: [Synth 8-6157] synthesizing module 'dmi_cdc' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_cdc.sv:19] INFO: [Synth 8-6157] synthesizing module 'cdc_2phase' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:19] INFO: [Synth 8-6157] synthesizing module 'cdc_2phase_src' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:68] INFO: [Synth 8-6155] done synthesizing module 'cdc_2phase_src' (27#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:68] INFO: [Synth 8-6157] synthesizing module 'cdc_2phase_dst' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:118] INFO: [Synth 8-6155] done synthesizing module 'cdc_2phase_dst' (28#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:118] INFO: [Synth 8-6155] done synthesizing module 'cdc_2phase' (29#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:19] INFO: [Synth 8-6157] synthesizing module 'cdc_2phase__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:19] INFO: [Synth 8-6157] synthesizing module 'cdc_2phase_src__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:68] INFO: [Synth 8-6155] done synthesizing module 'cdc_2phase_src__parameterized0' (29#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:68] INFO: [Synth 8-6157] synthesizing module 'cdc_2phase_dst__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:118] INFO: [Synth 8-6155] done synthesizing module 'cdc_2phase_dst__parameterized0' (29#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:118] INFO: [Synth 8-6155] done synthesizing module 'cdc_2phase__parameterized0' (29#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/cdc_2phase.sv:19] INFO: [Synth 8-6155] done synthesizing module 'dmi_cdc' (30#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_cdc.sv:19] INFO: [Synth 8-6155] done synthesizing module 'dmi_jtag' (31#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv:19] INFO: [Synth 8-6157] synthesizing module 'dm_top' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_top.sv:20] Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter DmBaseAddress bound to: 32'b00000000000000000001000000000000 Parameter SelectableHarts bound to: 1'b1 Parameter ReadByteEnable bound to: 1'b1 INFO: [Synth 8-6157] synthesizing module 'dm_csrs' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv:18] Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 Parameter HartSelLen bound to: 32'b00000000000000000000000000000001 Parameter NrHartsAligned bound to: 32'b00000000000000000000000000000010 Parameter DataEnd bound to: 8'b00000101 Parameter ProgBufEnd bound to: 8'b00100111 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv:294] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv:360] INFO: [Synth 8-6157] synthesizing module 'fifo_v2__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ALM_EMPTY_TH bound to: 32'b00000000000000000000000000000001 Parameter ALM_FULL_TH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized5' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized5' (31#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6155] done synthesizing module 'fifo_v2__parameterized0' (31#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv:13] INFO: [Synth 8-6155] done synthesizing module 'dm_csrs' (32#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv:18] INFO: [Synth 8-6157] synthesizing module 'dm_sba' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_sba.sv:18] Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter ReadByteEnable bound to: 1'b1 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_sba.sv:72] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_sba.sv:101] INFO: [Synth 8-6155] done synthesizing module 'dm_sba' (33#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_sba.sv:18] INFO: [Synth 8-6157] synthesizing module 'dm_mem' [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:19] Parameter NrHarts bound to: 32'b00000000000000000000000000000001 Parameter BusWidth bound to: 32'b00000000000000000000000001000000 Parameter SelectableHarts bound to: 1'b1 Parameter DmBaseAddress bound to: 32'b00000000000000000001000000000000 Parameter DbgAddressBits bound to: 32'b00000000000000000000000000001100 Parameter HartSelLen bound to: 32'b00000000000000000000000000000001 Parameter NrHartsAligned bound to: 32'b00000000000000000000000000000010 Parameter MaxAar bound to: 32'b00000000000000000000000000000100 Parameter HasSndScratch bound to: 1'b1 Parameter LoadBaseAddr bound to: 5'b01010 Parameter DataBaseAddr bound to: 12'b001110000000 Parameter DataEndAddr bound to: 12'b001110000111 Parameter ProgBufBaseAddr bound to: 12'b001101100000 Parameter ProgBufEndAddr bound to: 12'b001101111111 Parameter AbstractCmdBaseAddr bound to: 12'b001100111000 Parameter AbstractCmdEndAddr bound to: 12'b001101011111 Parameter WhereToAddr bound to: 12'b001100000000 Parameter FlagsBaseAddr bound to: 12'b010000000000 Parameter FlagsEndAddr bound to: 12'b011111111111 Parameter HaltedAddr bound to: 12'b000100000000 Parameter GoingAddr bound to: 12'b000100000100 Parameter ResumingAddr bound to: 12'b000100001000 Parameter ExceptionAddr bound to: 12'b000100001100 INFO: [Synth 8-6157] synthesizing module 'debug_rom' [/home/darshak/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom.sv:17] Parameter RomSize bound to: 32'b00000000000000000000000000010011 INFO: [Synth 8-6155] done synthesizing module 'debug_rom' (34#1) [/home/darshak/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom.sv:17] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:144] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:144] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:242] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:272] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:351] INFO: [Synth 8-6155] done synthesizing module 'dm_mem' (35#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_mem.sv:19] INFO: [Synth 8-6155] done synthesizing module 'dm_top' (36#1) [/home/darshak/cva6/corev_apu/riscv-dbg/src/dm_top.sv:20] INFO: [Synth 8-6157] synthesizing module 'axi2mem' [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:20] Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_ADDR_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter LOG_NR_BYTES bound to: 3 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:192] INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:234] INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:122] INFO: [Synth 8-6155] done synthesizing module 'axi2mem' (37#1) [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:20] INFO: [Synth 8-6157] synthesizing module 'axi_adapter' [/home/darshak/cva6/core/cache_subsystem/axi_adapter.sv:19] Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter CRITICAL_WORD_FIRST bound to: 1'b0 Parameter CACHELINE_BYTE_OFFSET bound to: 32'b00000000000000000000000000001000 Parameter AXI_ADDR_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_ID_WIDTH bound to: 32'b00000000000000000000000000000100 Parameter BURST_SIZE bound to: 0 - type: integer Parameter ADDR_INDEX bound to: 1 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/axi_adapter.sv:430] WARNING: [Synth 8-2898] ignoring assertion [/home/darshak/cva6/core/cache_subsystem/axi_adapter.sv:169] WARNING: [Synth 8-2898] ignoring assertion [/home/darshak/cva6/core/cache_subsystem/axi_adapter.sv:197] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/axi_adapter.sv:430] INFO: [Synth 8-6155] done synthesizing module 'axi_adapter' (38#1) [/home/darshak/cva6/core/cache_subsystem/axi_adapter.sv:19] INFO: [Synth 8-6157] synthesizing module 'ariane' [/home/darshak/cva6/corev_apu/src/ariane.sv:16] Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter AxiAddrWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6157] synthesizing module 'cvxif_example_coprocessor' [/home/darshak/cva6/core/cvxif_example/cvxif_example_coprocessor.sv:12] INFO: [Synth 8-6157] synthesizing module 'instr_decoder' [/home/darshak/cva6/core/cvxif_example/instr_decoder.sv:10] Parameter NbInstr bound to: 32'sb00000000000000000000000000000010 Parameter CoproInstr bound to: 140'b00000000000000000000000000101011000000000000000000000000011111111000000000000000000000000000000101101100000000000000000000000001111111110000 INFO: [Synth 8-6155] done synthesizing module 'instr_decoder' (39#1) [/home/darshak/cva6/core/cvxif_example/instr_decoder.sv:10] INFO: [Synth 8-6157] synthesizing module 'fifo_v3__parameterized6' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] Parameter FALL_THROUGH bound to: 1'b1 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter DEPTH bound to: 32'b00000000000000000000000000001000 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000011 Parameter FifoDepth bound to: 32'b00000000000000000000000000001000 INFO: [Synth 8-6155] done synthesizing module 'fifo_v3__parameterized6' (39#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/fifo_v3.sv:13] INFO: [Synth 8-6157] synthesizing module 'counter__parameterized0' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/counter.sv:14] Parameter WIDTH bound to: 32'b00000000000000000000000000000100 Parameter STICKY_OVERFLOW bound to: 1'b0 INFO: [Synth 8-6157] synthesizing module 'delta_counter__parameterized1' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] Parameter WIDTH bound to: 32'b00000000000000000000000000000100 Parameter STICKY_OVERFLOW bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'delta_counter__parameterized1' (39#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/delta_counter.sv:13] INFO: [Synth 8-6155] done synthesizing module 'counter__parameterized0' (39#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/counter.sv:14] INFO: [Synth 8-6155] done synthesizing module 'cvxif_example_coprocessor' (40#1) [/home/darshak/cva6/core/cvxif_example/cvxif_example_coprocessor.sv:12] INFO: [Synth 8-6157] synthesizing module 'cva6' [/home/darshak/cva6/core/cva6.sv:16] Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter AxiAddrWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter NumPorts bound to: 3 - type: integer INFO: [Synth 8-6157] synthesizing module 'perf_counters' [/home/darshak/cva6/core/perf_counters.sv:16] Parameter NumPorts bound to: 3 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/perf_counters.sv:119] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/perf_counters.sv:143] INFO: [Synth 8-6155] done synthesizing module 'perf_counters' (41#1) [/home/darshak/cva6/core/perf_counters.sv:16] INFO: [Synth 8-6157] synthesizing module 'wt_cache_subsystem' [/home/darshak/cva6/core/cache_subsystem/wt_cache_subsystem.sv:22] Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter NumPorts bound to: 3 - type: integer Parameter AxiAddrWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-6157] synthesizing module 'cva6_icache' [/home/darshak/cva6/core/cache_subsystem/cva6_icache.sv:28] Parameter RdTxId bound to: 2'b00 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'sram' [/home/darshak/cva6/common/local/util/sram.sv:21] Parameter DATA_WIDTH bound to: 45 - type: integer Parameter USER_WIDTH bound to: 1 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer Parameter SIM_INIT bound to: none - type: string Parameter OUT_REGS bound to: 0 - type: integer Parameter DATA_WIDTH_ALIGNED bound to: 64 - type: integer Parameter USER_WIDTH_ALIGNED bound to: 64 - type: integer Parameter BE_WIDTH_ALIGNED bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'tc_sram_wrapper' [/home/darshak/cva6/common/local/util/tc_sram_fpga_wrapper.sv:10] Parameter NumWords bound to: 256 - type: integer Parameter DataWidth bound to: 32'b00000000000000000000000001000000 Parameter ByteWidth bound to: 8 - type: integer Parameter NumPorts bound to: 1 - type: integer Parameter Latency bound to: 1 - type: integer Parameter SimInit bound to: none - type: string Parameter PrintSimCfg bound to: 1'b0 Parameter AddrWidth bound to: 32'b00000000000000000000000000001000 Parameter BeWidth bound to: 32'b00000000000000000000000000001000 INFO: [Synth 8-6157] synthesizing module 'SyncSpRamBeNx64' [/home/darshak/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv:28] Parameter ADDR_WIDTH bound to: 8 - type: integer Parameter DATA_DEPTH bound to: 256 - type: integer Parameter OUT_REGS bound to: 0 - type: integer Parameter SIM_INIT bound to: 1 - type: integer Parameter DATA_BYTES bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'SyncSpRamBeNx64' (42#1) [/home/darshak/cva6/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv:28] INFO: [Synth 8-6155] done synthesizing module 'tc_sram_wrapper' (43#1) [/home/darshak/cva6/common/local/util/tc_sram_fpga_wrapper.sv:10] INFO: [Synth 8-6155] done synthesizing module 'sram' (44#1) [/home/darshak/cva6/common/local/util/sram.sv:21] INFO: [Synth 8-6157] synthesizing module 'sram__parameterized0' [/home/darshak/cva6/common/local/util/sram.sv:21] Parameter DATA_WIDTH bound to: 128 - type: integer Parameter USER_WIDTH bound to: 128 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer Parameter SIM_INIT bound to: none - type: string Parameter OUT_REGS bound to: 0 - type: integer Parameter DATA_WIDTH_ALIGNED bound to: 128 - type: integer Parameter USER_WIDTH_ALIGNED bound to: 128 - type: integer Parameter BE_WIDTH_ALIGNED bound to: 16 - type: integer INFO: [Synth 8-6155] done synthesizing module 'sram__parameterized0' (44#1) [/home/darshak/cva6/common/local/util/sram.sv:21] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/cva6_icache.sv:182] INFO: [Synth 8-6157] synthesizing module 'lzc__parameterized1' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] Parameter WIDTH bound to: 32'b00000000000000000000000000000100 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized1' (44#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] INFO: [Synth 8-6157] synthesizing module 'lfsr' [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv:22] Parameter LfsrWidth bound to: 32'b00000000000000000000000000001000 Parameter OutWidth bound to: 32'b00000000000000000000000000000010 Parameter RstVal bound to: 8'b11111111 Parameter CipherLayers bound to: 32'b00000000000000000000000000000000 Parameter CipherReg bound to: 1'b1 Parameter Masks bound to: 3904'b0000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000001111000000000000000000000000000000000000000000000000000000000001110010000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001111101000000000000000000000000000000000000000000000000000000001111111010000000000000000000000000000000000000000000000000000001111111100000000000000000000000000000000000000000000000000000001100100101100000000000000000000000000000000000000000000000000001101100011110000000000000000000000000000000000000000000000000001001010010110000000000000000000000000000000000000000000000000001001001001011000000000000000000000000000000000000000000000000001000011010101110000000000000000000000000000000000000000000000001000011001111001000000000000000000000000000000000000000000000001000000110000111000000000000000000000000000000000000000000000001000000110110011010000000000000000000000000000000000000000000001000000001111111110000000000000000000000000000000000000000000001000000001111011100000000000000000000000000000000000000000000001000000000100101100100000000000000000000000000000000000000000001000000000011010101000000000000000000000000000000000000000000001000000000001001011001000000000000000000000000000000000000000001000000000001011100001110000000000000000000000000000000000000001000000000000010011110011000000000000000000000000000000000000001000000000000001110010110100000000000000000000000000000000000001000000000000000110101011100000000000000000000000000000000000001000000000000000100111100011000000000000000000000000000000000001000000000000000001011000001100000000000000000000000000000000001000000000000000001100100100100000000000000000000000000000000001000000000000000000010110110110000000000000000000000000000000001000000000000000000011101010011000000000000000000000000000000001000000000000000000000111101000110000000000000000000000000000001000000000000000000000101010111111000000000000000000000000000001000000000000000000000010000100001000000000000000000000000000001000000000000000000000010010001111100000000000000000000000000001000000000000000000000000011101001110000000000000000000000000001000000000000000000000000010101110100100000000000000000000000001000000000000000000000000001000011010100000000000000000000000001000000000000000000000000001001000010011000000000000000000000001000000000000000000000000000001110111111000000000000000000000001000000000000000000000000000010010001110110000000000000000000001000000000000000000000000000000100001110111000000000000000000001000000000000000000000000000000100001000110100000000000000000001000000000000000000000000000000001010111010010000000000000000001000000000000000000000000000000000111010011111000000000000000001000000000000000000000000000000000010001010011000000000000000001000000000000000000000000000000000011001000111100000000000000001000000000000000000000000000000000000100100001110000000000000001000000000000000000000000000000000000011111011001100000000000001000000000000000000000000000000000000001101011111010000000000001000000000000000000000000000000000000001011010100101000000000001000000000000000000000000000000000000000010110100101100000000001000000000000000000000000000000000000000010000101011110000000001000000000000000000000000000000000000000000110111011110000000001000000000000000000000000000000000000000000110000001101000000001000000000000000000000000000000000000000000001011011001010000001000000000000000000000000000000000000000000001000000101101000001000000000000000000000000000000000000000000000011001101010100001000000000000000000000000000000000000000000000100100110000010001000000000000000000000000000000000000000000000000111011110110001000000000000000000000000000000000000000000000000100110110001101000000000000000000000000000000000000000000000000001111110011011000000000000000000000000000000000000000000000000001100111100010 Parameter Sbox4 bound to: 64'b0010000101110100100011111110001111011010000010011011011001011100 Parameter Perm bound to: 384'b111111101111011111001111111110101110011110001110111101101101011101001101111100101100011100001100111011101011011011001011111010101010011010001010111001101001011001001001111000101000011000001000110111100111010111000111110110100110010110000110110101100101010101000101110100100100010100000100110011100011010011000011110010100010010010000010110001100001010001000001110000100000010000000000 INFO: [Synth 8-6155] done synthesizing module 'lfsr' (45#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv:22] INFO: [Synth 8-6155] done synthesizing module 'cva6_icache' (46#1) [/home/darshak/cva6/core/cache_subsystem/cva6_icache.sv:28] INFO: [Synth 8-6157] synthesizing module 'wt_dcache' [/home/darshak/cva6/core/cache_subsystem/wt_dcache.sv:16] INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter NumPorts bound to: 32'b00000000000000000000000000000011 Parameter RdAmoTxId bound to: 2'b01 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter RdTxId bound to: 2'b01 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_dcache_ctrl.sv:114] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/core/cache_subsystem/wt_dcache_ctrl.sv:114] INFO: [Synth 8-6155] done synthesizing module 'wt_dcache_ctrl' (47#1) [/home/darshak/cva6/core/cache_subsystem/wt_dcache_ctrl.sv:16] Parameter AxiCompliant bound to: 1'b1 Parameter AmoTxId bound to: 2'b01 Parameter NumPorts bound to: 32'b00000000000000000000000000000011 Parameter AxiDataWidth bound to: 32'sb00000000000000000000000001000000 Parameter WIDTH bound to: 32'b00000000000000000000000000000011 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized2' (47#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] Parameter WIDTH bound to: 32'b00000000000000000000000000001000 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000011 INFO: [Synth 8-6155] done synthesizing module 'lzc__parameterized3' (47#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lzc.sv:25] Parameter LfsrWidth bound to: 32'b00000000000000000000000000001000 Parameter OutWidth bound to: 32'b00000000000000000000000000000011 Parameter RstVal bound to: 8'b11111111 Parameter CipherLayers bound to: 32'b00000000000000000000000000000000 Parameter CipherReg bound to: 1'b1 Parameter Masks bound to: 3904'b0000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000001111000000000000000000000000000000000000000000000000000000000001110010000000000000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000000000000001111101000000000000000000000000000000000000000000000000000000001111111010000000000000000000000000000000000000000000000000000001111111100000000000000000000000000000000000000000000000000000001100100101100000000000000000000000000000000000000000000000000001101100011110000000000000000000000000000000000000000000000000001001010010110000000000000000000000000000000000000000000000000001001001001011000000000000000000000000000000000000000000000000001000011010101110000000000000000000000000000000000000000000000001000011001111001000000000000000000000000000000000000000000000001000000110000111000000000000000000000000000000000000000000000001000000110110011010000000000000000000000000000000000000000000001000000001111111110000000000000000000000000000000000000000000001000000001111011100000000000000000000000000000000000000000000001000000000100101100100000000000000000000000000000000000000000001000000000011010101000000000000000000000000000000000000000000001000000000001001011001000000000000000000000000000000000000000001000000000001011100001110000000000000000000000000000000000000001000000000000010011110011000000000000000000000000000000000000001000000000000001110010110100000000000000000000000000000000000001000000000000000110101011100000000000000000000000000000000000001000000000000000100111100011000000000000000000000000000000000001000000000000000001011000001100000000000000000000000000000000001000000000000000001100100100100000000000000000000000000000000001000000000000000000010110110110000000000000000000000000000000001000000000000000000011101010011000000000000000000000000000000001000000000000000000000111101000110000000000000000000000000000001000000000000000000000101010111111000000000000000000000000000001000000000000000000000010000100001000000000000000000000000000001000000000000000000000010010001111100000000000000000000000000001000000000000000000000000011101001110000000000000000000000000001000000000000000000000000010101110100100000000000000000000000001000000000000000000000000001000011010100000000000000000000000001000000000000000000000000001001000010011000000000000000000000001000000000000000000000000000001110111111000000000000000000000001000000000000000000000000000010010001110110000000000000000000001000000000000000000000000000000100001110111000000000000000000001000000000000000000000000000000100001000110100000000000000000001000000000000000000000000000000001010111010010000000000000000001000000000000000000000000000000000111010011111000000000000000001000000000000000000000000000000000010001010011000000000000000001000000000000000000000000000000000011001000111100000000000000001000000000000000000000000000000000000100100001110000000000000001000000000000000000000000000000000000011111011001100000000000001000000000000000000000000000000000000001101011111010000000000001000000000000000000000000000000000000001011010100101000000000001000000000000000000000000000000000000000010110100101100000000001000000000000000000000000000000000000000010000101011110000000001000000000000000000000000000000000000000000110111011110000000001000000000000000000000000000000000000000000110000001101000000001000000000000000000000000000000000000000000001011011001010000001000000000000000000000000000000000000000000001000000101101000001000000000000000000000000000000000000000000000011001101010100001000000000000000000000000000000000000000000000100100110000010001000000000000000000000000000000000000000000000000111011110110001000000000000000000000000000000000000000000000000100110110001101000000000000000000000000000000000000000000000000001111110011011000000000000000000000000000000000000000000000000001100111100010 Parameter Sbox4 bound to: 64'b0010000101110100100011111110001111011010000010011011011001011100 Parameter Perm bound to: 384'b111111101111011111001111111110101110011110001110111101101101011101001101111100101100011100001100111011101011011011001011111010101010011010001010111001101001011001001001111000101000011000001000110111100111010111000111110110100110010110000110110101100101010101000101110100100100010100000100110011100011010011000011110010100010010010000010110001100001010001000001110000100000010000000000 INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized0' (47#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/lfsr.sv:22] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/wt_cache_pkg.sv:398] Parameter Seed bound to: 32'b00000000000000000000000000000011 Parameter MaxExp bound to: 32'b00000000000000000000000000010000 Parameter WIDTH bound to: 32'b00000000000000000000000000010000 WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/exp_backoff.sv:59] INFO: [Synth 8-6155] done synthesizing module 'exp_backoff' (48#1) [/home/darshak/cva6/vendor/pulp-platform/common_cells/src/exp_backoff.sv:23] INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_dcache_missunit.sv:297] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_dcache_missunit.sv:397] Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000001000 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000011 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/wt_cache_pkg.sv:364] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/wt_cache_pkg.sv:334] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/wt_cache_pkg.sv:304] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000000010 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 Parameter NumIn bound to: 32'b00000000000000000000000000000100 Parameter DataWidth bound to: 32'b00000000000000000000000000000001 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b0 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000010 Parameter NumIn bound to: 32'b00000000000000000000000000001000 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b0 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000011 Parameter NumIn bound to: 32'b00000000000000000000000000001000 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b0 Parameter LockIn bound to: 1'b0 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000011 Parameter AxiCompliant bound to: 1'b1 Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter NumPorts bound to: 32'b00000000000000000000000000000011 Parameter AXI_OFFSET_WIDTH bound to: 4 - type: integer Parameter DATA_WIDTH bound to: 512 - type: integer Parameter USER_WIDTH bound to: 512 - type: integer Parameter USER_EN bound to: 0 - type: integer Parameter NUM_WORDS bound to: 256 - type: integer Parameter SIM_INIT bound to: none - type: string Parameter OUT_REGS bound to: 0 - type: integer Parameter DATA_WIDTH_ALIGNED bound to: 512 - type: integer Parameter USER_WIDTH_ALIGNED bound to: 512 - type: integer Parameter BE_WIDTH_ALIGNED bound to: 64 - type: integer Parameter NumIn bound to: 32'b00000000000000000000000000000011 Parameter DataWidth bound to: 32'b00000000000000000000000000000001 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b0 Parameter LockIn bound to: 1'b0 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000010 Parameter ReqFifoDepth bound to: 32'b00000000000000000000000000000010 Parameter MetaFifoDepth bound to: 32'b00000000000000000000000000000100 Parameter AxiAddrWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter AxiNumWords bound to: 2 - type: integer Parameter NumIn bound to: 32'b00000000000000000000000000000010 Parameter DataWidth bound to: 32'b00000000000000000000000000000001 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000001 WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv:149] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv:151] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv:184] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv:193] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv:210] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/cache_subsystem/wt_axi_adapter.sv:220] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000000010 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 Parameter FALL_THROUGH bound to: 1'b1 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000000101 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 Parameter AxiUserWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiNumWords bound to: 2 - type: integer Parameter AxiAddrWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiDataWidth bound to: 32'b00000000000000000000000001000000 Parameter AxiIdWidth bound to: 32'b00000000000000000000000000000100 Parameter AddrIndex bound to: 1 - type: integer Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter DEPTH bound to: 2 - type: integer Parameter NR_ENTRIES bound to: 32 - type: integer Parameter OFFSET bound to: 1 - type: integer Parameter NR_ROWS bound to: 16 - type: integer Parameter ROW_ADDR_BITS bound to: 1 - type: integer Parameter ROW_INDEX_BITS bound to: 1 - type: integer Parameter PREDICTION_BITS bound to: 6 - type: integer Parameter ANTIALIAS_BITS bound to: 8 - type: integer Parameter BRAM_WORD_BITS bound to: 65 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/btb.sv:54] Parameter NR_ENTRIES bound to: 128 - type: integer Parameter OFFSET bound to: 1 - type: integer Parameter NR_ROWS bound to: 64 - type: integer Parameter ROW_ADDR_BITS bound to: 1 - type: integer Parameter ROW_INDEX_BITS bound to: 1 - type: integer Parameter PREDICTION_BITS bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/bht.sv:43] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/frontend/frontend.sv:180] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/frontend/frontend.sv:180] Parameter WIDTH bound to: 32'b00000000000000000000000000000010 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000001 Parameter INPUT_WIDTH bound to: 32'b00000000000000000000000000000010 Parameter PopcountWidth bound to: 32'b00000000000000000000000000000010 Parameter PaddedWidth bound to: 32'b00000000000000000000000000000010 WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/frontend/instr_queue.sv:280] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/frontend/instr_queue.sv:280] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter DEPTH bound to: 32'b00000000000000000000000000000100 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000010 Parameter FifoDepth bound to: 32'b00000000000000000000000000000100 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/instr_queue.sv:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/instr_queue.sv:392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/instr_queue.sv:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/instr_queue.sv:394] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/core/frontend/instr_queue.sv:395] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/compressed_decoder.sv:41] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/compressed_decoder.sv:44] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/compressed_decoder.sv:106] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/compressed_decoder.sv:149] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/compressed_decoder.sv:163] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/compressed_decoder.sv:220] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/core/compressed_decoder.sv:220] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:99] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:488] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:513] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:559] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:574] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:600] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:626] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:676] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:694] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:729] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:745] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:768] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:791] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:822] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:830] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/core/decoder.sv:830] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:841] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:846] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:853] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:874] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:922] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:977] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/core/decoder.sv:977] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:988] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:993] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:1000] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:1025] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/decoder.sv:1044] Parameter NR_ENTRIES bound to: 32'b00000000000000000000000000001000 Parameter NR_WB_PORTS bound to: 32'b00000000000000000000000000000101 Parameter NR_COMMIT_PORTS bound to: 32'b00000000000000000000000000000010 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:619] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:590] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:607] Parameter NR_ENTRIES bound to: 32'b00000000000000000000000000001000 Parameter NR_WB_PORTS bound to: 32'b00000000000000000000000000000101 Parameter NR_COMMIT_PORTS bound to: 32'b00000000000000000000000000000010 Parameter BITS_ENTRIES bound to: 32'b00000000000000000000000000000011 Parameter NumIn bound to: 32'b00000000000000000000000000001001 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b1 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b0 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000100 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:590] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:607] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:590] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:607] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:590] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:607] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:590] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:607] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:590] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:607] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/home/darshak/cva6/core/include/ariane_pkg.sv:573] INFO: [Common 17-14] Message 'Synth 8-294' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Parameter NumIn bound to: 32'b00000000000000000000000000001101 Parameter DataWidth bound to: 32'b00000000000000000000000001000000 Parameter ExtPrio bound to: 1'b1 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b0 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000100 Parameter NR_COMMIT_PORTS bound to: 32'b00000000000000000000000000000010 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter NR_READ_PORTS bound to: 32'b00000000000000000000000000000010 Parameter NR_WRITE_PORTS bound to: 32'b00000000000000000000000000000010 Parameter ZERO_REG_ZERO bound to: 1'b1 Parameter ADDR_WIDTH bound to: 5 - type: integer Parameter NUM_WORDS bound to: 32 - type: integer Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter NR_READ_PORTS bound to: 32'b00000000000000000000000000000011 Parameter NR_WRITE_PORTS bound to: 32'b00000000000000000000000000000010 Parameter ZERO_REG_ZERO bound to: 1'b0 Parameter ADDR_WIDTH bound to: 5 - type: integer Parameter NUM_WORDS bound to: 32 - type: integer WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/issue_read_operands.sv:222] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/issue_read_operands.sv:237] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/issue_read_operands.sv:242] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/issue_read_operands.sv:496] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/issue_read_operands.sv:497] Parameter ASID_WIDTH bound to: 32'b00000000000000000000000000010000 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/core/fpu_wrap.sv:428] Parameter Features[Width] bound to: 64 - type: integer Parameter Features[EnableVectors] bound to: 1'b0 Parameter Features[EnableNanBox] bound to: 1'b1 Parameter Features[FpFmtMask] bound to: 5'b11000 Parameter Features[IntFmtMask] bound to: 4'b0011 Parameter Implementation[PipeRegs][0][0] bound to: 2 - type: integer Parameter Implementation[PipeRegs][0][1] bound to: 3 - type: integer Parameter Implementation[PipeRegs][0][2] bound to: 1 - type: integer Parameter Implementation[PipeRegs][0][3] bound to: 1 - type: integer Parameter Implementation[PipeRegs][0][4] bound to: 1 - type: integer Parameter Implementation[PipeRegs][1][0] bound to: 2 - type: integer Parameter Implementation[PipeRegs][1][1] bound to: 2 - type: integer Parameter Implementation[PipeRegs][1][2] bound to: 2 - type: integer Parameter Implementation[PipeRegs][1][3] bound to: 2 - type: integer Parameter Implementation[PipeRegs][1][4] bound to: 2 - type: integer Parameter Implementation[PipeRegs][2][0] bound to: 1 - type: integer Parameter Implementation[PipeRegs][2][1] bound to: 1 - type: integer Parameter Implementation[PipeRegs][2][2] bound to: 1 - type: integer Parameter Implementation[PipeRegs][2][3] bound to: 1 - type: integer Parameter Implementation[PipeRegs][2][4] bound to: 1 - type: integer Parameter Implementation[PipeRegs][3][0] bound to: 2 - type: integer Parameter Implementation[PipeRegs][3][1] bound to: 2 - type: integer Parameter Implementation[PipeRegs][3][2] bound to: 2 - type: integer Parameter Implementation[PipeRegs][3][3] bound to: 2 - type: integer Parameter Implementation[PipeRegs][3][4] bound to: 2 - type: integer Parameter Implementation[UnitTypes][0][0] bound to: 2'b01 Parameter Implementation[UnitTypes][0][1] bound to: 2'b01 Parameter Implementation[UnitTypes][0][2] bound to: 2'b01 Parameter Implementation[UnitTypes][0][3] bound to: 2'b01 Parameter Implementation[UnitTypes][0][4] bound to: 2'b01 Parameter Implementation[UnitTypes][1][0] bound to: 2'b10 Parameter Implementation[UnitTypes][1][1] bound to: 2'b10 Parameter Implementation[UnitTypes][1][2] bound to: 2'b10 Parameter Implementation[UnitTypes][1][3] bound to: 2'b10 Parameter Implementation[UnitTypes][1][4] bound to: 2'b10 Parameter Implementation[UnitTypes][2][0] bound to: 2'b01 Parameter Implementation[UnitTypes][2][1] bound to: 2'b01 Parameter Implementation[UnitTypes][2][2] bound to: 2'b01 Parameter Implementation[UnitTypes][2][3] bound to: 2'b01 Parameter Implementation[UnitTypes][2][4] bound to: 2'b01 Parameter Implementation[UnitTypes][3][0] bound to: 2'b10 Parameter Implementation[UnitTypes][3][1] bound to: 2'b10 Parameter Implementation[UnitTypes][3][2] bound to: 2'b10 Parameter Implementation[UnitTypes][3][3] bound to: 2'b10 Parameter Implementation[UnitTypes][3][4] bound to: 2'b10 Parameter Implementation[PipeConfig] bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter EnableSIMDMask bound to: 32'b00000000000000000000000000000000 Parameter NumLanes bound to: 32'b00000000000000000000000000000001 Parameter WIDTH bound to: 64 - type: integer Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000011 Parameter NUM_OPGROUPS bound to: 32'b00000000000000000000000000000100 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter OpGroup bound to: 2'b00 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter FpFmtMask bound to: 5'b11000 Parameter IntFmtMask bound to: 4'b0011 Parameter FmtPipeRegs bound to: 160'b0000000000000000000000000000001000000000000000000000000000000011000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001 Parameter FmtUnitTypes bound to: 10'b0101010101 Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000011 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter OpGroup bound to: 2'b00 Parameter FpFormat bound to: 3'b000 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter NumPipeRegs bound to: 2 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000011 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter FP_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SIMD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter CLASS_VEC_BITS bound to: 32'b00000000000000000000000000001000 Parameter FpFormat bound to: 3'b000 Parameter NumPipeRegs bound to: 2 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter EXP_BITS bound to: 8 - type: integer Parameter MAN_BITS bound to: 23 - type: integer Parameter BIAS bound to: 32'b00000000000000000000000001111111 Parameter PRECISION_BITS bound to: 32'b00000000000000000000000000011000 Parameter LOWER_SUM_WIDTH bound to: 32'b00000000000000000000000000110011 Parameter LZC_RESULT_WIDTH bound to: 32'b00000000000000000000000000000110 Parameter EXP_WIDTH bound to: 32'b00000000000000000000000000001010 Parameter SHIFT_AMOUNT_WIDTH bound to: 32'b00000000000000000000000000000111 Parameter NUM_INP_REGS bound to: 1 - type: integer Parameter NUM_MID_REGS bound to: 1 - type: integer Parameter NUM_OUT_REGS bound to: 0 - type: integer Parameter FpFormat bound to: 3'b000 Parameter NumOperands bound to: 32'b00000000000000000000000000000011 Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter EXP_BITS bound to: 8 - type: integer Parameter MAN_BITS bound to: 23 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000110011 Parameter MODE bound to: 1'b1 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000110 Parameter AbsWidth bound to: 32'b00000000000000000000000000011111 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv:48] Parameter OpGroup bound to: 2'b00 Parameter FpFormat bound to: 3'b001 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter NumPipeRegs bound to: 3 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000011 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter FP_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter SIMD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter CLASS_VEC_BITS bound to: 32'b00000000000000000000000000001000 Parameter FpFormat bound to: 3'b001 Parameter NumPipeRegs bound to: 3 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter EXP_BITS bound to: 11 - type: integer Parameter MAN_BITS bound to: 52 - type: integer Parameter BIAS bound to: 32'b00000000000000000000001111111111 Parameter PRECISION_BITS bound to: 32'b00000000000000000000000000110101 Parameter LOWER_SUM_WIDTH bound to: 32'b00000000000000000000000001101101 Parameter LZC_RESULT_WIDTH bound to: 32'b00000000000000000000000000000111 Parameter EXP_WIDTH bound to: 32'b00000000000000000000000000001101 Parameter SHIFT_AMOUNT_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter NUM_INP_REGS bound to: 1 - type: integer Parameter NUM_MID_REGS bound to: 1 - type: integer Parameter NUM_OUT_REGS bound to: 1 - type: integer Parameter FpFormat bound to: 3'b001 Parameter NumOperands bound to: 32'b00000000000000000000000000000011 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter EXP_BITS bound to: 11 - type: integer Parameter MAN_BITS bound to: 52 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000001101101 Parameter MODE bound to: 1'b1 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000111 Parameter AbsWidth bound to: 32'b00000000000000000000000000111111 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv:48] Parameter NumIn bound to: 32'b00000000000000000000000000000101 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b0 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000011 Parameter WIDTH bound to: 32'b00000000000000000000000000000101 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000011 Parameter OpGroup bound to: 2'b01 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter FpFmtMask bound to: 5'b11000 Parameter IntFmtMask bound to: 4'b0011 Parameter FmtPipeRegs bound to: 160'b0000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010 Parameter FmtUnitTypes bound to: 10'b1010101010 Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000010 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter OpGroup bound to: 2'b01 Parameter Width bound to: 64 - type: integer Parameter FpFmtConfig bound to: 5'b11000 Parameter IntFmtConfig bound to: 4'b0011 Parameter EnableVectors bound to: 1'b0 Parameter NumPipeRegs bound to: 2 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000010 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_SIMD_LANES bound to: 32'b00000000000000000000000000000001 Parameter MAX_FP_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter MAX_INT_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000010 Parameter NUM_INT_FORMATS bound to: 32'b00000000000000000000000000000100 Parameter FMT_BITS bound to: 32'b00000000000000000000000000000011 Parameter AUX_BITS bound to: 32'b00000000000000000000000000000101 Parameter FpFmtConfig bound to: 5'b11000 Parameter NumPipeRegs bound to: 2 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_INP_REGS bound to: 1 - type: integer Parameter NUM_OUT_REGS bound to: 1 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000000110101 Parameter MODE bound to: 1'b1 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000110 Parameter WIDTH bound to: 58 - type: integer Parameter OpGroup bound to: 2'b10 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter FpFmtMask bound to: 5'b11000 Parameter IntFmtMask bound to: 4'b0011 Parameter FmtPipeRegs bound to: 160'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001 Parameter FmtUnitTypes bound to: 10'b0101010101 Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000010 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter OpGroup bound to: 2'b10 Parameter FpFormat bound to: 3'b000 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter NumPipeRegs bound to: 1 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000010 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter FP_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter SIMD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter CLASS_VEC_BITS bound to: 32'b00000000000000000000000000001000 Parameter FpFormat bound to: 3'b000 Parameter NumPipeRegs bound to: 1 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter EXP_BITS bound to: 8 - type: integer Parameter MAN_BITS bound to: 23 - type: integer Parameter NUM_INP_REGS bound to: 1 - type: integer Parameter NUM_OUT_REGS bound to: 0 - type: integer Parameter FpFormat bound to: 3'b000 Parameter NumOperands bound to: 32'b00000000000000000000000000000010 Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter EXP_BITS bound to: 8 - type: integer Parameter MAN_BITS bound to: 23 - type: integer Parameter OpGroup bound to: 2'b10 Parameter FpFormat bound to: 3'b001 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter NumPipeRegs bound to: 1 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000010 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter FP_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter SIMD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter CLASS_VEC_BITS bound to: 32'b00000000000000000000000000001000 Parameter FpFormat bound to: 3'b001 Parameter NumPipeRegs bound to: 1 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter EXP_BITS bound to: 11 - type: integer Parameter MAN_BITS bound to: 52 - type: integer Parameter NUM_INP_REGS bound to: 1 - type: integer Parameter NUM_OUT_REGS bound to: 0 - type: integer Parameter FpFormat bound to: 3'b001 Parameter NumOperands bound to: 32'b00000000000000000000000000000010 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter EXP_BITS bound to: 11 - type: integer Parameter MAN_BITS bound to: 52 - type: integer Parameter OpGroup bound to: 2'b11 Parameter Width bound to: 64 - type: integer Parameter EnableVectors bound to: 1'b0 Parameter FpFmtMask bound to: 5'b11000 Parameter IntFmtMask bound to: 4'b0011 Parameter FmtPipeRegs bound to: 160'b0000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010 Parameter FmtUnitTypes bound to: 10'b1010101010 Parameter PipeConfig bound to: 2'b11 Parameter TrueSIMDClass bound to: 32'b00000000000000000000000000000000 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000011 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000001 Parameter OpGroup bound to: 2'b11 Parameter Width bound to: 64 - type: integer Parameter FpFmtConfig bound to: 5'b11000 Parameter IntFmtConfig bound to: 4'b0011 Parameter EnableVectors bound to: 1'b0 Parameter NumPipeRegs bound to: 2 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter NUM_OPERANDS bound to: 32'b00000000000000000000000000000011 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_SIMD_LANES bound to: 32'b00000000000000000000000000000001 Parameter MAX_FP_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter MAX_INT_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter NUM_LANES bound to: 32'b00000000000000000000000000000010 Parameter NUM_INT_FORMATS bound to: 32'b00000000000000000000000000000100 Parameter FMT_BITS bound to: 32'b00000000000000000000000000000011 Parameter AUX_BITS bound to: 32'b00000000000000000000000000000101 Parameter FpFmtConfig bound to: 5'b11000 Parameter IntFmtConfig bound to: 4'b0011 Parameter NumPipeRegs bound to: 2 - type: integer Parameter PipeConfig bound to: 2'b11 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter NUM_FORMATS bound to: 32'b00000000000000000000000000000101 Parameter NUM_INT_FORMATS bound to: 32'b00000000000000000000000000000100 Parameter MAX_INT_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter SUPER_FORMAT[exp_bits] bound to: 11 - type: integer Parameter SUPER_FORMAT[man_bits] bound to: 52 - type: integer Parameter SUPER_EXP_BITS bound to: 11 - type: integer Parameter SUPER_MAN_BITS bound to: 52 - type: integer Parameter SUPER_BIAS bound to: 32'b00000000000000000000001111111111 Parameter INT_MAN_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter LZC_RESULT_WIDTH bound to: 32'b00000000000000000000000000000110 Parameter INT_EXP_WIDTH bound to: 32'b00000000000000000000000000001100 Parameter NUM_INP_REGS bound to: 1 - type: integer Parameter NUM_MID_REGS bound to: 1 - type: integer Parameter NUM_OUT_REGS bound to: 0 - type: integer Parameter NUM_FP_STICKY bound to: 75 - type: integer Parameter NUM_INT_STICKY bound to: 64 - type: integer Parameter FpFormat bound to: 3'b000 Parameter NumOperands bound to: 32'b00000000000000000000000000000001 Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter EXP_BITS bound to: 8 - type: integer Parameter MAN_BITS bound to: 23 - type: integer Parameter FpFormat bound to: 3'b001 Parameter NumOperands bound to: 32'b00000000000000000000000000000001 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter EXP_BITS bound to: 11 - type: integer Parameter MAN_BITS bound to: 52 - type: integer Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter MODE bound to: 1'b1 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000110 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv:89] Parameter AbsWidth bound to: 32'b00000000000000000000000001000000 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv:48] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_pkg.sv:89] Parameter NumIn bound to: 32'b00000000000000000000000000000100 Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b0 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000010 Parameter INPUT_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter PopcountWidth bound to: 32'b00000000000000000000000000000111 Parameter PaddedWidth bound to: 32'b00000000000000000000000001000000 Parameter INPUT_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter PopcountWidth bound to: 32'b00000000000000000000000000000110 Parameter PaddedWidth bound to: 32'b00000000000000000000000000100000 Parameter INPUT_WIDTH bound to: 32'b00000000000000000000000000010000 Parameter PopcountWidth bound to: 32'b00000000000000000000000000000101 Parameter PaddedWidth bound to: 32'b00000000000000000000000000010000 Parameter INPUT_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter PopcountWidth bound to: 32'b00000000000000000000000000000100 Parameter PaddedWidth bound to: 32'b00000000000000000000000000001000 Parameter INPUT_WIDTH bound to: 32'b00000000000000000000000000000100 Parameter PopcountWidth bound to: 32'b00000000000000000000000000000011 Parameter PaddedWidth bound to: 32'b00000000000000000000000000000100 Parameter WIDTH bound to: 32'b00000000000000000000000001000000 Parameter MODE bound to: 1'b1 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000110 Parameter WIDTH bound to: 32'b00000000000000000000000000100000 Parameter MODE bound to: 1'b1 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000101 WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/branch_unit.sv:90] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/ex_stage.sv:216] Parameter WIDTH bound to: 64 - type: integer Parameter ASID_WIDTH bound to: 32'b00000000000000000000000000010000 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter INSTR_TLB_ENTRIES bound to: 32'b00000000000000000000000000010000 Parameter DATA_TLB_ENTRIES bound to: 32'b00000000000000000000000000010000 Parameter ASID_WIDTH bound to: 32'b00000000000000000000000000010000 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter PPNWMin bound to: 29 - type: integer Parameter TLB_ENTRIES bound to: 32'b00000000000000000000000000010000 Parameter ASID_WIDTH bound to: 32'b00000000000000000000000000010000 Parameter ASID_WIDTH bound to: 32'sb00000000000000000000000000010000 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/ptw.sv:120] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/ptw.sv:121] Parameter PLEN bound to: 32'b00000000000000000000000000111000 Parameter PMP_LEN bound to: 32'b00000000000000000000000000110110 Parameter NR_ENTRIES bound to: 8 - type: integer Parameter PLEN bound to: 32'b00000000000000000000000000111000 Parameter PMP_LEN bound to: 32'b00000000000000000000000000110110 Parameter WIDTH bound to: 32'b00000000000000000000000000111000 Parameter MODE bound to: 1'b0 Parameter CNT_WIDTH bound to: 32'b00000000000000000000000000000110 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/core/pmp/src/pmp_entry.sv:40] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:221] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:246] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:257] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:363] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:373] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:392] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:394] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:403] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/mmu_sv39/mmu.sv:405] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/amo_buffer.sv:52] Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter DEPTH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000001 Parameter ArianeCfg[RASDepth] bound to: 2 - type: integer Parameter ArianeCfg[BTBEntries] bound to: 32 - type: integer Parameter ArianeCfg[BHTEntries] bound to: 128 - type: integer Parameter ArianeCfg[NrNonIdempotentRules] bound to: 1 - type: integer Parameter ArianeCfg[NonIdempotentAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NonIdempotentLength][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[NrExecuteRegionRules] bound to: 3 - type: integer Parameter ArianeCfg[ExecuteRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][2] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[ExecuteRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000010000000000000000 Parameter ArianeCfg[ExecuteRegionLength][0] bound to: 64'b0000000000000000000000000000000000000000000000000001000000000000 Parameter ArianeCfg[NrCachedRegionRules] bound to: 1 - type: integer Parameter ArianeCfg[CachedRegionAddrBase][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionAddrBase][0] bound to: 64'b0000000000000000000000000000000010000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][15] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][14] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][13] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][12] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][11] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][10] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][9] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][8] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][7] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][6] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][5] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][4] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][3] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][2] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][1] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[CachedRegionLength][0] bound to: 64'b0000000000000000000000000000000001000000000000000000000000000000 Parameter ArianeCfg[AxiCompliant] bound to: 1'b1 Parameter ArianeCfg[SwapEndianess] bound to: 1'b0 Parameter ArianeCfg[DmBaseAddress] bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ArianeCfg[NrPMPEntries] bound to: 8 - type: integer Parameter Depth bound to: 32'b00000000000000000000000000000001 Parameter Depth bound to: 32'b00000000000000000000000000000000 WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/load_store_unit.sv:433] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/load_store_unit.sv:440] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/load_store_unit.sv:451] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/load_store_unit.sv:458] Parameter NR_COMMIT_PORTS bound to: 32'b00000000000000000000000000000010 Parameter DmBaseAddress bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter AsidWidth bound to: 32'sb00000000000000000000000000010000 Parameter NrCommitPorts bound to: 32'b00000000000000000000000000000010 Parameter NrPMPEntries bound to: 8 - type: integer Parameter MHPMCounterNum bound to: 32'b00000000000000000000000000000110 WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:505] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:601] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:601] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:636] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:647] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:902] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:921] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:970] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:978] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:993] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:996] WARNING: [Synth 8-693] zero replication count - replication ignored [/home/darshak/cva6/core/csr_regfile.sv:1002] Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter NR_CORES bound to: 32'b00000000000000000000000000000001 Parameter MSIP_BASE bound to: 16'b0000000000000000 Parameter MTIMECMP_BASE bound to: 16'b0100000000000000 Parameter MTIME_BASE bound to: 16'b1011111111111000 Parameter AddrSelWidth bound to: 1 - type: integer Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/clint/axi_lite_interface.sv:78] Parameter STAGES bound to: 32'b00000000000000000000000000000010 Parameter STAGES bound to: 32'b00000000000000000000000000000010 Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter LOG_NR_BYTES bound to: 3 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:192] INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:234] INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/axi_mem_if/src/axi2mem.sv:122] Parameter AxiAddrWidth bound to: 64 - type: integer Parameter AxiDataWidth bound to: 64 - type: integer Parameter AxiIdWidth bound to: 5 - type: integer Parameter AxiUserWidth bound to: 64 - type: integer Parameter InclUART bound to: 1'b1 Parameter InclSPI bound to: 1'b1 Parameter InclEthernet bound to: 1'b1 Parameter InclGPIO bound to: 1'b1 Parameter InclTimer bound to: 1'b1 INFO: [Synth 8-638] synthesizing module 'apb_uart' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:66] INFO: [Synth 8-3491] module 'slib_input_sync' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:28' bound to instance 'UART_IS_SIN' of component 'slib_input_sync' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:396] INFO: [Synth 8-638] synthesizing module 'slib_input_sync' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:37] INFO: [Synth 8-256] done synthesizing module 'slib_input_sync' (119#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:37] INFO: [Synth 8-3491] module 'slib_input_sync' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:28' bound to instance 'UART_IS_CTS' of component 'slib_input_sync' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:397] INFO: [Synth 8-3491] module 'slib_input_sync' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:28' bound to instance 'UART_IS_DSR' of component 'slib_input_sync' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:398] INFO: [Synth 8-3491] module 'slib_input_sync' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:28' bound to instance 'UART_IS_DCD' of component 'slib_input_sync' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:399] INFO: [Synth 8-3491] module 'slib_input_sync' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd:28' bound to instance 'UART_IS_RI' of component 'slib_input_sync' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:400] Parameter SIZE bound to: 2 - type: integer INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:28' bound to instance 'UART_IF_CTS' of component 'slib_input_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:403] INFO: [Synth 8-638] synthesizing module 'slib_input_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:41] Parameter SIZE bound to: 2 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_input_filter' (120#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:41] Parameter SIZE bound to: 2 - type: integer INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:28' bound to instance 'UART_IF_DSR' of component 'slib_input_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:404] Parameter SIZE bound to: 2 - type: integer INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:28' bound to instance 'UART_IF_DCD' of component 'slib_input_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:405] Parameter SIZE bound to: 2 - type: integer INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:28' bound to instance 'UART_IF_RI' of component 'slib_input_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:406] INFO: [Synth 8-3491] module 'uart_interrupt' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_interrupt.vhd:33' bound to instance 'UART_IIC' of component 'uart_interrupt' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:444] INFO: [Synth 8-638] synthesizing module 'uart_interrupt' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_interrupt.vhd:49] INFO: [Synth 8-256] done synthesizing module 'uart_interrupt' (121#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_interrupt.vhd:49] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_IIC_THRE_ED' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:457] INFO: [Synth 8-638] synthesizing module 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:38] INFO: [Synth 8-256] done synthesizing module 'slib_edge_detect' (122#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:38] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_PEDET' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:657] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_FEDET' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:658] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_BIDET' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:659] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_ED_CTS' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:683] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_ED_DSR' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:684] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_ED_RI' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:685] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_ED_DCD' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:686] INFO: [Synth 8-3491] module 'uart_baudgen' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_baudgen.vhd:29' bound to instance 'UART_BG16' of component 'uart_baudgen' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:747] INFO: [Synth 8-638] synthesizing module 'uart_baudgen' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_baudgen.vhd:40] INFO: [Synth 8-256] done synthesizing module 'uart_baudgen' (123#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_baudgen.vhd:40] Parameter RATIO bound to: 8 - type: integer INFO: [Synth 8-3491] module 'slib_clock_div' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_clock_div.vhd:29' bound to instance 'UART_BG2' of component 'slib_clock_div' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:754] INFO: [Synth 8-638] synthesizing module 'slib_clock_div' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_clock_div.vhd:41] Parameter RATIO bound to: 8 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_clock_div' (124#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_clock_div.vhd:41] INFO: [Synth 8-3491] module 'slib_edge_detect' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd:28' bound to instance 'UART_RCLK' of component 'slib_edge_detect' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:760] Parameter WIDTH bound to: 8 - type: integer Parameter SIZE_E bound to: 6 - type: integer INFO: [Synth 8-3491] module 'slib_fifo' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd:29' bound to instance 'UART_TXFF' of component 'slib_fifo' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:767] INFO: [Synth 8-638] synthesizing module 'slib_fifo' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd:48] Parameter WIDTH bound to: 8 - type: integer Parameter SIZE_E bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_fifo' (125#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd:48] Parameter WIDTH bound to: 11 - type: integer Parameter SIZE_E bound to: 6 - type: integer INFO: [Synth 8-3491] module 'slib_fifo' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd:29' bound to instance 'UART_RXFF' of component 'slib_fifo' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:786] INFO: [Synth 8-638] synthesizing module 'slib_fifo__parameterized1' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd:48] Parameter WIDTH bound to: 11 - type: integer Parameter SIZE_E bound to: 6 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_fifo__parameterized1' (125#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd:48] INFO: [Synth 8-3491] module 'uart_transmitter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_transmitter.vhd:29' bound to instance 'UART_TX' of component 'uart_transmitter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:822] INFO: [Synth 8-638] synthesizing module 'uart_transmitter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_transmitter.vhd:48] INFO: [Synth 8-256] done synthesizing module 'uart_transmitter' (126#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_transmitter.vhd:48] INFO: [Synth 8-3491] module 'uart_receiver' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd:29' bound to instance 'UART_RX' of component 'uart_receiver' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:840] INFO: [Synth 8-638] synthesizing module 'uart_receiver' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd:49] Parameter WIDTH bound to: 4 - type: integer INFO: [Synth 8-3491] module 'slib_counter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_counter.vhd:29' bound to instance 'RX_BRC' of component 'slib_counter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd:122] INFO: [Synth 8-638] synthesizing module 'slib_counter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_counter.vhd:46] Parameter WIDTH bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_counter' (127#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_counter.vhd:46] Parameter WIDTH bound to: 4 - type: integer Parameter THRESHOLD bound to: 10 - type: integer INFO: [Synth 8-3491] module 'slib_mv_filter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_mv_filter.vhd:29' bound to instance 'RX_MVF' of component 'slib_mv_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd:137] INFO: [Synth 8-638] synthesizing module 'slib_mv_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_mv_filter.vhd:44] Parameter WIDTH bound to: 4 - type: integer Parameter THRESHOLD bound to: 10 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_mv_filter' (128#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_mv_filter.vhd:44] Parameter SIZE bound to: 4 - type: integer INFO: [Synth 8-3491] module 'slib_input_filter' declared at '/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:28' bound to instance 'RX_IFSB' of component 'slib_input_filter' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd:150] INFO: [Synth 8-638] synthesizing module 'slib_input_filter__parameterized2' [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:41] Parameter SIZE bound to: 4 - type: integer INFO: [Synth 8-256] done synthesizing module 'slib_input_filter__parameterized2' (128#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd:41] INFO: [Synth 8-256] done synthesizing module 'uart_receiver' (129#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd:49] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:880] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:919] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:1006] INFO: [Synth 8-256] done synthesizing module 'apb_uart' (130#1) [/home/darshak/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd:66] Parameter dly bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 9'b000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SRVAL_A bound to: 9'b000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/darshak/cva6/corev_apu/fpga/src/ariane-ethernet/rgmii_soc.sv:86] Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter CINVCTRL_SEL bound to: FALSE - type: string Parameter DELAY_SRC bound to: IDATAIN - type: string Parameter HIGH_PERFORMANCE_MODE bound to: FALSE - type: string Parameter IDELAY_TYPE bound to: FIXED - type: string Parameter IDELAY_VALUE bound to: 0 - type: integer Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_DATAIN_INVERTED bound to: 1'b0 Parameter IS_IDATAIN_INVERTED bound to: 1'b0 Parameter PIPE_SEL bound to: FALSE - type: string Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: double Parameter SIGNAL_PATTERN bound to: DATA - type: string Parameter SIM_DELAY_D bound to: 0 - type: integer Parameter TARGET bound to: XILINX - type: string Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string Parameter USE_CLK90 bound to: TRUE - type: string Parameter ENABLE_PADDING bound to: 1 - type: integer Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer Parameter TX_FIFO_ADDR_WIDTH bound to: 12 - type: integer Parameter TX_FRAME_FIFO bound to: 1 - type: integer Parameter TX_DROP_BAD_FRAME bound to: 1 - type: integer Parameter TX_DROP_WHEN_FULL bound to: 0 - type: integer Parameter RX_FIFO_ADDR_WIDTH bound to: 12 - type: integer Parameter RX_FRAME_FIFO bound to: 1 - type: integer Parameter RX_DROP_BAD_FRAME bound to: 1 - type: integer Parameter RX_DROP_WHEN_FULL bound to: 1 - type: integer Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string Parameter USE_CLK90 bound to: TRUE - type: string Parameter ENABLE_PADDING bound to: 1 - type: integer Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string Parameter USE_CLK90 bound to: TRUE - type: string Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string Parameter WIDTH bound to: 5 - type: integer Parameter BUFR_DIVIDE bound to: BYPASS - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter WIDTH bound to: 5 - type: integer Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string Parameter INIT_Q1 bound to: 1'b0 Parameter INIT_Q2 bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter SRTYPE bound to: ASYNC - type: string Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter WIDTH bound to: 1 - type: integer Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D1_INVERTED bound to: 1'b0 Parameter IS_D2_INVERTED bound to: 1'b0 Parameter SRTYPE bound to: ASYNC - type: string Parameter TARGET bound to: XILINX - type: string Parameter IODDR_STYLE bound to: IODDR - type: string Parameter WIDTH bound to: 5 - type: integer Parameter ENABLE_PADDING bound to: 1 - type: integer Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer Parameter ETH_PRE bound to: 8'b01010101 Parameter ETH_SFD bound to: 8'b11010101 Parameter STATE_IDLE bound to: 3'b000 Parameter STATE_PAYLOAD bound to: 3'b001 Parameter STATE_WAIT_LAST bound to: 3'b010 Parameter STATE_CRC bound to: 3'b011 Parameter LFSR_WIDTH bound to: 32 - type: integer Parameter LFSR_POLY bound to: 79764919 - type: integer Parameter LFSR_CONFIG bound to: GALOIS - type: string Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer Parameter REVERSE bound to: 1 - type: integer Parameter DATA_WIDTH bound to: 8 - type: integer Parameter STYLE bound to: AUTO - type: string Parameter STYLE_INT bound to: LOOP - type: string Parameter ENABLE_PADDING bound to: 1 - type: integer Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer Parameter ETH_PRE bound to: 8'b01010101 Parameter ETH_SFD bound to: 8'b11010101 Parameter STATE_IDLE bound to: 3'b000 Parameter STATE_PREAMBLE bound to: 3'b001 Parameter STATE_PAYLOAD bound to: 3'b010 Parameter STATE_LAST bound to: 3'b011 Parameter STATE_PAD bound to: 3'b100 Parameter STATE_FCS bound to: 3'b101 Parameter STATE_WAIT_END bound to: 3'b110 Parameter STATE_IFG bound to: 3'b111 Parameter DRIVE bound to: 12 - type: integer Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string Parameter AXI4_ADDRESS_WIDTH bound to: 64 - type: integer Parameter AXI4_RDATA_WIDTH bound to: 64 - type: integer Parameter AXI4_WDATA_WIDTH bound to: 64 - type: integer Parameter AXI4_ID_WIDTH bound to: 5 - type: integer Parameter AXI4_USER_WIDTH bound to: 64 - type: integer Parameter AXI_NUMBYTES bound to: 32'b00000000000000000000000000001000 Parameter BUFF_DEPTH_SLAVE bound to: 32'b00000000000000000000000000000010 Parameter APB_NUM_SLAVES bound to: 32'b00000000000000000000000000001000 Parameter APB_ADDR_WIDTH bound to: 32'b00000000000000000000000000100000 Parameter ID_WIDTH bound to: 5 - type: integer Parameter ADDR_WIDTH bound to: 64 - type: integer Parameter USER_WIDTH bound to: 64 - type: integer Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000010100010 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010100010 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter THRESHOLD bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010100010 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ALM_EMPTY_TH bound to: 32'b00000000000000000000000000000001 Parameter ALM_FULL_TH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010100010 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 Parameter ID_WIDTH bound to: 5 - type: integer Parameter ADDR_WIDTH bound to: 64 - type: integer Parameter USER_WIDTH bound to: 64 - type: integer Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter DATA_WIDTH bound to: 64 - type: integer Parameter USER_WIDTH bound to: 64 - type: integer Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter STRB_WIDTH bound to: 32'sb00000000000000000000000000001000 Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000010001001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010001001 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter THRESHOLD bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010001001 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ALM_EMPTY_TH bound to: 32'b00000000000000000000000000000001 Parameter ALM_FULL_TH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010001001 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 Parameter ID_WIDTH bound to: 5 - type: integer Parameter DATA_WIDTH bound to: 64 - type: integer Parameter USER_WIDTH bound to: 64 - type: integer Parameter BUFFER_DEPTH bound to: 2 - type: integer Parameter STRB_WIDTH bound to: 8 - type: integer Parameter BUFFER_DEPTH bound to: 2 - type: integer Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000010001000 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010001000 Parameter DEPTH bound to: 2 - type: integer Parameter THRESHOLD bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010001000 Parameter DEPTH bound to: 2 - type: integer Parameter ALM_EMPTY_TH bound to: 32'b00000000000000000000000000000001 Parameter ALM_FULL_TH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000010001000 Parameter DEPTH bound to: 2 - type: integer Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 2 - type: integer Parameter ID_WIDTH bound to: 5 - type: integer Parameter USER_WIDTH bound to: 64 - type: integer Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter BUFFER_DEPTH bound to: 32'sb00000000000000000000000000000010 Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000001000111 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000111 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter THRESHOLD bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000111 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ALM_EMPTY_TH bound to: 32'b00000000000000000000000000000001 Parameter ALM_FULL_TH bound to: 32'b00000000000000000000000000000001 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FALL_THROUGH bound to: 1'b0 Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000111 Parameter DEPTH bound to: 32'b00000000000000000000000000000010 Parameter ADDR_DEPTH bound to: 32'b00000000000000000000000000000001 Parameter FifoDepth bound to: 32'b00000000000000000000000000000010 Parameter APB_ADDR_WIDTH bound to: 32 - type: integer Parameter TIMER_CNT bound to: 2 - type: integer Parameter APB_ADDR_WIDTH bound to: 32 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/src/apb_timer/timer.sv:92] INFO: [Synth 8-155] case statement is not full and has no default [/home/darshak/cva6/corev_apu/fpga/src/apb_timer/timer.sv:116] Parameter ADDR_WIDTH bound to: 32'sb00000000000000000000000000100000 Parameter DATA_WIDTH bound to: 32'sb00000000000000000000000000100000 Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 Parameter N_TARGET bound to: 32'sb00000000000000000000000000000010 Parameter MAX_PRIO bound to: 32'sb00000000000000000000000000000111 Parameter SRCW bound to: 32'sb00000000000000000000000000000101 Parameter PRIOW bound to: 3 - type: integer Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 Parameter MAX_PRIO bound to: 32'sb00000000000000000000000000000111 Parameter ALGORITHM bound to: SEQUENTIAL - type: string Parameter SRCW bound to: 32'b00000000000000000000000000000101 Parameter PRIOW bound to: 32'b00000000000000000000000000000011 Parameter N_SOURCE bound to: 32'sb00000000000000000000000000011110 Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 8 - type: integer Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_MAX_WRITE_TXNS bound to: 32'b00000000000000000000000000000001 Parameter RISCV_WORD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_STRB_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_MAX_WRITE_TXNS bound to: 32'b00000000000000000000000000000001 Parameter RISCV_WORD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_STRB_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter ADDR_BEGIN bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ADDR_END bound to: 64'b1111111111111111111111111111111111111111111111111111111111111111 Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_MAX_WRITE_TXNS bound to: 32'b00000000000000000000000000000001 Parameter RISCV_WORD_WIDTH bound to: 32'b00000000000000000000000001000000 Parameter AXI_STRB_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter OUTSTND_BURSTS_WIDTH bound to: 32'b00000000000000000000000000000001 Parameter AXI_ALU_RATIO bound to: 32'b00000000000000000000000000000001 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv:580] INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv:809] Parameter DATA_WIDTH bound to: 32'b00000000000000000000000001000000 INFO: [Synth 8-226] default block is never used [/home/darshak/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv:39] Parameter ADDR_BEGIN bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 Parameter ADDR_END bound to: 64'b1111111111111111111111111111111111111111111111111111111111111111 Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_DATA_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter AXI_USER_WIDTH bound to: 64 - type: integer Parameter AXI_STRB_WIDTH bound to: 32'b00000000000000000000000000001000 Parameter AXI_ADDR_WIDTH bound to: 64 - type: integer Parameter AXI_ID_WIDTH bound to: 5 - type: integer Parameter N_IDS bound to: 32 - type: integer Parameter N_INP bound to: 2 - type: integer Parameter ARBITER bound to: rr - type: string Parameter N_INP bound to: 2 - type: integer Parameter ARBITER bound to: rr - type: string Parameter NumIn bound to: 2 - type: integer Parameter DataWidth bound to: 32'b00000000000000000000000000100000 Parameter ExtPrio bound to: 1'b0 Parameter AxiVldRdy bound to: 1'b1 Parameter LockIn bound to: 1'b1 Parameter FairArb bound to: 1'b1 Parameter IdxWidth bound to: 32'b00000000000000000000000000000001 --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:54 ; elapsed = 00:00:59 . Memory (MB): peak = 2885.391 ; gain = 760.938 ; free physical = 13623 ; free virtual = 35637 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:01:04 ; elapsed = 00:01:10 . Memory (MB): peak = 2897.266 ; gain = 772.812 ; free physical = 13751 ; free virtual = 35766 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:01:04 ; elapsed = 00:01:10 . Memory (MB): peak = 2897.266 ; gain = 772.812 ; free physical = 13751 ; free virtual = 35766 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2922.078 ; gain = 0.000 ; free physical = 13508 ; free virtual = 35522 INFO: [Netlist 29-17] Analyzing 28 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_in_context.xdc] for cell 'i_ddr' WARNING: [Vivado 12-584] No ports matched ''. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_in_context.xdc:2] WARNING: [Vivado 12-584] No ports matched ''. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_in_context.xdc:3] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_in_context.xdc] for cell 'i_ddr' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen/xlnx_clk_gen_in_context.xdc] for cell 'i_xlnx_clk_gen' WARNING: [Vivado 12-584] No ports matched ''. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen/xlnx_clk_gen_in_context.xdc:1] WARNING: [Vivado 12-584] No ports matched ''. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen/xlnx_clk_gen_in_context.xdc:4] WARNING: [Vivado 12-584] No ports matched ''. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen/xlnx_clk_gen_in_context.xdc:6] WARNING: [Vivado 12-584] No ports matched ''. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen/xlnx_clk_gen_in_context.xdc:8] WARNING: [Vivado 12-584] No ports matched ''. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen/xlnx_clk_gen_in_context.xdc:10] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen/xlnx_clk_gen_in_context.xdc] for cell 'i_xlnx_clk_gen' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter/xlnx_axi_clock_converter_in_context.xdc] for cell 'i_xlnx_axi_clock_converter_ddr' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter/xlnx_axi_clock_converter_in_context.xdc] for cell 'i_xlnx_axi_clock_converter_ddr' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio/xlnx_axi_gpio_in_context.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_gpio' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio/xlnx_axi_gpio_in_context.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_gpio' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi/xlnx_axi_quad_spi_in_context.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi/xlnx_axi_quad_spi_in_context.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter_in_context.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter_in_context.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter_in_context.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter_in_context.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc] WARNING: [Vivado 12-627] No clocks matched 'clk_out2_xlnx_clk_gen'. [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:101] INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:101] CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks clk_out2_xlnx_clk_gen]'. [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:101] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:101] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. WARNING: [Vivado 12-508] No pins matched 'i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C'. [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:161] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc] WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/ariane_xilinx_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/constraints/ariane.xdc] WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/darshak/cva6/corev_apu/fpga/constraints/ariane.xdc:19] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/constraints/ariane.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/darshak/cva6/corev_apu/fpga/constraints/ariane.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/ariane_xilinx_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/ariane_xilinx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/ariane.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/ariane.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3417.406 ; gain = 0.000 ; free physical = 13113 ; free virtual = 35128 INFO: [Project 1-111] Unisim Transformation Summary: A total of 11 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance RAMB16_S9_S36 => RAMB36E1: 10 instances Constraint Validation Runtime : Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.69 . Memory (MB): peak = 3417.406 ; gain = 0.000 ; free physical = 13113 ; free virtual = 35127 WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'i_xlnx_axi_clock_converter_ddr' at clock pin 'm_axi_aclk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio' at clock pin 's_axi_aclk' is different from the actual clock period '20.000', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi' at clock pin 's_axi_aclk' is different from the actual clock period '20.000', this can lead to different synthesis results. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:02:13 ; elapsed = 00:01:58 . Memory (MB): peak = 3417.406 ; gain = 1292.953 ; free physical = 13693 ; free virtual = 35708 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information INFO: [Synth 8-802] inferred FSM for state register 'tap_state_q_reg' in module 'dmi_jtag_tap' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'dmi_jtag' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'dm_sba' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'dm_mem' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'axi2mem' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'axi_adapter' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'cva6_icache' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'wt_dcache_missunit' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'wt_dcache_ctrl' INFO: [Synth 8-802] inferred FSM for state register 'wr_state_q_reg' in module 'axi_shim' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'fpnew_divsqrt_multi' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'serdiv' INFO: [Synth 8-802] inferred FSM for state register 'ptw_lvl_q_reg' in module 'ptw' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'axi_lite_interface' INFO: [Synth 8-802] inferred FSM for state register 'state_q_reg' in module 'axi2mem__parameterized0' INFO: [Synth 8-802] inferred FSM for state register 'CState_reg' in module 'uart_transmitter' INFO: [Synth 8-802] inferred FSM for state register 'CState_reg' in module 'uart_receiver' INFO: [Synth 8-802] inferred FSM for state register 'State_reg' in module 'apb_uart' INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'axis_gmii_rx' INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'axis_gmii_tx' INFO: [Synth 8-802] inferred FSM for state register 'CS_reg' in module 'axi2apb_64_32' INFO: [Synth 8-802] inferred FSM for state register 'aw_state_q_reg' in module 'axi_riscv_amos' INFO: [Synth 8-802] inferred FSM for state register 'w_state_q_reg' in module 'axi_riscv_amos' INFO: [Synth 8-802] inferred FSM for state register 'b_state_q_reg' in module 'axi_riscv_amos' INFO: [Synth 8-802] inferred FSM for state register 'ar_state_q_reg' in module 'axi_riscv_amos' INFO: [Synth 8-802] inferred FSM for state register 'r_state_q_reg' in module 'axi_riscv_amos' INFO: [Synth 8-802] inferred FSM for state register 'r_state_q_reg' in module 'axi_riscv_lrsc' INFO: [Synth 8-802] inferred FSM for state register 'w_state_q_reg' in module 'axi_riscv_lrsc' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- R_FEEDTHROUGH | 00 | 00 R_HOLD | 01 | 10 INJECT_R | 10 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'r_state_q_reg' using encoding 'sequential' in module 'axi_atop_filter' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- W_FEEDTHROUGH | 000 | 000 BLOCK_AW | 001 | 001 ABSORB_W | 010 | 010 HOLD_B | 011 | 011 INJECT_B | 100 | 100 WAIT_R | 101 | 101 iSTATE | 110 | 111 * --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'w_state_q_reg' using encoding 'sequential' in module 'axi_atop_filter' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RunTestIdle | 0000000000000001 | 0001 SelectDrScan | 0000000000000010 | 0010 SelectIrScan | 0000000000000100 | 1001 TestLogicReset | 0000000000001000 | 0000 CaptureIr | 0000000000010000 | 1010 ShiftIr | 0000000000100000 | 1011 Exit1Ir | 0000000001000000 | 1100 PauseIr | 0000000010000000 | 1101 Exit2Ir | 0000000100000000 | 1110 UpdateIr | 0000001000000000 | 1111 CaptureDr | 0000010000000000 | 0011 ShiftDr | 0000100000000000 | 0100 Exit1Dr | 0001000000000000 | 0101 PauseDr | 0010000000000000 | 0110 Exit2Dr | 0100000000000000 | 0111 UpdateDr | 1000000000000000 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tap_state_q_reg' using encoding 'one-hot' in module 'dmi_jtag_tap' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- Idle | 000 | 000 Read | 001 | 001 WaitReadValid | 010 | 010 Write | 011 | 011 WaitWriteValid | 100 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'dmi_jtag' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 000 | 000 iSTATE2 | 001 | 001 iSTATE0 | 010 | 011 iSTATE3 | 011 | 010 iSTATE1 | 100 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'dm_sba' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- Idle | 00 | 00 Resume | 01 | 10 Go | 10 | 01 CmdExecuting | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'dm_mem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 000 READ | 001 | 001 WAIT_WVALID | 010 | 100 WRITE | 011 | 010 SEND_B | 100 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'axi2mem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 0000 | 0000 WAIT_AW_READY | 0001 | 0010 WAIT_LAST_W_READY_AW_READY | 0010 | 0100 WAIT_AW_READY_BURST | 0011 | 0101 WAIT_LAST_W_READY | 0100 | 0011 WAIT_B_VALID | 0101 | 0001 WAIT_AMO_R_VALID | 0110 | 1001 WAIT_R_VALID | 0111 | 0110 WAIT_R_VALID_MULTIPLE | 1000 | 0111 COMPLETE_READ | 1001 | 1000 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'axi_adapter' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FLUSH | 000 | 000 IDLE | 001 | 001 READ | 010 | 010 MISS | 011 | 011 KILL_MISS | 100 | 101 KILL_ATRANS | 101 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'cva6_icache' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FLUSH | 000 | 011 IDLE | 001 | 000 DRAIN | 010 | 001 AMO | 011 | 010 AMO_WAIT | 100 | 110 STORE_WAIT | 101 | 100 LOAD_WAIT | 110 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'wt_dcache_missunit' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 000 READ | 001 | 001 MISS_REQ | 010 | 010 KILL_MISS_ACK | 011 | 101 REPLAY_REQ | 100 | 110 REPLAY_READ | 101 | 111 MISS_WAIT | 110 | 011 KILL_MISS | 111 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'wt_dcache_ctrl' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 WAIT_AW_READY | 001 | 0001 WAIT_LAST_W_READY_AW_READY | 010 | 0011 WAIT_AW_READY_BURST | 011 | 0100 WAIT_LAST_W_READY | 100 | 0010 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'wr_state_q_reg' using encoding 'sequential' in module 'axi_shim' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 00 | 00 BUSY | 01 | 01 HOLD | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'fpnew_divsqrt_multi' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 00 | 00 DIVIDE | 01 | 01 FINISH | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'serdiv' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- iSTATE | 100 | 00 * iSTATE1 | 010 | 01 iSTATE0 | 001 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'ptw_lvl_q_reg' using encoding 'one-hot' in module 'ptw' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 00 | 00 WRITE | 01 | 10 WRITE_B | 10 | 11 READ | 11 | 01 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'axi_lite_interface' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 000 READ | 001 | 001 WAIT_WVALID | 010 | 100 WRITE | 011 | 010 SEND_B | 100 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_q_reg' using encoding 'sequential' in module 'axi2mem__parameterized0' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 0000000000001 | 0000 start | 0000000000010 | 0001 bit0 | 0000000000100 | 0010 bit1 | 0000000001000 | 0011 bit2 | 0000000010000 | 0100 bit3 | 0000000100000 | 0101 bit4 | 0000001000000 | 0110 bit5 | 0000010000000 | 0111 bit6 | 0000100000000 | 1000 bit7 | 0001000000000 | 1001 par | 0010000000000 | 1010 stop | 0100000000000 | 1011 stop2 | 1000000000000 | 1100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'CState_reg' using encoding 'one-hot' in module 'uart_transmitter' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 000001 | 000 start | 000010 | 001 data | 000100 | 010 par | 001000 | 011 stop | 010000 | 100 mwait | 100000 | 101 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'CState_reg' using encoding 'one-hot' in module 'uart_receiver' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- idle | 00 | 00 txstart | 01 | 01 txrun | 10 | 10 txend | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'State_reg' using encoding 'sequential' in module 'apb_uart' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- STATE_IDLE | 00 | 000 STATE_PAYLOAD | 01 | 001 STATE_WAIT_LAST | 10 | 010 STATE_CRC | 11 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'axis_gmii_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- STATE_IDLE | 000 | 000 STATE_PREAMBLE | 001 | 001 STATE_PAYLOAD | 010 | 010 STATE_LAST | 011 | 011 STATE_PAD | 100 | 100 STATE_FCS | 101 | 101 STATE_WAIT_END | 110 | 110 STATE_IFG | 111 | 111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'axis_gmii_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 0000 | 0000 WAIT_R_PREADY | 0001 | 1010 SINGLE_RD_64 | 0010 | 0010 SINGLE_RD | 0011 | 0001 BURST_RD_64 | 0100 | 0101 BURST_RD | 0101 | 0100 BURST_RD_1 | 0110 | 0011 WAIT_W_PREADY | 0111 | 1011 SINGLE_WR_64 | 1000 | 1001 SINGLE_WR | 1001 | 1000 BURST_WR_64 | 1010 | 0111 BURST_WR | 1011 | 0110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'CS_reg' using encoding 'sequential' in module 'axi2apb_64_32' WARNING: [Synth 8-327] inferring latch for variable 'ip_re_o_reg' [/home/darshak/cva6/corev_apu/rv_plic/rtl/plic_regmap.sv:325] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FEEDTHROUGH_AR | 00 | 00 WAIT_CHANNEL_AR | 01 | 01 SEND_AR | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'ar_state_q_reg' using encoding 'sequential' in module 'axi_riscv_amos' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FEEDTHROUGH_B | 00 | 00 WAIT_COMPLETE_B | 01 | 01 WAIT_CHANNEL_B | 10 | 10 SEND_B | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'b_state_q_reg' using encoding 'sequential' in module 'axi_riscv_amos' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FEEDTHROUGH_R | 00 | 00 WAIT_DATA_R | 01 | 01 WAIT_CHANNEL_R | 10 | 10 SEND_R | 11 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'r_state_q_reg' using encoding 'sequential' in module 'axi_riscv_amos' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FEEDTHROUGH_W | 000 | 000 WAIT_DATA_W | 001 | 001 WAIT_RESULT_W | 010 | 010 WAIT_CHANNEL_W | 011 | 011 SEND_W | 100 | 100 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'w_state_q_reg' using encoding 'sequential' in module 'axi_riscv_amos' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FEEDTHROUGH_AW | 001 | 00 WAIT_RESULT_AW | 010 | 01 SEND_AW | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'aw_state_q_reg' using encoding 'one-hot' in module 'axi_riscv_amos' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- AW_IDLE | 000 | 000 W_FORWARD | 001 | 001 W_WAIT_ART_CLR | 010 | 011 B_FORWARD | 011 | 101 W_DROP | 100 | 100 B_INJECT | 101 | 110 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'w_state_q_reg' using encoding 'sequential' in module 'axi_riscv_lrsc' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- R_IDLE | 00 | 00 R_WAIT_AR | 01 | 01 R_WAIT_R | 10 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'r_state_q_reg' using encoding 'sequential' in module 'axi_riscv_lrsc' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:03:21 ; elapsed = 00:03:22 . Memory (MB): peak = 3417.406 ; gain = 1292.953 ; free physical = 10272 ; free virtual = 32303 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 3 Input 164 Bit Adders := 1 2 Input 163 Bit Adders := 1 3 Input 77 Bit Adders := 1 2 Input 76 Bit Adders := 1 2 Input 65 Bit Adders := 2 3 Input 65 Bit Adders := 2 2 Input 64 Bit Adders := 49 3 Input 64 Bit Adders := 4 2 Input 63 Bit Adders := 1 3 Input 59 Bit Adders := 3 2 Input 54 Bit Adders := 1 3 Input 32 Bit Adders := 3 2 Input 32 Bit Adders := 20 2 Input 31 Bit Adders := 1 2 Input 20 Bit Adders := 1 2 Input 16 Bit Adders := 3 5 Input 13 Bit Adders := 1 3 Input 13 Bit Adders := 3 2 Input 13 Bit Adders := 4 6 Input 12 Bit Adders := 1 2 Input 12 Bit Adders := 2 4 Input 12 Bit Adders := 2 2 Input 11 Bit Adders := 5 5 Input 10 Bit Adders := 1 3 Input 10 Bit Adders := 1 4 Input 10 Bit Adders := 1 2 Input 10 Bit Adders := 3 3 Input 9 Bit Adders := 2 2 Input 9 Bit Adders := 12 2 Input 8 Bit Adders := 11 3 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 38 4 Input 7 Bit Adders := 1 3 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 9 3 Input 5 Bit Adders := 1 2 Input 5 Bit Adders := 6 2 Input 4 Bit Adders := 15 4 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 51 3 Input 3 Bit Adders := 5 2 Input 2 Bit Adders := 172 3 Input 2 Bit Adders := 64 4 Input 2 Bit Adders := 1 2 Input 1 Bit Adders := 61 3 Input 1 Bit Adders := 2 +---XORs : 2 Input 65 Bit XORs := 1 2 Input 64 Bit XORs := 69 2 Input 32 Bit XORs := 3 2 Input 8 Bit XORs := 2 2 Input 2 Bit XORs := 1 4 Input 1 Bit XORs := 15 2 Input 1 Bit XORs := 63 3 Input 1 Bit XORs := 10 7 Input 1 Bit XORs := 14 6 Input 1 Bit XORs := 10 8 Input 1 Bit XORs := 8 5 Input 1 Bit XORs := 9 9 Input 1 Bit XORs := 5 10 Input 1 Bit XORs := 2 +---Registers : 197 Bit Registers := 1 163 Bit Registers := 1 162 Bit Registers := 12 137 Bit Registers := 6 136 Bit Registers := 6 128 Bit Registers := 1 76 Bit Registers := 1 71 Bit Registers := 6 64 Bit Registers := 623 58 Bit Registers := 1 57 Bit Registers := 1 56 Bit Registers := 15 54 Bit Registers := 9 53 Bit Registers := 10 52 Bit Registers := 2 48 Bit Registers := 2 44 Bit Registers := 38 41 Bit Registers := 1 32 Bit Registers := 58 30 Bit Registers := 7 27 Bit Registers := 1 24 Bit Registers := 1 23 Bit Registers := 1 20 Bit Registers := 1 17 Bit Registers := 1 16 Bit Registers := 42 15 Bit Registers := 1 14 Bit Registers := 1 13 Bit Registers := 5 12 Bit Registers := 8 11 Bit Registers := 76 10 Bit Registers := 39 9 Bit Registers := 106 8 Bit Registers := 268 7 Bit Registers := 12 6 Bit Registers := 53 5 Bit Registers := 111 4 Bit Registers := 305 3 Bit Registers := 256 2 Bit Registers := 574 1 Bit Registers := 1359 +---Multipliers : 65x65 Multipliers := 1 53x53 Multipliers := 1 +---RAMs : 16K Bit (256 X 64 bit) RAMs := 36 88 Bit (8 X 11 bit) RAMs := 1 +---ROMs : ROMs := 1 +---Muxes : 2 Input 163 Bit Muxes := 2 2 Input 162 Bit Muxes := 6 2 Input 137 Bit Muxes := 3 2 Input 136 Bit Muxes := 3 2 Input 129 Bit Muxes := 2 2 Input 109 Bit Muxes := 3 2 Input 76 Bit Muxes := 2 2 Input 71 Bit Muxes := 3 8 Input 65 Bit Muxes := 3 2 Input 65 Bit Muxes := 4 2 Input 64 Bit Muxes := 1832 4 Input 64 Bit Muxes := 115 3 Input 64 Bit Muxes := 20 7 Input 64 Bit Muxes := 5 12 Input 64 Bit Muxes := 4 5 Input 64 Bit Muxes := 16 10 Input 64 Bit Muxes := 1 28 Input 64 Bit Muxes := 1 6 Input 64 Bit Muxes := 5 50 Input 64 Bit Muxes := 3 51 Input 64 Bit Muxes := 1 43 Input 64 Bit Muxes := 1 11 Input 64 Bit Muxes := 1 9 Input 64 Bit Muxes := 1 2 Input 58 Bit Muxes := 71 4 Input 58 Bit Muxes := 3 2 Input 57 Bit Muxes := 18 3 Input 57 Bit Muxes := 1 4 Input 57 Bit Muxes := 2 17 Input 57 Bit Muxes := 1 8 Input 57 Bit Muxes := 1 2 Input 56 Bit Muxes := 28 3 Input 56 Bit Muxes := 1 7 Input 56 Bit Muxes := 1 4 Input 56 Bit Muxes := 10 2 Input 55 Bit Muxes := 1 4 Input 54 Bit Muxes := 1 2 Input 54 Bit Muxes := 2 2 Input 53 Bit Muxes := 34 7 Input 52 Bit Muxes := 1 2 Input 52 Bit Muxes := 23 4 Input 52 Bit Muxes := 7 5 Input 52 Bit Muxes := 1 3 Input 52 Bit Muxes := 1 2 Input 51 Bit Muxes := 3 9 Input 48 Bit Muxes := 1 3 Input 44 Bit Muxes := 1 2 Input 44 Bit Muxes := 138 2 Input 41 Bit Muxes := 4 3 Input 33 Bit Muxes := 1 2 Input 32 Bit Muxes := 85 4 Input 32 Bit Muxes := 9 5 Input 32 Bit Muxes := 3 9 Input 32 Bit Muxes := 3 3 Input 32 Bit Muxes := 1 12 Input 32 Bit Muxes := 9 39 Input 32 Bit Muxes := 1 10 Input 32 Bit Muxes := 1 7 Input 32 Bit Muxes := 1 40 Input 31 Bit Muxes := 1 41 Input 31 Bit Muxes := 1 2 Input 31 Bit Muxes := 8 2 Input 30 Bit Muxes := 62 2 Input 27 Bit Muxes := 1 2 Input 24 Bit Muxes := 4 7 Input 23 Bit Muxes := 1 2 Input 23 Bit Muxes := 19 4 Input 23 Bit Muxes := 5 5 Input 23 Bit Muxes := 1 2 Input 21 Bit Muxes := 3 2 Input 20 Bit Muxes := 1 2 Input 18 Bit Muxes := 3 2 Input 16 Bit Muxes := 40 8 Input 16 Bit Muxes := 1 16 Input 16 Bit Muxes := 1 2 Input 14 Bit Muxes := 2 2 Input 13 Bit Muxes := 21 13 Input 13 Bit Muxes := 1 2 Input 12 Bit Muxes := 3 5 Input 12 Bit Muxes := 2 4 Input 12 Bit Muxes := 2 2 Input 11 Bit Muxes := 94 4 Input 11 Bit Muxes := 7 5 Input 11 Bit Muxes := 1 8 Input 11 Bit Muxes := 1 2 Input 10 Bit Muxes := 135 3 Input 10 Bit Muxes := 2 4 Input 10 Bit Muxes := 1 2 Input 9 Bit Muxes := 139 4 Input 9 Bit Muxes := 6 2 Input 8 Bit Muxes := 540 3 Input 8 Bit Muxes := 7 4 Input 8 Bit Muxes := 19 12 Input 8 Bit Muxes := 1 5 Input 8 Bit Muxes := 5 8 Input 8 Bit Muxes := 6 9 Input 8 Bit Muxes := 1 21 Input 8 Bit Muxes := 1 6 Input 8 Bit Muxes := 1 19 Input 8 Bit Muxes := 1 4 Input 7 Bit Muxes := 2 2 Input 7 Bit Muxes := 50 6 Input 7 Bit Muxes := 3 9 Input 7 Bit Muxes := 3 8 Input 7 Bit Muxes := 2 19 Input 7 Bit Muxes := 1 11 Input 7 Bit Muxes := 1 5 Input 7 Bit Muxes := 1 17 Input 7 Bit Muxes := 1 14 Input 7 Bit Muxes := 1 2 Input 6 Bit Muxes := 220 4 Input 6 Bit Muxes := 3 17 Input 6 Bit Muxes := 1 8 Input 6 Bit Muxes := 41 9 Input 6 Bit Muxes := 37 5 Input 6 Bit Muxes := 3 10 Input 6 Bit Muxes := 24 60 Input 6 Bit Muxes := 1 12 Input 6 Bit Muxes := 1 19 Input 6 Bit Muxes := 1 6 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 150 4 Input 5 Bit Muxes := 2 8 Input 5 Bit Muxes := 34 9 Input 5 Bit Muxes := 33 21 Input 5 Bit Muxes := 1 18 Input 5 Bit Muxes := 1 30 Input 5 Bit Muxes := 1 3 Input 5 Bit Muxes := 5 6 Input 5 Bit Muxes := 3 7 Input 5 Bit Muxes := 1 14 Input 5 Bit Muxes := 1 5 Input 5 Bit Muxes := 3 31 Input 5 Bit Muxes := 2 2 Input 4 Bit Muxes := 1620 5 Input 4 Bit Muxes := 11 4 Input 4 Bit Muxes := 16 3 Input 4 Bit Muxes := 5 7 Input 4 Bit Muxes := 2 12 Input 4 Bit Muxes := 2 9 Input 4 Bit Muxes := 35 8 Input 4 Bit Muxes := 2 10 Input 4 Bit Muxes := 2 46 Input 4 Bit Muxes := 3 2 Input 3 Bit Muxes := 770 5 Input 3 Bit Muxes := 58 7 Input 3 Bit Muxes := 8 6 Input 3 Bit Muxes := 10 3 Input 3 Bit Muxes := 15 4 Input 3 Bit Muxes := 11 19 Input 3 Bit Muxes := 5 17 Input 3 Bit Muxes := 1 8 Input 3 Bit Muxes := 4 34 Input 3 Bit Muxes := 1 9 Input 3 Bit Muxes := 2 2 Input 2 Bit Muxes := 1087 3 Input 2 Bit Muxes := 82 4 Input 2 Bit Muxes := 27 7 Input 2 Bit Muxes := 10 8 Input 2 Bit Muxes := 2 5 Input 2 Bit Muxes := 8 20 Input 2 Bit Muxes := 3 34 Input 2 Bit Muxes := 1 10 Input 2 Bit Muxes := 1 19 Input 2 Bit Muxes := 1 6 Input 2 Bit Muxes := 3 40 Input 2 Bit Muxes := 3 41 Input 2 Bit Muxes := 3 10 Input 1 Bit Muxes := 6 2 Input 1 Bit Muxes := 7411 6 Input 1 Bit Muxes := 237 3 Input 1 Bit Muxes := 218 7 Input 1 Bit Muxes := 82 4 Input 1 Bit Muxes := 223 5 Input 1 Bit Muxes := 72 12 Input 1 Bit Muxes := 56 15 Input 1 Bit Muxes := 1 8 Input 1 Bit Muxes := 34 34 Input 1 Bit Muxes := 3 9 Input 1 Bit Muxes := 25 16 Input 1 Bit Muxes := 1 50 Input 1 Bit Muxes := 16 60 Input 1 Bit Muxes := 1 21 Input 1 Bit Muxes := 1 14 Input 1 Bit Muxes := 5 19 Input 1 Bit Muxes := 5 39 Input 1 Bit Muxes := 2 30 Input 1 Bit Muxes := 2 13 Input 1 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 840 (col length:140) BRAMs: 890 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_mst_port_mux[1].i_axi_mux /\gen_mux.i_w_fifo/write_pointer_q_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_mst_port_mux[4].i_axi_mux /\gen_mux.i_w_fifo/write_pointer_q_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_mst_port_mux[5].i_axi_mux /\gen_mux.i_w_fifo/write_pointer_q_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_mst_port_mux[6].i_axi_mux /\gen_mux.i_w_fifo/write_pointer_q_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_slv_port_demux[0].i_axi_demux /\gen_demux.i_w_fifo/write_pointer_q_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_mst_port_mux[0].i_axi_mux /\gen_mux.i_w_fifo/write_pointer_q_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_mst_port_mux[2].i_axi_mux /\gen_mux.i_w_fifo/write_pointer_q_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_mst_port_mux[3].i_axi_mux /\gen_mux.i_w_fifo/write_pointer_q_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_mst_port_mux[9].i_axi_mux /\gen_mux.i_w_fifo/write_pointer_q_reg[0] ) WARNING: [Synth 8-3917] design wt_dcache__GB0 has port rd_tag_only_i[1] driven by constant 0 WARNING: [Synth 8-3917] design wt_dcache__GB0 has port rd_tag_only_i[0] driven by constant 0 WARNING: [Synth 8-3917] design wt_dcache__GB0 has port req_ports_o[1][data_rid][0] driven by constant 0 WARNING: [Synth 8-3917] design wt_dcache__GB0 has port req_ports_o[0][data_rid][0] driven by constant 0 INFO: [Synth 8-3886] merging instance 'i_adapter/i_icache_data_fifo/gen_asic_queue.mem_q_reg[1][paddr][0]' (FDCE) to 'i_adapter/i_icache_data_fifo/gen_asic_queue.mem_q_reg[1][paddr][1]' INFO: [Synth 8-3886] merging instance 'i_adapter/i_icache_data_fifo/gen_asic_queue.mem_q_reg[0][paddr][0]' (FDCE) to 'i_adapter/i_icache_data_fifo/gen_asic_queue.mem_q_reg[0][paddr][1]' INFO: [Synth 8-3886] merging instance 'i_adapter/i_icache_data_fifo/gen_asic_queue.mem_q_reg[1][paddr][1]' (FDCE) to 'i_adapter/i_icache_data_fifo/gen_asic_queue.mem_q_reg[1][paddr][2]' INFO: [Synth 8-3886] merging instance 'i_adapter/i_icache_data_fifo/gen_asic_queue.mem_q_reg[0][paddr][1]' (FDCE) to 'i_adapter/i_icache_data_fifo/gen_asic_queue.mem_q_reg[0][paddr][2]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_adapter/i_icache_data_fifo/\gen_asic_queue.mem_q_reg[1][paddr][2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_adapter/i_icache_data_fifo/\gen_asic_queue.mem_q_reg[0][paddr][2] ) INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rtrn_inv_q_reg[way][0]' (FDC) to 'i_adapter/dcache_rtrn_inv_q_reg[way][2]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rtrn_inv_q_reg[way][1]' (FDC) to 'i_adapter/dcache_rtrn_inv_q_reg[way][2]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rtrn_inv_q_reg[way][2]' (FDC) to 'i_adapter/dcache_rtrn_type_q_reg[2]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rtrn_inv_q_reg[vld]' (FDC) to 'i_adapter/dcache_rtrn_type_q_reg[2]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][0]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][1]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][1]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][2]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][2]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][3]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][3]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][4]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][4]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][5]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][5]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][6]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][6]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][7]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][7]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][8]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][8]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][9]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][9]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][10]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][10]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][11]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][11]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][12]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][12]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][13]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][13]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][14]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][14]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][15]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][15]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][16]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][16]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][17]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][17]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][18]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][18]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][19]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][19]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][20]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][20]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][21]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][21]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][22]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][22]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][23]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][23]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][24]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][24]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][25]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][25]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][26]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][26]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][27]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][27]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][28]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][28]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][29]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][29]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][30]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][30]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][31]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][31]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][32]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][32]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][33]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][33]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][34]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][34]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][35]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][35]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][36]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][36]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][37]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][37]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][38]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][38]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][39]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][39]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][40]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][40]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][41]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][41]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][42]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][42]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][43]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][43]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][44]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][44]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][45]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][45]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][46]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][46]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][47]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][47]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][48]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][48]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][49]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][49]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][50]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][50]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][51]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][51]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][52]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][52]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][53]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][53]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][54]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][54]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][55]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][55]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][56]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][56]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][57]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][57]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][58]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][58]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][59]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][59]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][60]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][60]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][61]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][61]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][62]' INFO: [Synth 8-3886] merging instance 'i_adapter/dcache_rd_shift_user_q_reg[1][62]' (FDCE) to 'i_adapter/dcache_rd_shift_user_q_reg[1][63]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_adapter/\dcache_rd_shift_user_q_reg[1][63] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_adapter/\dcache_rtrn_type_q_reg[2] ) INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][56]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][0]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][48]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][0]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][40]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][0]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][32]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][0]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][24]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][0]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][16]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][0]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][8]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][0]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][0]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][1]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][57]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][1]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][49]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][1]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][41]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][1]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][33]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][1]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][25]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][1]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][17]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][1]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][9]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][1]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][1]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][2]' INFO: [Synth 8-3886] merging instance 'i_adapter/icache_rd_shift_user_q_reg[1][58]' (FDCE) to 'i_adapter/icache_rd_shift_user_q_reg[1][2]' INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_adapter/\icache_rd_shift_user_q_reg[1][7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_cva6_icache/\cl_offset_q_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_cva6_icache/inv_q_reg) WARNING: [Synth 8-3332] Sequential element (FSM_sequential_wr_state_q_reg[1]) is unused and will be removed from module axi_shim. WARNING: [Synth 8-7129] Port clk_i in module rr_arb_tree__parameterized8__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port rst_ni in module rr_arb_tree__parameterized8__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port flush_i in module rr_arb_tree__parameterized8__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port clk_i in module rr_arb_tree__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port rst_ni in module rr_arb_tree__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port flush_i in module rr_arb_tree__parameterized9 is either unconnected or has no load WARNING: [Synth 8-7129] Port clk_i in module rr_arb_tree__parameterized9__2 is either unconnected or has no load WARNING: [Synth 8-7129] Port rst_ni in module rr_arb_tree__parameterized9__2 is either unconnected or has no load WARNING: [Synth 8-7129] Port flush_i in module rr_arb_tree__parameterized9__2 is either unconnected or has no load WARNING: [Synth 8-7129] Port clk_i in module rr_arb_tree__parameterized9__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port rst_ni in module rr_arb_tree__parameterized9__1 is either unconnected or has no load WARNING: [Synth 8-7129] Port flush_i in module rr_arb_tree__parameterized9__1 is either unconnected or has no load WARNING: [Synth 8-3917] design issue_stage__GC0 has port issue_instr_o[rs1][5] driven by constant 0 WARNING: [Synth 8-3917] design issue_stage__GC0 has port issue_instr_o[rs2][5] driven by constant 0 WARNING: [Synth 8-3917] design issue_stage__GC0 has port issue_instr_o[rd][5] driven by constant 0 WARNING: [Synth 8-7129] Port issue_instr_i[valid] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][63] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][62] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][61] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][60] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][59] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][58] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][57] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][56] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][55] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][54] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][53] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][52] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][51] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][50] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][49] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][48] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][47] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][46] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][45] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][44] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][43] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][42] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][41] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][40] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][39] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][38] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][37] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][36] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][35] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][34] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][33] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][32] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][31] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][30] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][29] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][28] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][27] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][26] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][25] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][24] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][23] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][22] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][21] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][20] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][19] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][18] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][17] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][16] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][15] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][14] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][13] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][12] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][11] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][10] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][9] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][8] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][7] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][6] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][5] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][4] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][3] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][2] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][1] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][cause][0] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][63] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][62] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][61] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][60] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][59] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][58] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][57] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][56] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][55] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][54] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][53] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][52] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][51] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][50] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][49] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][48] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][47] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][46] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][45] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][44] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][43] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][42] in module issue_read_operands is either unconnected or has no load WARNING: [Synth 8-7129] Port issue_instr_i[ex][tval][41] in module issue_read_operands is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][3] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][5] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][6] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][7] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][8] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][9] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][10] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][11] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][12] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][13] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][14] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][15] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][16] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][17] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][18] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][19] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][20] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][22] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][23] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][24] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][25] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][26] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][27] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][28] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][29] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][30] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][31] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][32] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][33] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][34] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][35] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][36] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][37] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][38] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][39] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][40] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][41] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][42] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][43] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][44] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][45] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][46] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][47] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][48] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][49] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][50] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][51] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][52] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][53] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][54] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][55] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][56] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][57] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][58] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][59] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][60] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][61] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][62] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_issue_read_operands/\gen_asic_regfile.i_ariane_regfile/mem_reg[0][63] ) DSP Report: Generating DSP product, operation Mode is: A*B. DSP Report: operator product is absorbed into DSP product. DSP Report: operator product is absorbed into DSP product. DSP Report: Generating DSP product, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator product is absorbed into DSP product. DSP Report: operator product is absorbed into DSP product. INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 10 [/home/darshak/cva6/vendor/openhwgroup/cvfpu/src/fpnew_fma.sv:332] DSP Report: Generating DSP product, operation Mode is: A*B. DSP Report: operator product is absorbed into DSP product. DSP Report: operator product is absorbed into DSP product. DSP Report: Generating DSP product, operation Mode is: PCIN+A*B. DSP Report: operator product is absorbed into DSP product. DSP Report: operator product is absorbed into DSP product. DSP Report: Generating DSP product, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator product is absorbed into DSP product. DSP Report: operator product is absorbed into DSP product. DSP Report: Generating DSP product, operation Mode is: A*B. DSP Report: operator product is absorbed into DSP product. DSP Report: operator product is absorbed into DSP product. DSP Report: Generating DSP product, operation Mode is: PCIN+A*B. DSP Report: operator product is absorbed into DSP product. DSP Report: operator product is absorbed into DSP product. DSP Report: Generating DSP product, operation Mode is: PCIN+A*B. DSP Report: operator product is absorbed into DSP product. DSP Report: operator product is absorbed into DSP product. DSP Report: Generating DSP product, operation Mode is: A*B. DSP Report: operator product is absorbed into DSP product. DSP Report: operator product is absorbed into DSP product. DSP Report: Generating DSP product, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator product is absorbed into DSP product. DSP Report: operator product is absorbed into DSP product. DSP Report: Generating DSP product, operation Mode is: PCIN+A*B. DSP Report: operator product is absorbed into DSP product. DSP Report: operator product is absorbed into DSP product. INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3886] merging instance 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_input_pipeline[0].inp_pipe_mask_q_reg[1]' (FDCE) to 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_input_pipeline[0].inp_pipe_is_boxed_q_reg[1][0]' INFO: [Synth 8-3886] merging instance 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_input_pipeline[0].inp_pipe_is_boxed_q_reg[1][2]' (FDCE) to 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_input_pipeline[0].inp_pipe_is_boxed_q_reg[1][0]' INFO: [Synth 8-3886] merging instance 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_input_pipeline[0].inp_pipe_is_boxed_q_reg[1][1]' (FDCE) to 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_input_pipeline[0].inp_pipe_is_boxed_q_reg[1][0]' INFO: [Synth 8-3886] merging instance 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_stat_q_reg[1][DZ]' (FDCE) to 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][0]' INFO: [Synth 8-3886] merging instance 'gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_input_pipeline[0].inp_pipe_mask_q_reg[1]' (FDCE) to 'gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_input_pipeline[0].inp_pipe_is_boxed_q_reg[1][1]' INFO: [Synth 8-3886] merging instance 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][0]' (FDCE) to 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][1]' INFO: [Synth 8-3886] merging instance 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][1]' (FDCE) to 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][2]' INFO: [Synth 8-3886] merging instance 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][2]' (FDCE) to 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][3]' INFO: [Synth 8-3886] merging instance 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][3]' (FDCE) to 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][4]' INFO: [Synth 8-3886] merging instance 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][4]' (FDCE) to 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][5]' INFO: [Synth 8-3886] merging instance 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][5]' (FDCE) to 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][6]' INFO: [Synth 8-3886] merging instance 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][6]' (FDCE) to 'gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][7]' INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_operation_groups[0].i_opgroup_block /\gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma /\gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][50] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_operation_groups[2].i_opgroup_block /\gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_noncomp/gen_input_pipeline[0].inp_pipe_aux_q_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_operation_groups[2].i_opgroup_block /\gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_noncomp/gen_input_pipeline[0].inp_pipe_aux_q_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_operation_groups[0].i_opgroup_block /\gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_spec_res_q_reg[1][mantissa][21] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_operation_groups[3].i_opgroup_block /\i_arbiter/gen_arbiter.rr_q_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_operation_groups[2].i_opgroup_block /\i_arbiter/gen_arbiter.rr_q_reg[2] ) INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_operation_groups[0].i_opgroup_block /\i_arbiter/gen_arbiter.rr_q_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi /\gen_input_pipeline[0].inp_pipe_aux_q_reg[1][4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi /i_divsqrt_lei/\nrbd_nrsc_U0/control_U0 /\Precision_ctl_S_reg[4] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\gen_operation_groups[1].i_opgroup_block/i_arbiter/gen_arbiter.rr_q_reg[0] ) INFO: [Synth 8-5587] ROM size for "amo_op_d" is below threshold of ROM address width. It will be mapped to LUTs INFO: [Synth 8-5546] ROM "extract_transfer_size" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "extract_transfer_size" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "extract_transfer_size" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 16 [/home/darshak/cva6/core/multiplier.sv:102] DSP Report: Generating DSP mult_result_d, operation Mode is: A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: PCIN+A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: PCIN+A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: PCIN+A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: PCIN+A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: PCIN+A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: PCIN+A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: Generating DSP mult_result_d, operation Mode is: (PCIN>>17)+A*B. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. DSP Report: operator mult_result_d is absorbed into DSP mult_result_d. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[47]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[46]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[45]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[44]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[43]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[42]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[41]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[40]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[39]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[38]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[37]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[36]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[35]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[34]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[33]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[32]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[31]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[30]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[29]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[28]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[27]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[26]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[25]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[24]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[23]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[22]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[21]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[20]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[19]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[18]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[17]) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[47]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[46]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[45]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[44]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[43]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[42]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[41]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[40]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[39]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[38]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[37]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[36]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[35]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[34]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[33]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[32]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[31]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[30]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[29]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[28]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[27]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[26]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[25]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[24]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[23]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[22]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[21]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[20]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[19]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[18]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[17]__0) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[47]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[46]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[45]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[44]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[43]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[42]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[41]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[40]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[39]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[38]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[37]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[36]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[35]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[34]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[33]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[32]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[31]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[30]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[29]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[28]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[27]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[26]__1) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[47]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[46]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[45]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[44]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[43]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[42]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[41]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[40]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[39]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[38]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[37]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[36]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[35]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[34]__2) is unused and will be removed from module multiplier. WARNING: [Synth 8-3332] Sequential element (mult_result_q_reg[33]__2) is unused and will be removed from module multiplier. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5546] ROM "medeleg_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "scounteren_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "mstatus_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "dcsr_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "dpc_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "stvec_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "dscratch0_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "dscratch1_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "mideleg_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "mie_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "sscratch_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "sepc_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "scause_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "stval_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "mcounteren_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "mscratch_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "mepc_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "mcause_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "mtval_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "mcountinhibit_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "dcache_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "icache_d" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "perf_we_o" won't be mapped to RAM because it is too sparse INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 0 across sequential element (csr_regfile_i/\mip_q_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (csr_regfile_i/\mideleg_q_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (csr_regfile_i/\pmpaddr_q_reg[15][0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (csr_regfile_i/\medeleg_q_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (csr_regfile_i/\stvec_q_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (csr_regfile_i/\pmpaddr_q_reg[15][1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (csr_regfile_i/\mcountinhibit_q_reg[1] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (csr_regfile_i/\medeleg_q_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (csr_regfile_i/\mip_q_reg[2] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (csr_regfile_i/\mideleg_q_reg[2] ) INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5546] ROM "resp_o" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "ip_re_o" won't be mapped to RAM because it is too sparse --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:07:28 ; elapsed = 00:07:30 . Memory (MB): peak = 3417.406 ; gain = 1292.953 ; free physical = 9718 ; free virtual = 31901 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +--------------+------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +--------------+------------------+---------------+----------------+ |debug_rom | mem | 32x55 | LUT | |fpu_wrap | fpu_gen.fpu_op_d | 64x4 | LUT | |ariane_xilinx | fpu_gen.fpu_op_d | 64x4 | LUT | +--------------+------------------+---------------+----------------+ Block RAM: Preliminary Mapping Report (see note below) +--------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +--------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |\gen_data_banks[0].i_data_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[2].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[3].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[4].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[5].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[6].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[7].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[2].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[3].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[4].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[5].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[6].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[7].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[0].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[1].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[2].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[3].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[4].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[5].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[6].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[7].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[0].tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[0].data_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[0].data_sram | gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[1].tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[1].data_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[1].data_sram | gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[2].tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[2].data_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[2].data_sram | gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[3].tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[3].data_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[3].data_sram | gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +--------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. Distributed RAM: Preliminary Mapping Report (see note below) +-------------------------+--------------------+-----------+----------------------+-------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +-------------------------+--------------------+-----------+----------------------+-------------+ |\gen_ethernet.eth_rgmii | rx_length_axis_reg | Implied | 8 x 11 | RAM32M x 2 | +-------------------------+--------------------+-----------+----------------------+-------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. DSP: Preliminary Mapping Report (see note below) +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |fpnew_fma | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |fpnew_fma | (PCIN>>17)+A*B | 25 | 8 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 | |fpnew_fma | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |fpnew_fma | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |fpnew_fma | (PCIN>>17)+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |fpnew_fma | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |fpnew_fma | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |fpnew_fma | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |fpnew_fma | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |fpnew_fma | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |fpnew_fma | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | (PCIN>>17)+A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | PCIN+A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | (PCIN>>17)+A*B | 14 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | PCIN+A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | (PCIN>>17)+A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | (PCIN>>17)+A*B | 18 | 14 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | |multiplier | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:07:43 ; elapsed = 00:07:47 . Memory (MB): peak = 3417.406 ; gain = 1292.953 ; free physical = 9519 ; free virtual = 31802 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- info: optimization accepted worst group hill climbing move (-2056.0/oG. 43.0ps) --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:16:20 ; elapsed = 00:16:38 . Memory (MB): peak = 3982.859 ; gain = 1858.406 ; free physical = 8751 ; free virtual = 31054 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Block RAM: Final Mapping Report +--------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +--------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |\gen_data_banks[0].i_data_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[2].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[3].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[4].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[5].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[6].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[0].i_data_sram | gen_cut[7].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[2].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[3].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[4].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[5].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[6].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_data_banks[1].i_data_sram | gen_cut[7].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[0].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[1].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[2].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[3].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[4].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[5].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[6].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |\gen_tag_srams[7].i_tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[0].tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[0].data_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[0].data_sram | gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[1].tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[1].data_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[1].data_sram | gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[2].tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[2].data_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[2].data_sram | gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[3].tag_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[3].data_sram | gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | |i_cva6_icache/\gen_sram[3].data_sram | gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg | 256 x 64(READ_FIRST) | W | | 256 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +--------------------------------------+-----------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Distributed RAM: Final Mapping Report +-------------------------+--------------------+-----------+----------------------+-------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +-------------------------+--------------------+-----------+----------------------+-------------+ |\gen_ethernet.eth_rgmii | rx_length_axis_reg | Implied | 8 x 11 | RAM32M x 2 | +-------------------------+--------------------+-----------+----------------------+-------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-5816] Retiming module `addr_decode` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `addr_decode' done INFO: [Synth 8-5816] Retiming module `addr_decode__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `addr_decode__1' done INFO: [Synth 8-5816] Retiming module `axi_xbar__GCB0` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `axi_xbar__GCB0' done INFO: [Synth 8-5816] Retiming module `axi_xbar__GCB1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `axi_xbar__GCB1' done INFO: [Synth 8-5816] Retiming module `axi_xbar__GCB2` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `axi_xbar__GCB2' done INFO: [Synth 8-5816] Retiming module `cvxif_example_coprocessor` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `cvxif_example_coprocessor' done INFO: [Synth 8-5816] Retiming module `wt_dcache_mem` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `wt_dcache_mem' done INFO: [Synth 8-5816] Retiming module `wt_cache_subsystem__GC0` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `wt_cache_subsystem__GC0' done INFO: [Synth 8-5816] Retiming module `scoreboard__GB2` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `scoreboard__GB2' done RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_14/gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/preprocess_U0/Mant_a_norm_DP_reg[51] along load instance fpu_gen.i_fpnew_bulki_14/preprocess_U0/i_2 due to (NOT ENOUGH REGISTERS) RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_14/gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/preprocess_U0/Mant_a_norm_DP_reg[27] along load instance fpu_gen.i_fpnew_bulki_14/preprocess_U0/i_1 due to (NOT ENOUGH REGISTERS) INFO: [Synth 8-5816] Retiming module `fpnew_top__GB1` Numbers of forward move = 2, and backward move = 27 Retimed registers names: gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Crtl_cnt_S_reg[1]_fret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Crtl_cnt_S_reg[1]_fret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[32]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[32]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[32]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[33]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[33]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[33]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[34]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[34]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[34]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[35]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[35]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[35]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[36]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[36]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[36]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[37]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[37]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[37]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[38]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[38]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[38]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[39]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[39]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[39]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[40]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[40]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[40]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[41]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[41]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[41]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[42]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[42]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[42]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[43]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[43]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[43]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[44]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[44]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[44]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[45]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[45]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[45]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[46]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[46]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[46]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[47]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[47]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[47]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[48]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[48]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[48]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[49]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[49]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[49]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[50]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[50]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[50]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[51]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[51]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[51]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[52]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[52]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[52]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[53]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[53]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[53]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[54]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[54]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[54]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[55]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[55]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[55]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[56]_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[56]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Partial_remainder_DP_reg[56]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Quotient_DP_reg[0]_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Quotient_DP_reg[0]_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Quotient_DP_reg[0]_bret__2 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Quotient_DP_reg[0]_bret__3 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Quotient_DP_reg[0]_bret__4 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Quotient_DP_reg[0]_bret_bret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Quotient_DP_reg[0]_bret_bret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Quotient_DP_reg[0]_bret_bret__1 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Quotient_DP_reg[0]_bret_bret__2 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Quotient_DP_reg[0]_bret_bret__3 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/nrbd_nrsc_U0/control_U0/Quotient_DP_reg[0]_bret_bret__4 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/preprocess_U0/Exp_a_norm_DP_reg[0]_fret gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/preprocess_U0/Exp_a_norm_DP_reg[0]_fret__0 gen_operation_groups[1].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_divsqrt_multi/i_divsqrt_lei/preprocess_U0/Exp_a_norm_DP_reg[0]_fret__1 INFO: [Synth 8-5816] Retiming module `fpnew_top__GB1' done INFO: [Synth 8-5816] Retiming module `fpu_wrap__GC0` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `fpu_wrap__GC0' done INFO: [Synth 8-5816] Retiming module `tlb` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `tlb' done INFO: [Synth 8-5816] Retiming module `tlb__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `tlb__1' done INFO: [Synth 8-5816] Retiming module `pmp` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `pmp' done INFO: [Synth 8-5816] Retiming module `ptw__GC0` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ptw__GC0' done INFO: [Synth 8-5816] Retiming module `pmp__1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `pmp__1' done INFO: [Synth 8-5816] Retiming module `pmp__2` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `pmp__2' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT0` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT0' done INFO: [Synth 8-5816] Retiming module `ariane_peripherals__GCB0` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_peripherals__GCB0' done INFO: [Synth 8-5816] Retiming module `ariane_peripherals__GCB1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_peripherals__GCB1' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx__GCB0` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx__GCB0' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx__GCB1` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx__GCB1' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx__GCB2` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx__GCB2' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx' done INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[2].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[3].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[4].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[5].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[6].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[7].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[2].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[3].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[4].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[5].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[6].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[7].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[0].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[1].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[2].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[3].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[4].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[5].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[6].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[7].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_cva6i_7/i_cva6_icache/gen_sram[0].tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_cva6i_7/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_cva6i_7/i_cva6_icache/gen_sram[0].data_sram/gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_cva6i_7/i_cva6_icache/gen_sram[1].tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_cva6i_7/i_cva6_icache/gen_sram[1].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_cva6i_7/i_cva6_icache/gen_sram[1].data_sram/gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_cva6i_7/i_cva6_icache/gen_sram[2].tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_cva6i_7/i_cva6_icache/gen_sram[2].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_cva6i_7/i_cva6_icache/gen_sram[2].data_sram/gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_cva6i_7/i_cva6_icache/gen_sram[3].tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_cva6i_7/i_cva6_icache/gen_sram[3].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_cva6i_7/i_cva6_icache/gen_sram[3].data_sram/gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/i_bootrom/addr_q_reg_rep_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_2/i_bootrom/addr_q_reg_rep_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__354 along load instance fpu_gen.i_fpnew_bulki_13/i_1562 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__353 along load instance fpu_gen.i_fpnew_bulki_13/i_1562 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__352 along load instance fpu_gen.i_fpnew_bulki_13/i_1562 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__351 along load instance fpu_gen.i_fpnew_bulki_13/i_1562 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__358 along load instance fpu_gen.i_fpnew_bulki_13/i_1563 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__357 along load instance fpu_gen.i_fpnew_bulki_13/i_1563 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__356 along load instance fpu_gen.i_fpnew_bulki_13/i_1563 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__355 along load instance fpu_gen.i_fpnew_bulki_13/i_1563 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__354 along load instance fpu_gen.i_fpnew_bulki_13/i_1562 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__353 along load instance fpu_gen.i_fpnew_bulki_13/i_1562 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__352 along load instance fpu_gen.i_fpnew_bulki_13/i_1562 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__351 along load instance fpu_gen.i_fpnew_bulki_13/i_1562 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__358 along load instance fpu_gen.i_fpnew_bulki_13/i_1563 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__357 along load instance fpu_gen.i_fpnew_bulki_13/i_1563 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__362 along load instance fpu_gen.i_fpnew_bulki_13/i_1564 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__361 along load instance fpu_gen.i_fpnew_bulki_13/i_1564 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__356 along load instance fpu_gen.i_fpnew_bulki_13/i_1563 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__355 along load instance fpu_gen.i_fpnew_bulki_13/i_1563 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__360 along load instance fpu_gen.i_fpnew_bulki_13/i_1564 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__359 along load instance fpu_gen.i_fpnew_bulki_13/i_1564 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__366 along load instance fpu_gen.i_fpnew_bulki_13/i_1565 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__365 along load instance fpu_gen.i_fpnew_bulki_13/i_1565 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__364 along load instance fpu_gen.i_fpnew_bulki_13/i_1565 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__363 along load instance fpu_gen.i_fpnew_bulki_13/i_1565 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__354 along load instance fpu_gen.i_fpnew_bulki_13/i_1562 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__353 along load instance fpu_gen.i_fpnew_bulki_13/i_1562 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__352 along load instance fpu_gen.i_fpnew_bulki_13/i_1562 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__351 along load instance fpu_gen.i_fpnew_bulki_13/i_1562 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__358 along load instance fpu_gen.i_fpnew_bulki_13/i_1563 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__357 along load instance fpu_gen.i_fpnew_bulki_13/i_1563 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__362 along load instance fpu_gen.i_fpnew_bulki_13/i_1564 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__361 along load instance fpu_gen.i_fpnew_bulki_13/i_1564 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__356 along load instance fpu_gen.i_fpnew_bulki_13/i_1563 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__355 along load instance fpu_gen.i_fpnew_bulki_13/i_1563 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__360 along load instance fpu_gen.i_fpnew_bulki_13/i_1564 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__359 along load instance fpu_gen.i_fpnew_bulki_13/i_1564 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__366 along load instance fpu_gen.i_fpnew_bulki_13/i_1565 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__365 along load instance fpu_gen.i_fpnew_bulki_13/i_1565 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__364 along load instance fpu_gen.i_fpnew_bulki_13/i_1565 RETIMING: forward move fails for register fpu_gen.i_fpnew_bulki_13/i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__363 along load instance fpu_gen.i_fpnew_bulki_13/i_1565 INFO: [Synth 8-5816] Retiming module `fpnew_top__GB0_tempName` Numbers of forward move = 3, and backward move = 56 Retimed registers names: i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][149]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][149]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][149]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][149]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][149]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][150]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][150]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][150]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][150]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][150]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][151]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][151]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][151]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][151]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][151]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][152]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][152]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][152]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][152]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][152]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][153]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][153]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][153]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][153]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][153]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][154]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][154]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][154]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][154]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][154]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][155]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][155]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][155]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][155]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][155]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][156]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][156]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][156]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][156]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][156]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][157]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][157]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][157]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][157]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][157]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][158]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][158]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][158]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][158]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][158]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][159]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][159]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][159]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][159]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][159]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][160]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][160]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][160]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][160]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][160]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][161]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][161]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][161]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][161]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][161]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__10 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__100 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__101 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__102 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__103 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__104 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__105 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__106 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__107 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__108 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__109 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__11 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__110 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__111 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i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__90 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__91 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__92 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__93 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__94 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__95 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__96 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__97 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__98 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][162]_bret_bret__99 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][76]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][76]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][76]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][77]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][77]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][77]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][78]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][78]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][78]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][79]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][79]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][79]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][80]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][80]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_inside_pipeline[0].mid_pipe_sum_q_reg[1][80]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][0]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][0]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][0]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][10]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][10]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][10]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][1]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][1]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][1]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][2]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][2]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][2]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][3]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][3]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][3]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][4]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][4]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][4]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][5]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][5]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][5]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][6]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][6]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][6]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][7]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][7]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][7]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][8]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][8]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][8]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][9]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][9]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][exponent][9]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][36]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][36]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][37]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][37]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][38]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][38]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][39]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][39]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][40]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][40]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][41]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][41]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][42]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][42]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][43]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][43]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][44]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][44]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][45]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][45]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][46]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][46]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][47]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][47]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][48]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][48]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][49]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][49]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][50]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][50]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][51]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][51]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_result_q_reg[1][mantissa][51]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][NX]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][NX]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][NX]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][OF]_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][OF]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret__5 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret__6 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__10 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__11 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__12 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__13 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__14 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__5 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__6 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__7 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__8 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/gen_output_pipeline[0].out_pipe_status_q_reg[1][UF]_bret_bret_bret__9 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__10 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__0 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__1 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__10 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__11 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__12 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__13 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__14 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__5 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__6 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__7 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__8 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__11_fret__9 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__12 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__13 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__14 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__15 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__16 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__17 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__18 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__19 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__2 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__20 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__3 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__4 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__5 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__6 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__7 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__8 i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[3].i_opgroup_block/gen_merged_slice.i_multifmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fpnew_cast_multi/gen_inside_pipeline[0].mid_pipe_dst_fmt_q_reg[1][0]_fret__9 INFO: [Synth 8-5816] Retiming module `fpnew_top__GB0_tempName' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx' done INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT0__4_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT0__4_tempName' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx' done INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/darshak/cva6/core/multiplier.sv:138] INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/darshak/cva6/core/multiplier.sv:138] INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/darshak/cva6/core/multiplier.sv:138] INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/darshak/cva6/core/multiplier.sv:138] INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT1_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT1_tempName' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT2_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT2_tempName' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT3_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT3_tempName' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT4_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT4_tempName' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT5_tempName` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx_GT5_tempName' done INFO: [Synth 8-5816] Retiming module `ariane_xilinx` Numbers of forward move = 0, and backward move = 0 INFO: [Synth 8-5816] Retiming module `ariane_xilinx' done --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:20:19 ; elapsed = 00:20:40 . Memory (MB): peak = 3994.785 ; gain = 1870.332 ; free physical = 7795 ; free virtual = 30100 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[2].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[3].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[4].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[5].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[6].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[0].i_data_sram/gen_cut[7].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[2].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[3].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[4].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[5].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[6].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks[1].i_data_sram/gen_cut[7].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[0].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[1].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[2].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[3].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[4].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[5].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[6].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams[7].i_tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[1].tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[1].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[1].data_sram/gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[2].tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[2].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[2].data_sram/gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[3].tag_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[3].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[3].data_sram/gen_cut[1].i_tc_sram_wrapper/i_ram/Mem_DP_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_bootrom/addr_q_reg_rep_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance i_bootrom/addr_q_reg_rep_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-4649] Removing BlackBox instance \i_ariane/i_cva6/i_frontend/i_btb/i_unread of module unread having unconnected or no output ports INFO: [Synth 8-4649] Removing BlackBox instance \i_ariane/i_cva6/i_frontend/i_bht/i_unread of module unread__6 having unconnected or no output ports INFO: [Synth 8-4649] Removing BlackBox instance \i_ariane/i_cva6/i_frontend/i_instr_queue/i_unread_address_fifo of module unread__1 having unconnected or no output ports INFO: [Synth 8-4649] Removing BlackBox instance \i_ariane/i_cva6/i_frontend/i_instr_queue/i_unread_branch_mask of module unread__2 having unconnected or no output ports INFO: [Synth 8-4649] Removing BlackBox instance \i_ariane/i_cva6/i_frontend/i_instr_queue/i_unread_lzc of module unread__3 having unconnected or no output ports INFO: [Synth 8-4649] Removing BlackBox instance \i_ariane/i_cva6/i_frontend/i_instr_queue/i_unread_fifo_pos of module unread__4 having unconnected or no output ports INFO: [Synth 8-4649] Removing BlackBox instance \i_ariane/i_cva6/i_frontend/i_instr_queue/i_unread_instr_fifo of module unread__5 having unconnected or no output ports --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:20:53 ; elapsed = 00:21:15 . Memory (MB): peak = 4021.996 ; gain = 1897.543 ; free physical = 8090 ; free virtual = 30571 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:20:53 ; elapsed = 00:21:15 . Memory (MB): peak = 4021.996 ; gain = 1897.543 ; free physical = 8091 ; free virtual = 30572 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:21:20 ; elapsed = 00:21:43 . Memory (MB): peak = 4021.996 ; gain = 1897.543 ; free physical = 8079 ; free virtual = 30560 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:21:21 ; elapsed = 00:21:44 . Memory (MB): peak = 4021.996 ; gain = 1897.543 ; free physical = 8079 ; free virtual = 30560 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:21:26 ; elapsed = 00:21:49 . Memory (MB): peak = 4021.996 ; gain = 1897.543 ; free physical = 8079 ; free virtual = 30561 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:21:27 ; elapsed = 00:21:50 . Memory (MB): peak = 4021.996 ; gain = 1897.543 ; free physical = 8079 ; free virtual = 30561 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |ariane_xilinx | i_ariane_peripherals/gen_ethernet.eth_rgmii/rgmii_soc1/core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_3_reg | 3 | 1 | NO | NO | YES | 1 | 0 | |ariane_xilinx | i_ariane_peripherals/gen_ethernet.eth_rgmii/rgmii_soc1/core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rx_er_d4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | |ariane_xilinx | i_ariane_peripherals/gen_ethernet.eth_rgmii/rgmii_soc1/core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[7] | 4 | 8 | NO | NO | YES | 8 | 0 | |ariane_xilinx | i_ariane_peripherals/gen_ethernet.eth_rgmii/rgmii_soc1/core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/tx_mii_select_3_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+--------------------------+----------+ | |BlackBox name |Instances | +------+--------------------------+----------+ |1 |xlnx_mig_7_ddr3 | 1| |2 |xlnx_axi_clock_converter | 1| |3 |xlnx_clk_gen | 1| |4 |xlnx_axi_gpio | 1| |5 |xlnx_axi_dwidth_converter | 2| |6 |xlnx_axi_quad_spi | 1| +------+--------------------------+----------+ Report Cell Usage: +------+---------------------------+------+ | |Cell |Count | +------+---------------------------+------+ |1 |xlnx_axi_clock_converter | 1| |2 |xlnx_axi_dwidth_converter | 1| |3 |xlnx_axi_dwidth_converter_ | 1| |4 |xlnx_axi_gpio | 1| |5 |xlnx_axi_quad_spi | 1| |6 |xlnx_clk_gen | 1| |7 |xlnx_mig_7_ddr3 | 1| |8 |BUFG | 1| |9 |BUFIO | 1| |10 |BUFR | 1| |11 |CARRY4 | 2845| |12 |DSP48E1 | 27| |15 |IDDR | 5| |16 |IDELAYCTRL | 1| |17 |IDELAYE2 | 5| |18 |LUT1 | 511| |19 |LUT2 | 7693| |20 |LUT3 | 14275| |21 |LUT4 | 8317| |22 |LUT5 | 11496| |23 |LUT6 | 29958| |24 |MUXF7 | 2147| |25 |MUXF8 | 256| |26 |ODDR | 6| |27 |RAM32M | 2| |28 |RAMB16_S9_S36 | 10| |29 |RAMB36E1 | 38| |32 |SRL16E | 11| |33 |FDCE | 35177| |34 |FDPE | 175| |35 |FDRE | 301| |36 |FDSE | 140| |37 |IBUF | 21| |38 |IOBUF | 1| |39 |OBUF | 22| +------+---------------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:21:27 ; elapsed = 00:21:50 . Memory (MB): peak = 4021.996 ; gain = 1897.543 ; free physical = 8079 ; free virtual = 30561 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 509 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:20:33 ; elapsed = 00:21:16 . Memory (MB): peak = 4025.906 ; gain = 1381.312 ; free physical = 13016 ; free virtual = 35498 Synthesis Optimization Complete : Time (s): cpu = 00:21:33 ; elapsed = 00:21:53 . Memory (MB): peak = 4025.906 ; gain = 1901.453 ; free physical = 13045 ; free virtual = 35499 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4025.906 ; gain = 0.000 ; free physical = 12986 ; free virtual = 35439 INFO: [Netlist 29-17] Analyzing 5343 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 1 inverter(s) to 2 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4102.035 ; gain = 0.000 ; free physical = 12942 ; free virtual = 35395 INFO: [Project 1-111] Unisim Transformation Summary: A total of 13 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAMB16_S9_S36 => RAMB36E1: 8 instances RAMB16_S9_S36 => RAMB36E1 (inverted pins: CLKARDCLK): 2 instances INFO: [Common 17-83] Releasing license: Synthesis 874 Infos, 274 Warnings, 2 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:22:06 ; elapsed = 00:22:27 . Memory (MB): peak = 4102.035 ; gain = 1985.586 ; free physical = 13205 ; free virtual = 35659 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/ariane.runs/synth_1/ariane_xilinx.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:25 ; elapsed = 00:00:24 . Memory (MB): peak = 4134.051 ; gain = 32.016 ; free physical = 13194 ; free virtual = 35667 INFO: [runtcl-4] Executing : report_utilization -file ariane_xilinx_utilization_synth.rpt -pb ariane_xilinx_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 09:24:55 2023... [Tue Oct 10 09:25:06 2023] synth_1 finished wait_on_run: Time (s): cpu = 00:22:53 ; elapsed = 00:23:21 . Memory (MB): peak = 3593.867 ; gain = 0.000 ; free physical = 15162 ; free virtual = 37187 # open_run synth_1 Design is defaulting to impl run constrset: constrs_1 Design is defaulting to synth run part: xc7k325tffg900-2 INFO: [Project 1-454] Reading design checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.dcp' for cell 'i_ddr' INFO: [Project 1-454] Reading design checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.dcp' for cell 'i_xlnx_axi_clock_converter_ddr' INFO: [Project 1-454] Reading design checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.dcp' for cell 'i_xlnx_clk_gen' INFO: [Project 1-454] Reading design checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.dcp' for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio' INFO: [Project 1-454] Reading design checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.dcp' for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_gpio' INFO: [Project 1-454] Reading design checkpoint '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.dcp' for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi' Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 3593.867 ; gain = 0.000 ; free physical = 15071 ; free virtual = 37095 INFO: [Netlist 29-17] Analyzing 6186 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.1 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. i_xlnx_clk_gen/inst/clkin1_ibufg Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design. WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'i_xlnx_clk_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc] for cell 'i_ddr' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc] for cell 'i_ddr' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen_board.xdc] for cell 'i_xlnx_clk_gen/inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen_board.xdc] for cell 'i_xlnx_clk_gen/inst' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc] for cell 'i_xlnx_clk_gen/inst' INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc:57] INFO: [Timing 38-2] Deriving generated clocks [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc:57] get_clocks: Time (s): cpu = 00:00:37 ; elapsed = 00:00:19 . Memory (MB): peak = 4108.195 ; gain = 514.328 ; free physical = 14358 ; free virtual = 36383 Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xdc] for cell 'i_xlnx_clk_gen/inst' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_gpio/U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_gpio/U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_gpio/U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_gpio/U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_board.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_board.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc] CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:16] CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:17] CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:18] CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:19] CRITICAL WARNING: [Common 17-69] Command failed: 'E6' is not a valid site or package pin name. [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc:20] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/constraints/genesys-2.xdc] Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/constraints/ariane.xdc] Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/constraints/ariane.xdc] Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc] for cell 'i_xlnx_axi_clock_converter_ddr/inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc] for cell 'i_xlnx_axi_clock_converter_ddr/inst' CRITICAL WARNING: [Designutils 20-1280] Could not find module 'xlnx_axi_dwidth_converter_dm_master'. The XDC file /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master_clocks.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'xlnx_axi_dwidth_converter_dm_slave'. The XDC file /home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_clocks.xdc will not be read for any cell of this module. Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_clocks.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_clocks.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter_clocks.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter_clocks.xdc] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst' Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter_clocks.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst' Finished Parsing XDC File [/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter_clocks.xdc] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' INFO: [Vivado 12-3272] Current instance is the top level cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. Instance: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst This will add unnecessary latency to the design. Please check the design for the following: 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2020.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Constraints 18-5572] Instance i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4111.195 ; gain = 0.000 ; free physical = 14479 ; free virtual = 36504 INFO: [Project 1-111] Unisim Transformation Summary: A total of 372 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 26 instances OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 308 instances open_run: Time (s): cpu = 00:01:21 ; elapsed = 00:01:00 . Memory (MB): peak = 4111.195 ; gain = 517.328 ; free physical = 14479 ; free virtual = 36504 # exec mkdir -p reports/ # exec rm -rf reports/* # check_timing -verbose -file reports/$project.check_timing.rpt INFO: [Timing 38-35] Done setting XDC timing constraints. check_timing: Time (s): cpu = 00:00:50 ; elapsed = 00:00:12 . Memory (MB): peak = 4170.582 ; gain = 59.387 ; free physical = 14297 ; free virtual = 36322 # report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack. report_timing: Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 4184.582 ; gain = 14.000 ; free physical = 14246 ; free virtual = 36271 # report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group. # report_utilization -hierarchical -file reports/$project.utilization.rpt # report_cdc -file reports/$project.cdc.rpt INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -2, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs INFO: [Timing 38-433] Consider using Xilinx recommended XPM_CDC modules to avoid Critical severities INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port. # report_clock_interaction -file reports/$project.clock_interaction.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs WARNING: [Timing 38-164] This design has multiple clocks. Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. report_clock_interaction: Time (s): cpu = 00:00:41 ; elapsed = 00:00:07 . Memory (MB): peak = 4214.582 ; gain = 6.000 ; free physical = 14238 ; free virtual = 36263 # set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1] # set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1] # launch_runs impl_1 INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.xci' is already up-to-date INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4267.477 ; gain = 12.875 ; free physical = 14221 ; free virtual = 36247 [Tue Oct 10 09:27:09 2023] Launched impl_1... Run output will be captured here: /home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/runme.log launch_runs: Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 4292.438 ; gain = 77.855 ; free physical = 14176 ; free virtual = 36230 # wait_on_run impl_1 [Tue Oct 10 09:27:09 2023] Waiting for impl_1 to finish... *** Running vivado with args -log ariane_xilinx.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source ariane_xilinx.tcl -notrace ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source ariane_xilinx.tcl -notrace Command: open_checkpoint /home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2116.398 ; gain = 0.000 ; free physical = 13973 ; free virtual = 36026 INFO: [Device 21-403] Loading part xc7k325tffg900-2 Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2116.504 ; gain = 0.000 ; free physical = 13356 ; free virtual = 35410 INFO: [Netlist 29-17] Analyzing 6186 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.1 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'i_xlnx_clk_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3059.992 ; gain = 0.000 ; free physical = 12546 ; free virtual = 34600 Restored from archive | CPU: 0.280000 secs | Memory: 1.678932 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3059.992 ; gain = 0.000 ; free physical = 12546 ; free virtual = 34600 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3059.992 ; gain = 0.000 ; free physical = 12559 ; free virtual = 34613 INFO: [Project 1-111] Unisim Transformation Summary: A total of 372 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 26 instances OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 308 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2020.1 (64-bit) build 2902540 open_checkpoint: Time (s): cpu = 00:00:43 ; elapsed = 00:01:00 . Memory (MB): peak = 3059.992 ; gain = 943.594 ; free physical = 12559 ; free virtual = 34613 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 12 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3183.855 ; gain = 115.859 ; free physical = 12550 ; free virtual = 34604 Starting Cache Timing Information Task Ending Cache Timing Information Task | Checksum: 6bceef57 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.37 . Memory (MB): peak = 3183.855 ; gain = 0.000 ; free physical = 12546 ; free virtual = 34600 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 3 inverter(s) to 3 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 10f94574a Time (s): cpu = 00:00:16 ; elapsed = 00:00:07 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12567 ; free virtual = 34621 INFO: [Opt 31-389] Phase Retarget created 397 cells and removed 687 cells INFO: [Opt 31-1021] In phase Retarget, 211 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 22 inverter(s) to 59 load pin(s). Phase 2 Constant propagation | Checksum: 173c45773 Time (s): cpu = 00:00:19 ; elapsed = 00:00:11 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12565 ; free virtual = 34619 INFO: [Opt 31-389] Phase Constant propagation created 597 cells and removed 1320 cells INFO: [Opt 31-1021] In phase Constant propagation, 166 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Sweep Phase 3 Sweep | Checksum: d6d07329 Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12558 ; free virtual = 34612 INFO: [Opt 31-389] Phase Sweep created 9 cells and removed 2302 cells INFO: [Opt 31-1021] In phase Sweep, 751 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets INFO: [Opt 31-129] Inserted BUFG to drive high-fanout reset|set|enable net. BUFG cell: i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]_0_BUFG_inst, Net: i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]_0 Phase 4 BUFG optimization | Checksum: a5898896 Time (s): cpu = 00:00:28 ; elapsed = 00:00:19 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12559 ; free virtual = 34613 INFO: [Opt 31-662] Phase BUFG optimization created 2 cells of which 1 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: a5898896 Time (s): cpu = 00:00:29 ; elapsed = 00:00:21 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12558 ; free virtual = 34612 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 152eeebfb Time (s): cpu = 00:00:30 ; elapsed = 00:00:22 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12557 ; free virtual = 34611 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 197 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 397 | 687 | 211 | | Constant propagation | 597 | 1320 | 166 | | Sweep | 9 | 2302 | 751 | | BUFG optimization | 2 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 1 | 197 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.50 . Memory (MB): peak = 3287.852 ; gain = 0.000 ; free physical = 12557 ; free virtual = 34611 Ending Logic Optimization Task | Checksum: d9e4b752 Time (s): cpu = 00:00:36 ; elapsed = 00:00:27 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12557 ; free virtual = 34611 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 8 BRAM(s) out of a total of 51 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 8 WE to EN ports Number of BRAM Ports augmented: 0 newly gated: 9 Total Ports: 102 Number of Flops added for Enable Generation: 3 Ending PowerOpt Patch Enables Task | Checksum: 12ae88733 Time (s): cpu = 00:00:13 ; elapsed = 00:00:05 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 12370 ; free virtual = 34429 Ending Power Optimization Task | Checksum: 12ae88733 Time (s): cpu = 00:07:24 ; elapsed = 00:06:46 . Memory (MB): peak = 4079.484 ; gain = 791.633 ; free physical = 12458 ; free virtual = 34517 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets Ending Logic Optimization Task | Checksum: e9d94061 Time (s): cpu = 00:00:28 ; elapsed = 00:00:10 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 12470 ; free virtual = 34529 Ending Final Cleanup Task | Checksum: e9d94061 Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 12468 ; free virtual = 34527 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 12468 ; free virtual = 34527 Ending Netlist Obfuscation Task | Checksum: e9d94061 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 12468 ; free virtual = 34527 INFO: [Common 17-83] Releasing license: Implementation 41 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:08:43 ; elapsed = 00:07:37 . Memory (MB): peak = 4079.484 ; gain = 1019.492 ; free physical = 12468 ; free virtual = 34527 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.10 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 12360 ; free virtual = 34421 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:49 ; elapsed = 00:00:31 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 10266 ; free virtual = 32357 INFO: [runtcl-4] Executing : report_drc -file ariane_xilinx_drc_opted.rpt -pb ariane_xilinx_drc_opted.pb -rpx ariane_xilinx_drc_opted.rpx Command: report_drc -file ariane_xilinx_drc_opted.rpt -pb ariane_xilinx_drc_opted.pb -rpx ariane_xilinx_drc_opted.rpx INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.1/data/ip'. INFO: [DRC 23-27] Running DRC with 12 threads INFO: [Coretcl 2-168] The results of DRC are in file /home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:17 ; elapsed = 00:00:08 . Memory (MB): peak = 4246.930 ; gain = 167.445 ; free physical = 12288 ; free virtual = 34384 Command: place_design -directive RuntimeOptimized Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [DRC 23-27] Running DRC with 12 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 12 threads WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][1]_rep) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][1]_rep__0) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][valid]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[5][sbe][ex][cause][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[5][sbe][ex][cause][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[5][sbe][ex][cause][2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[5][sbe][ex][cause][3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[5][sbe][ex][cause][4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_r_spill_reg/spill_register_flushable_i/gen_spill_reg.a_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_r_spill_reg/spill_register_flushable_i/gen_spill_reg.b_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.a_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.b_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[0] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[0] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.a_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[0] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.b_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[1] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[1] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.a_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[1] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.b_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 33 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 12 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11958 ; free virtual = 34046 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 46f16c1c Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11956 ; free virtual = 34044 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11953 ; free virtual = 34041 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device GCIO site IOB_X0Y22 GCIO site IOB_X0Y24 GCIO site IOB_X0Y26 GCIO site IOB_X0Y28 GCIO site IOB_X1Y22 GCIO site IOB_X1Y24 GCIO site IOB_X1Y26 GCIO site IOB_X1Y28 GCIO site IOB_X0Y72 GCIO site IOB_X0Y74 GCIO site IOB_X0Y76 GCIO site IOB_X0Y78 GCIO site IOB_X1Y72 GCIO site IOB_X1Y74 GCIO site IOB_X1Y76 GCIO site IOB_X1Y78 GCIO site IOB_X0Y122 GCIO site IOB_X0Y124 GCIO site IOB_X0Y126 GCIO site IOB_X0Y128 GCIO site IOB_X1Y122 GCIO site IOB_X1Y124 GCIO site IOB_X1Y126 GCIO site IOB_X1Y128 GCIO site IOB_X0Y172 GCIO site IOB_X0Y174 GCIO site IOB_X0Y176 GCIO site IOB_X0Y178 GCIO site IOB_X0Y222 GCIO site IOB_X0Y224 GCIO site IOB_X0Y226 GCIO site IOB_X0Y228 GCIO site IOB_X0Y272 GCIO site IOB_X0Y274 GCIO site IOB_X0Y276 GCIO site IOB_X0Y278 GCIO site IOB_X0Y322 GCIO site IOB_X0Y324 GCIO site IOB_X0Y326 GCIO site IOB_X0Y328 WARNING: [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X1Y76 i_ddr/u_xlnx_mig_7_ddr3_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y3 Resolution: A dedicated routing path between the two can be used if: (a) The clock-capable IO (CCIO) is placed on a CCIO capable site (b) The MMCM is placed in the same clock region as the CCIO pin. If the IOB is driving multiple MMCMs, all MMCMs must be placed in the same clock region, one clock region above or one clock region below the IOB. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1764eb1e2 Time (s): cpu = 00:00:21 ; elapsed = 00:00:14 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 10618 ; free virtual = 32706 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1cd48be52 Time (s): cpu = 00:01:19 ; elapsed = 00:00:37 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 10010 ; free virtual = 32116 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1cd48be52 Time (s): cpu = 00:01:20 ; elapsed = 00:00:38 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 10010 ; free virtual = 32116 Phase 1 Placer Initialization | Checksum: 1cd48be52 Time (s): cpu = 00:01:20 ; elapsed = 00:00:38 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9998 ; free virtual = 32105 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 2568006b8 Time (s): cpu = 00:01:43 ; elapsed = 00:00:46 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9882 ; free virtual = 31995 Phase 2.2 Global Placement Core Phase 2.2 Global Placement Core | Checksum: 11674b988 Time (s): cpu = 00:06:18 ; elapsed = 00:02:41 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9757 ; free virtual = 31933 Phase 2 Global Placement | Checksum: 11674b988 Time (s): cpu = 00:06:18 ; elapsed = 00:02:41 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9823 ; free virtual = 31999 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1e31bef64 Time (s): cpu = 00:06:41 ; elapsed = 00:02:47 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9831 ; free virtual = 32009 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 29cea9fb5 Time (s): cpu = 00:07:16 ; elapsed = 00:02:59 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9810 ; free virtual = 31994 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 28268b50b Time (s): cpu = 00:07:19 ; elapsed = 00:03:01 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9810 ; free virtual = 31994 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1d56e2315 Time (s): cpu = 00:07:19 ; elapsed = 00:03:01 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9810 ; free virtual = 31994 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1a34cfde7 Time (s): cpu = 00:08:24 ; elapsed = 00:04:04 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11721 ; free virtual = 33913 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 18b345702 Time (s): cpu = 00:08:32 ; elapsed = 00:04:12 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11729 ; free virtual = 33920 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 23111f06e Time (s): cpu = 00:08:33 ; elapsed = 00:04:13 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11729 ; free virtual = 33921 Phase 3 Detail Placement | Checksum: 23111f06e Time (s): cpu = 00:08:35 ; elapsed = 00:04:15 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11730 ; free virtual = 33921 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1b1c052ee Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 12 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.201 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 195247ea8 Time (s): cpu = 00:00:21 ; elapsed = 00:00:04 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11706 ; free virtual = 33897 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1ed557303 Time (s): cpu = 00:00:25 ; elapsed = 00:00:05 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11702 ; free virtual = 33894 Phase 4.1.1.1 BUFG Insertion | Checksum: 1b1c052ee Time (s): cpu = 00:10:16 ; elapsed = 00:04:40 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11706 ; free virtual = 33898 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.201. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 1cd6212e2 Time (s): cpu = 00:10:21 ; elapsed = 00:04:45 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11702 ; free virtual = 33894 Phase 4.1 Post Commit Optimization | Checksum: 1cd6212e2 Time (s): cpu = 00:10:23 ; elapsed = 00:04:46 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11702 ; free virtual = 33894 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1cd6212e2 Time (s): cpu = 00:10:25 ; elapsed = 00:04:47 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11708 ; free virtual = 33899 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1cd6212e2 Time (s): cpu = 00:10:26 ; elapsed = 00:04:49 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11709 ; free virtual = 33901 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11709 ; free virtual = 33901 Phase 4.4 Final Placement Cleanup | Checksum: 15ce7f84d Time (s): cpu = 00:10:27 ; elapsed = 00:04:50 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11606 ; free virtual = 33797 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15ce7f84d Time (s): cpu = 00:10:28 ; elapsed = 00:04:51 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11545 ; free virtual = 33737 Ending Placer Task | Checksum: 9f1378ef Time (s): cpu = 00:10:28 ; elapsed = 00:04:51 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11498 ; free virtual = 33689 INFO: [Common 17-83] Releasing license: Implementation 66 Infos, 35 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:10:43 ; elapsed = 00:04:59 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11648 ; free virtual = 33839 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:24 ; elapsed = 00:00:08 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11656 ; free virtual = 34017 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:47 ; elapsed = 00:00:30 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 10376 ; free virtual = 32505 INFO: [runtcl-4] Executing : report_io -file ariane_xilinx_io_placed.rpt report_io: Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.49 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 10312 ; free virtual = 32440 INFO: [runtcl-4] Executing : report_utilization -file ariane_xilinx_utilization_placed.rpt -pb ariane_xilinx_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file ariane_xilinx_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.64 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 10144 ; free virtual = 32273 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 76 Infos, 35 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:11 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9827 ; free virtual = 31964 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:23 ; elapsed = 00:00:08 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9587 ; free virtual = 31903 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:47 ; elapsed = 00:00:30 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9740 ; free virtual = 31940 Command: route_design -directive RuntimeOptimized Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 12 threads GCIO site IOB_X0Y22 GCIO site IOB_X0Y24 GCIO site IOB_X0Y26 GCIO site IOB_X0Y28 GCIO site IOB_X1Y22 GCIO site IOB_X1Y24 GCIO site IOB_X1Y26 GCIO site IOB_X1Y28 GCIO site IOB_X0Y72 GCIO site IOB_X0Y74 GCIO site IOB_X0Y76 GCIO site IOB_X0Y78 GCIO site IOB_X1Y72 GCIO site IOB_X1Y74 GCIO site IOB_X1Y76 GCIO site IOB_X1Y78 GCIO site IOB_X0Y122 GCIO site IOB_X0Y124 GCIO site IOB_X0Y126 GCIO site IOB_X0Y128 GCIO site IOB_X1Y122 GCIO site IOB_X1Y124 GCIO site IOB_X1Y126 GCIO site IOB_X1Y128 GCIO site IOB_X0Y172 GCIO site IOB_X0Y174 GCIO site IOB_X0Y176 GCIO site IOB_X0Y178 GCIO site IOB_X0Y222 GCIO site IOB_X0Y224 GCIO site IOB_X0Y226 GCIO site IOB_X0Y228 GCIO site IOB_X0Y272 GCIO site IOB_X0Y274 GCIO site IOB_X0Y276 GCIO site IOB_X0Y278 GCIO site IOB_X0Y322 GCIO site IOB_X0Y324 GCIO site IOB_X0Y326 GCIO site IOB_X0Y328 WARNING: [DRC PLCK-23] Clock Placer Checks: Sub-optimal placement for a clock-capable IO pin and MMCM pair. Resolution: A dedicated routing path between the two can be used if: (a) The clock-capable IO (CCIO) is placed on a CCIO capable site (b) The MMCM is placed in the same clock region as the CCIO pin. If the IOB is driving multiple MMCMs, all MMCMs must be placed in the same clock region, one clock region above or one clock region below the IOB. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X1Y76 i_ddr/u_xlnx_mig_7_ddr3_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y3 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 84a39d51 ConstDB: 0 ShapeSum: 1a6fdb9e RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 14b9aa420 Time (s): cpu = 00:01:08 ; elapsed = 00:00:22 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9411 ; free virtual = 31629 Post Restoration Checksum: NetGraph: 5467804b NumContArr: f73323d5 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 14b9aa420 Time (s): cpu = 00:01:10 ; elapsed = 00:00:23 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9448 ; free virtual = 31668 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 14b9aa420 Time (s): cpu = 00:01:11 ; elapsed = 00:00:25 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9390 ; free virtual = 31611 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 14b9aa420 Time (s): cpu = 00:01:11 ; elapsed = 00:00:25 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9389 ; free virtual = 31611 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 1da69c6ce Time (s): cpu = 00:02:47 ; elapsed = 00:01:01 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9324 ; free virtual = 31566 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.119 | TNS=0.000 | WHS=-0.473 | THS=-2532.063| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 164c9d4b3 Time (s): cpu = 00:04:10 ; elapsed = 00:01:21 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9295 ; free virtual = 31545 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.119 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 1d98b961e Time (s): cpu = 00:04:11 ; elapsed = 00:01:21 . Memory (MB): peak = 4254.332 ; gain = 7.402 ; free physical = 9292 ; free virtual = 31543 Phase 2 Router Initialization | Checksum: 12d710387 Time (s): cpu = 00:04:11 ; elapsed = 00:01:22 . Memory (MB): peak = 4254.332 ; gain = 7.402 ; free physical = 9292 ; free virtual = 31543 Router Utilization Summary Global Vertical Routing Utilization = 0.00228417 % Global Horizontal Routing Utilization = 0.00398333 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 112369 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 112367 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: af9635c4 Time (s): cpu = 00:05:34 ; elapsed = 00:01:43 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 9260 ; free virtual = 31520 INFO: [Route 35-580] Design has 64 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | oserdes_clk_1 | oserdes_clkdiv_1 |i_ddr/u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.ddr.oserdes_dq_i/RST| | oserdes_clk_2 | oserdes_clkdiv_2 |i_ddr/u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[4].oserdes_dq_.ddr.oserdes_dq_i/RST| | oserdes_clk_6 | oserdes_clkdiv_6 |i_ddr/u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[4].oserdes_dq_.sdr.oserdes_dq_i/RST| | oserdes_clk_2 | oserdes_clkdiv_2 |i_ddr/u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST| | oserdes_clk_6 | oserdes_clkdiv_6 |i_ddr/u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/RST| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 22874 Number of Nodes with overlaps = 2818 Number of Nodes with overlaps = 769 Number of Nodes with overlaps = 297 Number of Nodes with overlaps = 119 Number of Nodes with overlaps = 68 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.119 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1e98eb886 Time (s): cpu = 00:13:40 ; elapsed = 00:04:41 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11295 ; free virtual = 33568 Phase 4 Rip-up And Reroute | Checksum: 1e98eb886 Time (s): cpu = 00:13:40 ; elapsed = 00:04:41 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11295 ; free virtual = 33568 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 1e98eb886 Time (s): cpu = 00:13:41 ; elapsed = 00:04:42 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11295 ; free virtual = 33568 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1e98eb886 Time (s): cpu = 00:13:41 ; elapsed = 00:04:42 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11295 ; free virtual = 33568 Phase 5 Delay and Skew Optimization | Checksum: 1e98eb886 Time (s): cpu = 00:13:42 ; elapsed = 00:04:43 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11295 ; free virtual = 33568 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 17ba27433 Time (s): cpu = 00:14:12 ; elapsed = 00:04:51 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11295 ; free virtual = 33567 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.119 | TNS=0.000 | WHS=0.056 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 21f3ba679 Time (s): cpu = 00:14:12 ; elapsed = 00:04:52 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11294 ; free virtual = 33567 Phase 6 Post Hold Fix | Checksum: 21f3ba679 Time (s): cpu = 00:14:13 ; elapsed = 00:04:52 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11294 ; free virtual = 33567 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 9.71034 % Global Horizontal Routing Utilization = 11.593 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 1b93aa2b6 Time (s): cpu = 00:14:14 ; elapsed = 00:04:53 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11293 ; free virtual = 33565 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b93aa2b6 Time (s): cpu = 00:14:15 ; elapsed = 00:04:54 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11290 ; free virtual = 33563 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1dd52059a Time (s): cpu = 00:14:26 ; elapsed = 00:05:05 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11289 ; free virtual = 33562 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.119 | TNS=0.000 | WHS=0.056 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 1dd52059a Time (s): cpu = 00:14:27 ; elapsed = 00:05:06 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11297 ; free virtual = 33570 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:14:27 ; elapsed = 00:05:06 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11401 ; free virtual = 33674 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 94 Infos, 36 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:14:45 ; elapsed = 00:05:15 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11401 ; free virtual = 33674 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 4293.336 ; gain = 0.000 ; free physical = 11142 ; free virtual = 33630 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:49 ; elapsed = 00:00:31 . Memory (MB): peak = 4293.336 ; gain = 8.004 ; free physical = 11147 ; free virtual = 33411 INFO: [runtcl-4] Executing : report_drc -file ariane_xilinx_drc_routed.rpt -pb ariane_xilinx_drc_routed.pb -rpx ariane_xilinx_drc_routed.rpx Command: report_drc -file ariane_xilinx_drc_routed.rpt -pb ariane_xilinx_drc_routed.pb -rpx ariane_xilinx_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 12 threads GCIO site IOB_X0Y22 GCIO site IOB_X0Y24 GCIO site IOB_X0Y26 GCIO site IOB_X0Y28 GCIO site IOB_X1Y22 GCIO site IOB_X1Y24 GCIO site IOB_X1Y26 GCIO site IOB_X1Y28 GCIO site IOB_X0Y72 GCIO site IOB_X0Y74 GCIO site IOB_X0Y76 GCIO site IOB_X0Y78 GCIO site IOB_X1Y72 GCIO site IOB_X1Y74 GCIO site IOB_X1Y76 GCIO site IOB_X1Y78 GCIO site IOB_X0Y122 GCIO site IOB_X0Y124 GCIO site IOB_X0Y126 GCIO site IOB_X0Y128 GCIO site IOB_X1Y122 GCIO site IOB_X1Y124 GCIO site IOB_X1Y126 GCIO site IOB_X1Y128 GCIO site IOB_X0Y172 GCIO site IOB_X0Y174 GCIO site IOB_X0Y176 GCIO site IOB_X0Y178 GCIO site IOB_X0Y222 GCIO site IOB_X0Y224 GCIO site IOB_X0Y226 GCIO site IOB_X0Y228 GCIO site IOB_X0Y272 GCIO site IOB_X0Y274 GCIO site IOB_X0Y276 GCIO site IOB_X0Y278 GCIO site IOB_X0Y322 GCIO site IOB_X0Y324 GCIO site IOB_X0Y326 GCIO site IOB_X0Y328 INFO: [Coretcl 2-168] The results of DRC are in file /home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:39 ; elapsed = 00:00:10 . Memory (MB): peak = 4597.000 ; gain = 303.664 ; free physical = 11289 ; free virtual = 33614 INFO: [runtcl-4] Executing : report_methodology -file ariane_xilinx_methodology_drc_routed.rpt -pb ariane_xilinx_methodology_drc_routed.pb -rpx ariane_xilinx_methodology_drc_routed.rpx Command: report_methodology -file ariane_xilinx_methodology_drc_routed.rpt -pb ariane_xilinx_methodology_drc_routed.pb -rpx ariane_xilinx_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 12 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:02:09 ; elapsed = 00:00:32 . Memory (MB): peak = 4648.957 ; gain = 51.957 ; free physical = 9238 ; free virtual = 31469 INFO: [runtcl-4] Executing : report_power -file ariane_xilinx_power_routed.rpt -pb ariane_xilinx_power_summary_routed.pb -rpx ariane_xilinx_power_routed.rpx Command: report_power -file ariane_xilinx_power_routed.rpt -pb ariane_xilinx_power_summary_routed.pb -rpx ariane_xilinx_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation 107 Infos, 36 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:02:01 ; elapsed = 00:00:45 . Memory (MB): peak = 4745.023 ; gain = 96.066 ; free physical = 9128 ; free virtual = 31400 INFO: [runtcl-4] Executing : report_route_status -file ariane_xilinx_route_status.rpt -pb ariane_xilinx_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file ariane_xilinx_timing_summary_routed.rpt -pb ariane_xilinx_timing_summary_routed.pb -rpx ariane_xilinx_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. INFO: [runtcl-4] Executing : report_incremental_reuse -file ariane_xilinx_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file ariane_xilinx_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4745.023 ; gain = 0.000 ; free physical = 9081 ; free virtual = 31373 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file ariane_xilinx_bus_skew_routed.rpt -pb ariane_xilinx_bus_skew_routed.pb -rpx ariane_xilinx_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 09:50:16 2023... [Tue Oct 10 09:50:31 2023] impl_1 finished wait_on_run: Time (s): cpu = 00:00:03 ; elapsed = 00:23:22 . Memory (MB): peak = 4292.438 ; gain = 0.000 ; free physical = 11863 ; free virtual = 34171 # launch_runs impl_1 -to_step write_bitstream INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_clk_gen/xlnx_clk_gen.srcs/sources_1/ip/xlnx_clk_gen/xlnx_clk_gen.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.srcs/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xci' is already up-to-date INFO: [Vivado 12-4149] The synthesis checkpoint for IP '/home/darshak/cva6/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.srcs/sources_1/ip/xlnx_axi_dwidth_converter/xlnx_axi_dwidth_converter.xci' is already up-to-date [Tue Oct 10 09:50:33 2023] Launched impl_1... Run output will be captured here: /home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/runme.log # wait_on_run impl_1 [Tue Oct 10 09:50:33 2023] Waiting for impl_1 to finish... *** Running vivado with args -log ariane_xilinx.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source ariane_xilinx.tcl -notrace ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source ariane_xilinx.tcl -notrace Command: open_checkpoint /home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2116.398 ; gain = 0.000 ; free physical = 13973 ; free virtual = 36026 INFO: [Device 21-403] Loading part xc7k325tffg900-2 Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2116.504 ; gain = 0.000 ; free physical = 13356 ; free virtual = 35410 INFO: [Netlist 29-17] Analyzing 6186 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.1 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'i_xlnx_clk_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3059.992 ; gain = 0.000 ; free physical = 12546 ; free virtual = 34600 Restored from archive | CPU: 0.280000 secs | Memory: 1.678932 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3059.992 ; gain = 0.000 ; free physical = 12546 ; free virtual = 34600 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3059.992 ; gain = 0.000 ; free physical = 12559 ; free virtual = 34613 INFO: [Project 1-111] Unisim Transformation Summary: A total of 372 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 26 instances OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 308 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2020.1 (64-bit) build 2902540 open_checkpoint: Time (s): cpu = 00:00:43 ; elapsed = 00:01:00 . Memory (MB): peak = 3059.992 ; gain = 943.594 ; free physical = 12559 ; free virtual = 34613 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 12 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 3183.855 ; gain = 115.859 ; free physical = 12550 ; free virtual = 34604 Starting Cache Timing Information Task Ending Cache Timing Information Task | Checksum: 6bceef57 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.37 . Memory (MB): peak = 3183.855 ; gain = 0.000 ; free physical = 12546 ; free virtual = 34600 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 3 inverter(s) to 3 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 10f94574a Time (s): cpu = 00:00:16 ; elapsed = 00:00:07 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12567 ; free virtual = 34621 INFO: [Opt 31-389] Phase Retarget created 397 cells and removed 687 cells INFO: [Opt 31-1021] In phase Retarget, 211 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 22 inverter(s) to 59 load pin(s). Phase 2 Constant propagation | Checksum: 173c45773 Time (s): cpu = 00:00:19 ; elapsed = 00:00:11 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12565 ; free virtual = 34619 INFO: [Opt 31-389] Phase Constant propagation created 597 cells and removed 1320 cells INFO: [Opt 31-1021] In phase Constant propagation, 166 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Sweep Phase 3 Sweep | Checksum: d6d07329 Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12558 ; free virtual = 34612 INFO: [Opt 31-389] Phase Sweep created 9 cells and removed 2302 cells INFO: [Opt 31-1021] In phase Sweep, 751 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets INFO: [Opt 31-129] Inserted BUFG to drive high-fanout reset|set|enable net. BUFG cell: i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]_0_BUFG_inst, Net: i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]_0 Phase 4 BUFG optimization | Checksum: a5898896 Time (s): cpu = 00:00:28 ; elapsed = 00:00:19 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12559 ; free virtual = 34613 INFO: [Opt 31-662] Phase BUFG optimization created 2 cells of which 1 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: a5898896 Time (s): cpu = 00:00:29 ; elapsed = 00:00:21 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12558 ; free virtual = 34612 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 152eeebfb Time (s): cpu = 00:00:30 ; elapsed = 00:00:22 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12557 ; free virtual = 34611 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 197 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 397 | 687 | 211 | | Constant propagation | 597 | 1320 | 166 | | Sweep | 9 | 2302 | 751 | | BUFG optimization | 2 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 1 | 197 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.50 . Memory (MB): peak = 3287.852 ; gain = 0.000 ; free physical = 12557 ; free virtual = 34611 Ending Logic Optimization Task | Checksum: d9e4b752 Time (s): cpu = 00:00:36 ; elapsed = 00:00:27 . Memory (MB): peak = 3287.852 ; gain = 56.027 ; free physical = 12557 ; free virtual = 34611 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 8 BRAM(s) out of a total of 51 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-201] Structural ODC has moved 8 WE to EN ports Number of BRAM Ports augmented: 0 newly gated: 9 Total Ports: 102 Number of Flops added for Enable Generation: 3 Ending PowerOpt Patch Enables Task | Checksum: 12ae88733 Time (s): cpu = 00:00:13 ; elapsed = 00:00:05 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 12370 ; free virtual = 34429 Ending Power Optimization Task | Checksum: 12ae88733 Time (s): cpu = 00:07:24 ; elapsed = 00:06:46 . Memory (MB): peak = 4079.484 ; gain = 791.633 ; free physical = 12458 ; free virtual = 34517 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets Ending Logic Optimization Task | Checksum: e9d94061 Time (s): cpu = 00:00:28 ; elapsed = 00:00:10 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 12470 ; free virtual = 34529 Ending Final Cleanup Task | Checksum: e9d94061 Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 12468 ; free virtual = 34527 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 12468 ; free virtual = 34527 Ending Netlist Obfuscation Task | Checksum: e9d94061 Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 12468 ; free virtual = 34527 INFO: [Common 17-83] Releasing license: Implementation 41 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:08:43 ; elapsed = 00:07:37 . Memory (MB): peak = 4079.484 ; gain = 1019.492 ; free physical = 12468 ; free virtual = 34527 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.10 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 12360 ; free virtual = 34421 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:49 ; elapsed = 00:00:31 . Memory (MB): peak = 4079.484 ; gain = 0.000 ; free physical = 10266 ; free virtual = 32357 INFO: [runtcl-4] Executing : report_drc -file ariane_xilinx_drc_opted.rpt -pb ariane_xilinx_drc_opted.pb -rpx ariane_xilinx_drc_opted.rpx Command: report_drc -file ariane_xilinx_drc_opted.rpt -pb ariane_xilinx_drc_opted.pb -rpx ariane_xilinx_drc_opted.rpx INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.1/data/ip'. INFO: [DRC 23-27] Running DRC with 12 threads INFO: [Coretcl 2-168] The results of DRC are in file /home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:17 ; elapsed = 00:00:08 . Memory (MB): peak = 4246.930 ; gain = 167.445 ; free physical = 12288 ; free virtual = 34384 Command: place_design -directive RuntimeOptimized Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [DRC 23-27] Running DRC with 12 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 12 threads WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][1]_rep) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][1]_rep__0) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/ex_stage_i/csr_buffer_i/csr_reg_q_reg[csr_address][9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][valid]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[5][sbe][ex][cause][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[5][sbe][ex][cause][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[5][sbe][ex][cause][2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[5][sbe][ex][cause][3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[5][sbe][ex][cause][4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_r_spill_reg/spill_register_flushable_i/gen_spill_reg.a_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_r_spill_reg/spill_register_flushable_i/gen_spill_reg.b_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.a_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.b_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[0] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[0] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.a_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[0] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.b_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[1] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[1] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.a_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[1] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.b_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 33 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 46-5] The placer was invoked with the 'RuntimeOptimized' directive. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 12 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11958 ; free virtual = 34046 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 46f16c1c Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11956 ; free virtual = 34044 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11953 ; free virtual = 34041 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device GCIO site IOB_X0Y22 GCIO site IOB_X0Y24 GCIO site IOB_X0Y26 GCIO site IOB_X0Y28 GCIO site IOB_X1Y22 GCIO site IOB_X1Y24 GCIO site IOB_X1Y26 GCIO site IOB_X1Y28 GCIO site IOB_X0Y72 GCIO site IOB_X0Y74 GCIO site IOB_X0Y76 GCIO site IOB_X0Y78 GCIO site IOB_X1Y72 GCIO site IOB_X1Y74 GCIO site IOB_X1Y76 GCIO site IOB_X1Y78 GCIO site IOB_X0Y122 GCIO site IOB_X0Y124 GCIO site IOB_X0Y126 GCIO site IOB_X0Y128 GCIO site IOB_X1Y122 GCIO site IOB_X1Y124 GCIO site IOB_X1Y126 GCIO site IOB_X1Y128 GCIO site IOB_X0Y172 GCIO site IOB_X0Y174 GCIO site IOB_X0Y176 GCIO site IOB_X0Y178 GCIO site IOB_X0Y222 GCIO site IOB_X0Y224 GCIO site IOB_X0Y226 GCIO site IOB_X0Y228 GCIO site IOB_X0Y272 GCIO site IOB_X0Y274 GCIO site IOB_X0Y276 GCIO site IOB_X0Y278 GCIO site IOB_X0Y322 GCIO site IOB_X0Y324 GCIO site IOB_X0Y326 GCIO site IOB_X0Y328 WARNING: [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X1Y76 i_ddr/u_xlnx_mig_7_ddr3_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y3 Resolution: A dedicated routing path between the two can be used if: (a) The clock-capable IO (CCIO) is placed on a CCIO capable site (b) The MMCM is placed in the same clock region as the CCIO pin. If the IOB is driving multiple MMCMs, all MMCMs must be placed in the same clock region, one clock region above or one clock region below the IOB. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1764eb1e2 Time (s): cpu = 00:00:21 ; elapsed = 00:00:14 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 10618 ; free virtual = 32706 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1cd48be52 Time (s): cpu = 00:01:19 ; elapsed = 00:00:37 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 10010 ; free virtual = 32116 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1cd48be52 Time (s): cpu = 00:01:20 ; elapsed = 00:00:38 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 10010 ; free virtual = 32116 Phase 1 Placer Initialization | Checksum: 1cd48be52 Time (s): cpu = 00:01:20 ; elapsed = 00:00:38 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9998 ; free virtual = 32105 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 2568006b8 Time (s): cpu = 00:01:43 ; elapsed = 00:00:46 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9882 ; free virtual = 31995 Phase 2.2 Global Placement Core Phase 2.2 Global Placement Core | Checksum: 11674b988 Time (s): cpu = 00:06:18 ; elapsed = 00:02:41 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9757 ; free virtual = 31933 Phase 2 Global Placement | Checksum: 11674b988 Time (s): cpu = 00:06:18 ; elapsed = 00:02:41 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9823 ; free virtual = 31999 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1e31bef64 Time (s): cpu = 00:06:41 ; elapsed = 00:02:47 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9831 ; free virtual = 32009 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 29cea9fb5 Time (s): cpu = 00:07:16 ; elapsed = 00:02:59 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9810 ; free virtual = 31994 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 28268b50b Time (s): cpu = 00:07:19 ; elapsed = 00:03:01 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9810 ; free virtual = 31994 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1d56e2315 Time (s): cpu = 00:07:19 ; elapsed = 00:03:01 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9810 ; free virtual = 31994 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1a34cfde7 Time (s): cpu = 00:08:24 ; elapsed = 00:04:04 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11721 ; free virtual = 33913 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 18b345702 Time (s): cpu = 00:08:32 ; elapsed = 00:04:12 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11729 ; free virtual = 33920 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 23111f06e Time (s): cpu = 00:08:33 ; elapsed = 00:04:13 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11729 ; free virtual = 33921 Phase 3 Detail Placement | Checksum: 23111f06e Time (s): cpu = 00:08:35 ; elapsed = 00:04:15 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11730 ; free virtual = 33921 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1b1c052ee Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 12 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.201 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 195247ea8 Time (s): cpu = 00:00:21 ; elapsed = 00:00:04 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11706 ; free virtual = 33897 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. Ending Physical Synthesis Task | Checksum: 1ed557303 Time (s): cpu = 00:00:25 ; elapsed = 00:00:05 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11702 ; free virtual = 33894 Phase 4.1.1.1 BUFG Insertion | Checksum: 1b1c052ee Time (s): cpu = 00:10:16 ; elapsed = 00:04:40 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11706 ; free virtual = 33898 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.201. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 1cd6212e2 Time (s): cpu = 00:10:21 ; elapsed = 00:04:45 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11702 ; free virtual = 33894 Phase 4.1 Post Commit Optimization | Checksum: 1cd6212e2 Time (s): cpu = 00:10:23 ; elapsed = 00:04:46 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11702 ; free virtual = 33894 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1cd6212e2 Time (s): cpu = 00:10:25 ; elapsed = 00:04:47 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11708 ; free virtual = 33899 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1cd6212e2 Time (s): cpu = 00:10:26 ; elapsed = 00:04:49 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11709 ; free virtual = 33901 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11709 ; free virtual = 33901 Phase 4.4 Final Placement Cleanup | Checksum: 15ce7f84d Time (s): cpu = 00:10:27 ; elapsed = 00:04:50 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11606 ; free virtual = 33797 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15ce7f84d Time (s): cpu = 00:10:28 ; elapsed = 00:04:51 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11545 ; free virtual = 33737 Ending Placer Task | Checksum: 9f1378ef Time (s): cpu = 00:10:28 ; elapsed = 00:04:51 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11498 ; free virtual = 33689 INFO: [Common 17-83] Releasing license: Implementation 66 Infos, 35 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:10:43 ; elapsed = 00:04:59 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11648 ; free virtual = 33839 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:24 ; elapsed = 00:00:08 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 11656 ; free virtual = 34017 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:47 ; elapsed = 00:00:30 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 10376 ; free virtual = 32505 INFO: [runtcl-4] Executing : report_io -file ariane_xilinx_io_placed.rpt report_io: Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.49 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 10312 ; free virtual = 32440 INFO: [runtcl-4] Executing : report_utilization -file ariane_xilinx_utilization_placed.rpt -pb ariane_xilinx_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file ariane_xilinx_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.64 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 10144 ; free virtual = 32273 Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. INFO: [Common 17-83] Releasing license: Implementation 76 Infos, 35 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully phys_opt_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:11 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9827 ; free virtual = 31964 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:23 ; elapsed = 00:00:08 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9587 ; free virtual = 31903 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_physopt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:47 ; elapsed = 00:00:30 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9740 ; free virtual = 31940 Command: route_design -directive RuntimeOptimized Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 12 threads GCIO site IOB_X0Y22 GCIO site IOB_X0Y24 GCIO site IOB_X0Y26 GCIO site IOB_X0Y28 GCIO site IOB_X1Y22 GCIO site IOB_X1Y24 GCIO site IOB_X1Y26 GCIO site IOB_X1Y28 GCIO site IOB_X0Y72 GCIO site IOB_X0Y74 GCIO site IOB_X0Y76 GCIO site IOB_X0Y78 GCIO site IOB_X1Y72 GCIO site IOB_X1Y74 GCIO site IOB_X1Y76 GCIO site IOB_X1Y78 GCIO site IOB_X0Y122 GCIO site IOB_X0Y124 GCIO site IOB_X0Y126 GCIO site IOB_X0Y128 GCIO site IOB_X1Y122 GCIO site IOB_X1Y124 GCIO site IOB_X1Y126 GCIO site IOB_X1Y128 GCIO site IOB_X0Y172 GCIO site IOB_X0Y174 GCIO site IOB_X0Y176 GCIO site IOB_X0Y178 GCIO site IOB_X0Y222 GCIO site IOB_X0Y224 GCIO site IOB_X0Y226 GCIO site IOB_X0Y228 GCIO site IOB_X0Y272 GCIO site IOB_X0Y274 GCIO site IOB_X0Y276 GCIO site IOB_X0Y278 GCIO site IOB_X0Y322 GCIO site IOB_X0Y324 GCIO site IOB_X0Y326 GCIO site IOB_X0Y328 WARNING: [DRC PLCK-23] Clock Placer Checks: Sub-optimal placement for a clock-capable IO pin and MMCM pair. Resolution: A dedicated routing path between the two can be used if: (a) The clock-capable IO (CCIO) is placed on a CCIO capable site (b) The MMCM is placed in the same clock region as the CCIO pin. If the IOB is driving multiple MMCMs, all MMCMs must be placed in the same clock region, one clock region above or one clock region below the IOB. Both the above conditions must be met at the same time, else it may lead to longer and less predictable clock insertion delays. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X1Y76 i_ddr/u_xlnx_mig_7_ddr3_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y3 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-270] Using Router directive 'RuntimeOptimized'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 84a39d51 ConstDB: 0 ShapeSum: 1a6fdb9e RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 14b9aa420 Time (s): cpu = 00:01:08 ; elapsed = 00:00:22 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9411 ; free virtual = 31629 Post Restoration Checksum: NetGraph: 5467804b NumContArr: f73323d5 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: 14b9aa420 Time (s): cpu = 00:01:10 ; elapsed = 00:00:23 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9448 ; free virtual = 31668 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: 14b9aa420 Time (s): cpu = 00:01:11 ; elapsed = 00:00:25 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9390 ; free virtual = 31611 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: 14b9aa420 Time (s): cpu = 00:01:11 ; elapsed = 00:00:25 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9389 ; free virtual = 31611 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 1da69c6ce Time (s): cpu = 00:02:47 ; elapsed = 00:01:01 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9324 ; free virtual = 31566 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.119 | TNS=0.000 | WHS=-0.473 | THS=-2532.063| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing Phase 2.5.1 Update Timing | Checksum: 164c9d4b3 Time (s): cpu = 00:04:10 ; elapsed = 00:01:21 . Memory (MB): peak = 4246.930 ; gain = 0.000 ; free physical = 9295 ; free virtual = 31545 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.119 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 2.5 Update Timing for Bus Skew | Checksum: 1d98b961e Time (s): cpu = 00:04:11 ; elapsed = 00:01:21 . Memory (MB): peak = 4254.332 ; gain = 7.402 ; free physical = 9292 ; free virtual = 31543 Phase 2 Router Initialization | Checksum: 12d710387 Time (s): cpu = 00:04:11 ; elapsed = 00:01:22 . Memory (MB): peak = 4254.332 ; gain = 7.402 ; free physical = 9292 ; free virtual = 31543 Router Utilization Summary Global Vertical Routing Utilization = 0.00228417 % Global Horizontal Routing Utilization = 0.00398333 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 112369 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 112367 Number of Partially Routed Nets = 2 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: af9635c4 Time (s): cpu = 00:05:34 ; elapsed = 00:01:43 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 9260 ; free virtual = 31520 INFO: [Route 35-580] Design has 64 pins with tight setup and hold constraints. The top 5 pins with tight setup and hold constraints: +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | Launch Clock | Capture Clock | Pin | +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ | oserdes_clk_1 | oserdes_clkdiv_1 |i_ddr/u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.ddr.oserdes_dq_i/RST| | oserdes_clk_2 | oserdes_clkdiv_2 |i_ddr/u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[4].oserdes_dq_.ddr.oserdes_dq_i/RST| | oserdes_clk_6 | oserdes_clkdiv_6 |i_ddr/u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[4].oserdes_dq_.sdr.oserdes_dq_i/RST| | oserdes_clk_2 | oserdes_clkdiv_2 |i_ddr/u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST| | oserdes_clk_6 | oserdes_clkdiv_6 |i_ddr/u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/RST| +--------------------------+--------------------------+----------------------------------------------------------------------------------------------------------+ File with complete list of pins: tight_setup_hold_pins.txt Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 22874 Number of Nodes with overlaps = 2818 Number of Nodes with overlaps = 769 Number of Nodes with overlaps = 297 Number of Nodes with overlaps = 119 Number of Nodes with overlaps = 68 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.119 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1e98eb886 Time (s): cpu = 00:13:40 ; elapsed = 00:04:41 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11295 ; free virtual = 33568 Phase 4 Rip-up And Reroute | Checksum: 1e98eb886 Time (s): cpu = 00:13:40 ; elapsed = 00:04:41 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11295 ; free virtual = 33568 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 1e98eb886 Time (s): cpu = 00:13:41 ; elapsed = 00:04:42 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11295 ; free virtual = 33568 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1e98eb886 Time (s): cpu = 00:13:41 ; elapsed = 00:04:42 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11295 ; free virtual = 33568 Phase 5 Delay and Skew Optimization | Checksum: 1e98eb886 Time (s): cpu = 00:13:42 ; elapsed = 00:04:43 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11295 ; free virtual = 33568 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 17ba27433 Time (s): cpu = 00:14:12 ; elapsed = 00:04:51 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11295 ; free virtual = 33567 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.119 | TNS=0.000 | WHS=0.056 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 21f3ba679 Time (s): cpu = 00:14:12 ; elapsed = 00:04:52 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11294 ; free virtual = 33567 Phase 6 Post Hold Fix | Checksum: 21f3ba679 Time (s): cpu = 00:14:13 ; elapsed = 00:04:52 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11294 ; free virtual = 33567 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 9.71034 % Global Horizontal Routing Utilization = 11.593 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 1b93aa2b6 Time (s): cpu = 00:14:14 ; elapsed = 00:04:53 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11293 ; free virtual = 33565 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b93aa2b6 Time (s): cpu = 00:14:15 ; elapsed = 00:04:54 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11290 ; free virtual = 33563 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1dd52059a Time (s): cpu = 00:14:26 ; elapsed = 00:05:05 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11289 ; free virtual = 33562 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=0.119 | TNS=0.000 | WHS=0.056 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 1dd52059a Time (s): cpu = 00:14:27 ; elapsed = 00:05:06 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11297 ; free virtual = 33570 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:14:27 ; elapsed = 00:05:06 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11401 ; free virtual = 33674 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 94 Infos, 36 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:14:45 ; elapsed = 00:05:15 . Memory (MB): peak = 4285.332 ; gain = 38.402 ; free physical = 11401 ; free virtual = 33674 INFO: [Common 17-600] The following parameters have non-default value. general.maxThreads INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 4293.336 ; gain = 0.000 ; free physical = 11142 ; free virtual = 33630 INFO: [Common 17-1381] The checkpoint '/home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:49 ; elapsed = 00:00:31 . Memory (MB): peak = 4293.336 ; gain = 8.004 ; free physical = 11147 ; free virtual = 33411 INFO: [runtcl-4] Executing : report_drc -file ariane_xilinx_drc_routed.rpt -pb ariane_xilinx_drc_routed.pb -rpx ariane_xilinx_drc_routed.rpx Command: report_drc -file ariane_xilinx_drc_routed.rpt -pb ariane_xilinx_drc_routed.pb -rpx ariane_xilinx_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 12 threads GCIO site IOB_X0Y22 GCIO site IOB_X0Y24 GCIO site IOB_X0Y26 GCIO site IOB_X0Y28 GCIO site IOB_X1Y22 GCIO site IOB_X1Y24 GCIO site IOB_X1Y26 GCIO site IOB_X1Y28 GCIO site IOB_X0Y72 GCIO site IOB_X0Y74 GCIO site IOB_X0Y76 GCIO site IOB_X0Y78 GCIO site IOB_X1Y72 GCIO site IOB_X1Y74 GCIO site IOB_X1Y76 GCIO site IOB_X1Y78 GCIO site IOB_X0Y122 GCIO site IOB_X0Y124 GCIO site IOB_X0Y126 GCIO site IOB_X0Y128 GCIO site IOB_X1Y122 GCIO site IOB_X1Y124 GCIO site IOB_X1Y126 GCIO site IOB_X1Y128 GCIO site IOB_X0Y172 GCIO site IOB_X0Y174 GCIO site IOB_X0Y176 GCIO site IOB_X0Y178 GCIO site IOB_X0Y222 GCIO site IOB_X0Y224 GCIO site IOB_X0Y226 GCIO site IOB_X0Y228 GCIO site IOB_X0Y272 GCIO site IOB_X0Y274 GCIO site IOB_X0Y276 GCIO site IOB_X0Y278 GCIO site IOB_X0Y322 GCIO site IOB_X0Y324 GCIO site IOB_X0Y326 GCIO site IOB_X0Y328 INFO: [Coretcl 2-168] The results of DRC are in file /home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:39 ; elapsed = 00:00:10 . Memory (MB): peak = 4597.000 ; gain = 303.664 ; free physical = 11289 ; free virtual = 33614 INFO: [runtcl-4] Executing : report_methodology -file ariane_xilinx_methodology_drc_routed.rpt -pb ariane_xilinx_methodology_drc_routed.pb -rpx ariane_xilinx_methodology_drc_routed.rpx Command: report_methodology -file ariane_xilinx_methodology_drc_routed.rpt -pb ariane_xilinx_methodology_drc_routed.pb -rpx ariane_xilinx_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 12 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/darshak/cva6/corev_apu/fpga/ariane.runs/impl_1/ariane_xilinx_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:02:09 ; elapsed = 00:00:32 . Memory (MB): peak = 4648.957 ; gain = 51.957 ; free physical = 9238 ; free virtual = 31469 INFO: [runtcl-4] Executing : report_power -file ariane_xilinx_power_routed.rpt -pb ariane_xilinx_power_summary_routed.pb -rpx ariane_xilinx_power_routed.rpx Command: report_power -file ariane_xilinx_power_routed.rpt -pb ariane_xilinx_power_summary_routed.pb -rpx ariane_xilinx_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation 107 Infos, 36 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:02:01 ; elapsed = 00:00:45 . Memory (MB): peak = 4745.023 ; gain = 96.066 ; free physical = 9128 ; free virtual = 31400 INFO: [runtcl-4] Executing : report_route_status -file ariane_xilinx_route_status.rpt -pb ariane_xilinx_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file ariane_xilinx_timing_summary_routed.rpt -pb ariane_xilinx_timing_summary_routed.pb -rpx ariane_xilinx_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. INFO: [runtcl-4] Executing : report_incremental_reuse -file ariane_xilinx_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file ariane_xilinx_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4745.023 ; gain = 0.000 ; free physical = 9081 ; free virtual = 31373 INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file ariane_xilinx_bus_skew_routed.rpt -pb ariane_xilinx_bus_skew_routed.pb -rpx ariane_xilinx_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 09:50:16 2023... *** Running vivado with args -log ariane_xilinx.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source ariane_xilinx.tcl -notrace ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source ariane_xilinx.tcl -notrace Command: open_checkpoint ariane_xilinx_routed.dcp Starting open_checkpoint Task Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2116.398 ; gain = 0.000 ; free physical = 11644 ; free virtual = 33960 INFO: [Device 21-403] Loading part xc7k325tffg900-2 Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2116.504 ; gain = 0.000 ; free physical = 10998 ; free virtual = 33331 INFO: [Netlist 29-17] Analyzing 6127 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.1 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'i_xlnx_clk_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are: general.maxThreads INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3174.680 ; gain = 121.633 ; free physical = 10027 ; free virtual = 32375 Restored from archive | CPU: 9.860000 secs | Memory: 130.676750 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3174.680 ; gain = 121.633 ; free physical = 10027 ; free virtual = 32375 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3174.680 ; gain = 0.000 ; free physical = 10037 ; free virtual = 32386 INFO: [Project 1-111] Unisim Transformation Summary: A total of 353 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 17 instances OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 298 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2020.1 (64-bit) build 2902540 open_checkpoint: Time (s): cpu = 00:00:58 ; elapsed = 00:01:15 . Memory (MB): peak = 3174.680 ; gain = 1058.281 ; free physical = 10037 ; free virtual = 32386 INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. INFO: [Memdata 28-208] The XPM instance: is part of IP: . This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. Command: write_bitstream -force ariane_xilinx.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.1/data/ip'. INFO: [DRC 23-27] Running DRC with 12 threads GCIO site IOB_X0Y22 GCIO site IOB_X0Y24 GCIO site IOB_X0Y26 GCIO site IOB_X0Y28 GCIO site IOB_X1Y22 GCIO site IOB_X1Y24 GCIO site IOB_X1Y26 GCIO site IOB_X1Y28 GCIO site IOB_X0Y72 GCIO site IOB_X0Y74 GCIO site IOB_X0Y76 GCIO site IOB_X0Y78 GCIO site IOB_X1Y72 GCIO site IOB_X1Y74 GCIO site IOB_X1Y76 GCIO site IOB_X1Y78 GCIO site IOB_X0Y122 GCIO site IOB_X0Y124 GCIO site IOB_X0Y126 GCIO site IOB_X0Y128 GCIO site IOB_X1Y122 GCIO site IOB_X1Y124 GCIO site IOB_X1Y126 GCIO site IOB_X1Y128 GCIO site IOB_X0Y172 GCIO site IOB_X0Y174 GCIO site IOB_X0Y176 GCIO site IOB_X0Y178 GCIO site IOB_X0Y222 GCIO site IOB_X0Y224 GCIO site IOB_X0Y226 GCIO site IOB_X0Y228 GCIO site IOB_X0Y272 GCIO site IOB_X0Y274 GCIO site IOB_X0Y276 GCIO site IOB_X0Y278 GCIO site IOB_X0Y322 GCIO site IOB_X0Y324 GCIO site IOB_X0Y326 GCIO site IOB_X0Y328 ERROR: [DRC NSTD-1] Unspecified I/O Standard: 5 out of 117 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: trst_n, tms, tdo, tdi, and tck. ERROR: [DRC UCIO-1] Unconstrained Logical Port: 5 out of 117 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: trst_n, tms, tdo, tdi, and tck. WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__1 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__1 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__2 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__2 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__3 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__3 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__4 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__4 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__5 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__5/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__5 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__5/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__6 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__6/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__6 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__6/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__7 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__7 input i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__7/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__0 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__0 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__10 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__10 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__10/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__12 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__12/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__12 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__12/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__14 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__14/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__14 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__14/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__2 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__2 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__3 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__3 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__5 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__5/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__5 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__5/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__6 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__6/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__6 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__6/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__7 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__7 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__7/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__9 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__9/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPIP-1] Input pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__9 input i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__9/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product output i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0 output i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0 output i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__1 output i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__4 output i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__5 output i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__7 output i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-1] PREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product multiplier stage i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0 multiplier stage i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[0].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0 multiplier stage i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__1 multiplier stage i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__4 multiplier stage i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__5 multiplier stage i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__7 multiplier stage i_ariane/i_cva6/ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/product__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d multiplier stage i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 multiplier stage i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__10 multiplier stage i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 multiplier stage i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 multiplier stage i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__14 multiplier stage i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__14/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__2 multiplier stage i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 multiplier stage i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__6 multiplier stage i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__6/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 multiplier stage i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[0]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[10]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[11]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[12]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[13]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[14]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[15]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[16]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[1]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[2]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[3]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[4]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[5]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[6]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[7]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[8]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__1 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[9]__0). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[0]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[10]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[11]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[12]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[13]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[14]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[15]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[16]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[1]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[2]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[3]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[4]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[5]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[6]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[7]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[8]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__11 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[9]__6). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[0]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[10]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[11]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[12]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[13]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[14]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[15]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[16]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[1]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[2]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[3]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[4]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[5]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[6]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[7]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[8]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__13 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[9]__7). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[0]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[10]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[11]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[12]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[13]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[14]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[15]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[16]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[1]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[2]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[3]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[4]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[5]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[6]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[7]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[8]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__4 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[9]__2). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[0]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[10]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[11]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[12]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[13]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[14]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[15]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[16]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[1]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[2]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[3]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[4]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[5]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[6]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. WARNING: [DRC DPOR-1] Asynchronous load check: DSP i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_d__8 output is connected to registers with an asynchronous reset (i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/mult_result_q_reg[7]__4). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area. INFO: [Common 17-14] Message 'DRC DPOR-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC REQP-1709] Clock output buffering: PLLE2_ADV connectivity violation. The signal i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of i_ddr/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][ex][cause][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][ex][cause][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][ex][cause][2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][ex][cause][3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][ex][cause][4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][ex][cause][63]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][ex][valid]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][fu][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][fu][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][fu][2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][fu][3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][op][0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][op][1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][op][2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][op][3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][op][4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][op][5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][op][6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][op][7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg has an input control pin i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/Mem_DP_reg/ADDRARDADDR[13] (net: i_ariane/i_cva6/i_cache_subsystem/i_cva6_icache/gen_sram[0].data_sram/gen_cut[0].i_tc_sram_wrapper/i_ram/ADDRBWRADDR[7]) which is driven by a register (i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[4][sbe][valid]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_r_spill_reg/spill_register_flushable_i/gen_spill_reg.a_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_r_spill_reg/spill_register_flushable_i/gen_spill_reg.b_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.a_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.b_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[0] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[0] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.a_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[0] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.b_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[1] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[1] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.a_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEA[1] (net: i_ariane_peripherals/gen_spi.i_xlnx_axi_quad_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/ena) which is driven by a register (i_axi_xbar/i_xbar/gen_mst_port_mux[3].i_axi_mux/gen_mux.i_w_spill_reg/spill_register_flushable_i/gen_spill_reg.b_full_q_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC RTSTAT-10] No routable loads: 113 net(s) have no routable loads. The problem bus(es) and/or net(s) are i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, i_xlnx_axi_clock_converter_ddr/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q[resp][1:0], i_ariane_peripherals/gen_spi.i_xlnx_axi_dwidth_converter_spi/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb, i_ariane_peripherals/gen_gpio.i_xlnx_axi_dwidth_converter_gpio/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_afull_fb... and (the first 15 of 68 listed). INFO: [Vivado 12-3199] DRC finished with 2 Errors, 221 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. INFO: [Common 17-83] Releasing license: Implementation 23 Infos, 220 Warnings, 0 Critical Warnings and 3 Errors encountered. write_bitstream failed write_bitstream: Time (s): cpu = 00:01:26 ; elapsed = 00:00:26 . Memory (MB): peak = 3853.570 ; gain = 666.016 ; free physical = 11939 ; free virtual = 34289 ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 09:52:30 2023... [Tue Oct 10 09:52:31 2023] impl_1 finished WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1' wait_on_run: Time (s): cpu = 00:02:41 ; elapsed = 00:01:57 . Memory (MB): peak = 4324.453 ; gain = 0.000 ; free physical = 13859 ; free virtual = 36209 # open_run impl_1 Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4407.184 ; gain = 0.000 ; free physical = 13707 ; free virtual = 36057 INFO: [Netlist 29-17] Analyzing 6127 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2020.1 INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'i_xlnx_clk_gen/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. INFO: [Timing 38-478] Restoring timing data from binary archive. INFO: [Timing 38-479] Binary timing data restore complete. INFO: [Project 1-856] Restoring constraints from binary archive. INFO: [Constraints 18-5170] The checkpoint was created with non-default parameter values which do not match the current Vivado settings. Mismatching parameters are: general.maxThreads INFO: [Project 1-853] Binary constraint restore complete. Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 5009.012 ; gain = 105.633 ; free physical = 13212 ; free virtual = 35562 Restored from archive | CPU: 8.880000 secs | Memory: 129.571999 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 5009.012 ; gain = 105.633 ; free physical = 13212 ; free virtual = 35562 Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5009.012 ; gain = 0.000 ; free physical = 13190 ; free virtual = 35540 INFO: [Project 1-111] Unisim Transformation Summary: A total of 353 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 1 instance IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances LUT6_2 => LUT6_2 (LUT5, LUT6): 17 instances OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 298 instances open_run: Time (s): cpu = 00:00:35 ; elapsed = 00:00:46 . Memory (MB): peak = 5009.012 ; gain = 684.559 ; free physical = 13190 ; free virtual = 35540 # write_verilog -force -mode funcsim work-fpga/${project}_funcsim.v write_verilog: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5009.012 ; gain = 0.000 ; free physical = 13147 ; free virtual = 35557 # write_verilog -force -mode timesim work-fpga/${project}_timesim.v write_verilog: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5030.824 ; gain = 21.812 ; free physical = 13083 ; free virtual = 35553 # write_sdf -force work-fpga/${project}_timesim.sdf write_sdf: Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 5220.059 ; gain = 189.234 ; free physical = 12718 ; free virtual = 35445 # exec mkdir -p reports/ # exec rm -rf reports/* # check_timing -file reports/${project}.check_timing.rpt check_timing: Time (s): cpu = 00:00:45 ; elapsed = 00:00:09 . Memory (MB): peak = 5228.059 ; gain = 8.000 ; free physical = 12690 ; free virtual = 35417 # report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 100 -nworst 100 -delay_type max -sort_by slack. report_timing: Time (s): cpu = 00:00:41 ; elapsed = 00:00:09 . Memory (MB): peak = 5228.059 ; gain = 0.000 ; free physical = 12633 ; free virtual = 35359 # report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by group. # report_utilization -hierarchical -file reports/${project}.utilization.rpt report_utilization: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5228.059 ; gain = 0.000 ; free physical = 12618 ; free virtual = 35345 INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 09:54:45 2023... cp ariane.runs/impl_1/ariane_xilinx* ./work-fpga vivado -nojournal -mode batch -source scripts/prologue.tcl -source scripts/write_cfgmem.tcl -tclargs work-fpga/ariane_xilinx.mcs work-fpga/ariane_xilinx.bit ****** Vivado v2020.1 (64-bit) **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020 **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020 ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. source scripts/prologue.tcl # set project ariane # create_project $project . -force -part $::env(XILINX_PART) # set_property board_part $::env(XILINX_BOARD) [current_project] # set_param general.maxThreads 20 # set_msg_config -id {[Synth 8-5858]} -new_severity "info" # set_msg_config -id {[Synth 8-4480]} -limit 1000 source scripts/write_cfgmem.tcl # if {$argc < 2 || $argc > 4} { # puts $argc # puts {Error: Invalid number of arguments} # puts {Usage: write_cfgmem.tcl mcsfile bitfile [datafile]} # exit 1 # } # lassign $argv mcsfile bitfile # if {$::env(BOARD) eq "genesys2"} { # write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit "up 0x0 $bitfile" -file $mcsfile -force # } elseif {$::env(BOARD) eq "vc707"} { # write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 $bitfile" -file $mcsfile -force # } elseif {$::env(BOARD) eq "kc705"} { # write_cfgmem -format mcs -interface SPIx4 -size 128 -loadbit "up 0x0 $bitfile" -file $mcsfile -force # } else { # exit 1 # } Command: write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit {up 0x0 work-fpga/ariane_xilinx.bit} -file work-fpga/ariane_xilinx.mcs -force Creating config memory files... Creating bitstream load up from address 0x00000000 Loading bitfile work-fpga/ariane_xilinx.bit 0 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered. write_cfgmem failed ERROR: [Common 17-39] 'write_cfgmem' failed due to earlier errors. while executing "write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit "up 0x0 $bitfile" -file $mcsfile -force" invoked from within "if {$::env(BOARD) eq "genesys2"} { write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit "up 0x0 $bitfile" -file $mcsfile -force } elseif ..." (file "scripts/write_cfgmem.tcl" line 29) INFO: [Common 17-206] Exiting Vivado at Tue Oct 10 09:55:13 2023... make[1]: Leaving directory '/home/darshak/cva6/corev_apu/fpga'