Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 | Date : Tue Oct 1 20:49:47 2019 | Host : mescoba1 running 64-bit Linux Mint 18.1 Serena | Command : report_timing_summary -file /home/miguel/hdl-playground/Nexys-Video-HDMI/proj/timing/timing1.txt | Design : hdmi_wrapper | Device : 7a200t-sbg484 | Speed File : -1 PRODUCTION 1.20 2017-11-01 ------------------------------------------------------------------------------------------------------------------ Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 7 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 8 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 3249 register/latch pins with multiple clocks. (HIGH) 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -4.676 -15021.253 6409 84781 -0.373 -0.835 4 84605 -0.455 -6.404 15 36904 Timing constraints are not met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- TMDS_IN_clk_p {0.000 3.030} 6.060 165.017 CLKFBIN {0.000 3.030} 6.060 165.017 CLK_OUT_5x_hdmi_clk {0.000 0.606} 1.212 825.083 dvi2rgb_0_PixelClk {0.000 2.424} 6.060 165.017 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {0.000 16.500} 33.000 30.303 hdmi_i/dvi2rgb_0/U0/RefClk {0.000 2.500} 5.000 200.000 hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK {0.000 16.666} 33.333 30.000 hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE {0.000 16.666} 33.333 30.000 sys_clk_i {0.000 5.000} 10.000 100.000 freq_refclk {0.000 0.625} 1.250 800.000 u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {0.000 1.250} 2.500 400.000 iserdes_clkdiv {0.000 5.000} 10.000 100.000 u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {0.000 1.250} 2.500 400.000 iserdes_clkdiv_1 {0.000 5.000} 10.000 100.000 mem_refclk {0.000 1.250} 2.500 400.000 oserdes_clk {0.000 1.250} 2.500 400.000 oserdes_clkdiv {0.000 5.000} 10.000 100.000 oserdes_clk_1 {0.000 1.250} 2.500 400.000 oserdes_clkdiv_1 {0.000 5.000} 10.000 100.000 oserdes_clk_2 {0.000 1.250} 2.500 400.000 oserdes_clkdiv_2 {0.000 2.500} 5.000 200.000 oserdes_clk_3 {0.000 1.250} 2.500 400.000 oserdes_clkdiv_3 {0.000 2.500} 5.000 200.000 pll_clk3_out {0.000 5.000} 10.000 100.000 clk_pll_i {0.000 5.000} 10.000 100.000 mmcm_clk {0.000 1.000} 2.000 500.000 axi_dynclk_0_PXL_CLK_O {0.000 4.000} 10.000 100.000 mmcm_fbclk_out {0.000 5.000} 10.000 100.000 mmcm_clkout0 {0.000 3.125} 6.250 160.000 mmcm_clkout1 {0.000 2.500} 5.000 200.000 pll_clkfbout {0.000 5.000} 10.000 100.000 sync_pulse {1.094 3.594} 40.000 25.000 tmds_clk_pin {0.000 6.250} 12.500 80.000 CLKFBIN_1 {0.000 6.250} 12.500 80.000 CLK_OUT_5x_hdmi_clk_1 {0.000 1.250} 2.500 400.000 dvi2rgb_0_PixelClk_1 {0.000 5.000} 12.500 80.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- TMDS_IN_clk_p 1.530 0.000 0 1 CLKFBIN 4.811 0.000 0 2 CLK_OUT_5x_hdmi_clk -0.455 -6.404 15 15 dvi2rgb_0_PixelClk 1.833 0.000 0 6290 0.107 0.000 0 6290 1.174 0.000 0 3237 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK 25.837 0.000 0 928 0.084 0.000 0 928 15.250 0.000 0 484 hdmi_i/dvi2rgb_0/U0/RefClk -0.097 -0.152 2 685 0.054 0.000 0 685 0.264 0.000 0 394 hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK 13.359 0.000 0 309 0.062 0.000 0 309 15.686 0.000 0 315 hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE 7.993 0.000 0 104 1.519 0.000 0 104 16.166 0.000 0 95 sys_clk_i 3.000 0.000 0 1 freq_refclk 0.000 0.000 0 8 u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 0.833 0.000 0 16 iserdes_clkdiv 7.875 0.000 0 33 0.071 0.000 0 33 2.850 0.000 0 9 u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 0.833 0.000 0 16 iserdes_clkdiv_1 7.891 0.000 0 33 0.071 0.000 0 33 2.850 0.000 0 9 mem_refclk 1.331 0.000 0 1 0.336 0.000 0 1 0.625 0.000 0 8 oserdes_clk 0.833 0.000 0 12 oserdes_clkdiv 8.041 0.000 0 44 0.090 0.000 0 44 2.850 0.000 0 12 oserdes_clk_1 0.833 0.000 0 12 oserdes_clkdiv_1 8.564 0.000 0 48 0.094 0.000 0 48 2.850 0.000 0 13 oserdes_clk_2 0.913 0.000 0 4 0.413 0.000 0 4 0.833 0.000 0 12 oserdes_clkdiv_2 3.571 0.000 0 36 0.092 0.000 0 36 0.000 0.000 0 11 oserdes_clk_3 0.929 0.000 0 4 0.408 0.000 0 4 0.833 0.000 0 12 oserdes_clkdiv_3 3.587 0.000 0 36 0.086 0.000 0 36 0.000 0.000 0 11 pll_clk3_out 3.000 0.000 0 3 clk_pll_i -0.152 -0.471 6 62395 0.052 0.000 0 62395 2.500 0.000 0 24766 mmcm_clk 0.333 0.000 0 12 axi_dynclk_0_PXL_CLK_O 2.131 0.000 0 5951 0.106 0.000 0 5951 2.750 0.000 0 3041 mmcm_fbclk_out 8.751 0.000 0 2 mmcm_clkout0 0.920 0.000 0 1233 0.104 0.000 0 1233 2.145 0.000 0 626 mmcm_clkout1 -0.975 -18.395 81 6082 0.081 0.000 0 6082 0.264 0.000 0 3739 pll_clkfbout 8.751 0.000 0 2 sync_pulse 1.250 0.000 0 8 tmds_clk_pin 4.750 0.000 0 1 CLKFBIN_1 11.251 0.000 0 2 CLK_OUT_5x_hdmi_clk_1 0.833 0.000 0 15 dvi2rgb_0_PixelClk_1 8.273 0.000 0 6290 0.107 0.000 0 6290 3.750 0.000 0 3237 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- hdmi_i/dvi2rgb_0/U0/RefClk dvi2rgb_0_PixelClk -1.773 -1.773 1 1 0.126 0.000 0 1 clk_pll_i dvi2rgb_0_PixelClk 8.436 0.000 0 42 mmcm_clkout0 dvi2rgb_0_PixelClk 5.048 0.000 0 5 mmcm_clkout1 dvi2rgb_0_PixelClk -4.676 -91.180 21 21 -0.373 -0.835 4 21 dvi2rgb_0_PixelClk_1 dvi2rgb_0_PixelClk -4.207 -14935.253 6290 6290 0.054 0.000 0 6290 mmcm_clkout1 hdmi_i/dvi2rgb_0/U0/RefClk -2.757 -24.135 17 17 1.263 0.000 0 17 clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 6.998 0.000 0 8 38.139 0.000 0 8 clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 6.546 0.000 0 8 38.061 0.000 0 8 sync_pulse mem_refclk 0.973 0.000 0 1 0.668 0.000 0 1 oserdes_clk oserdes_clkdiv 1.594 0.000 0 12 0.095 0.000 0 12 oserdes_clk_1 oserdes_clkdiv_1 1.594 0.000 0 13 0.095 0.000 0 13 oserdes_clk_2 oserdes_clkdiv_2 1.278 0.000 0 15 0.076 0.000 0 15 oserdes_clk_3 oserdes_clkdiv_3 1.594 0.000 0 15 0.095 0.000 0 15 dvi2rgb_0_PixelClk clk_pll_i 3.977 0.000 0 34 axi_dynclk_0_PXL_CLK_O clk_pll_i 8.248 0.000 0 34 mmcm_clkout1 clk_pll_i 18.871 0.000 0 12 dvi2rgb_0_PixelClk_1 clk_pll_i 3.977 0.000 0 34 clk_pll_i axi_dynclk_0_PXL_CLK_O 8.839 0.000 0 42 dvi2rgb_0_PixelClk mmcm_clkout0 4.862 0.000 0 5 dvi2rgb_0_PixelClk_1 mmcm_clkout0 4.862 0.000 0 5 clk_pll_i mmcm_clkout1 12.088 0.000 0 1 dvi2rgb_0_PixelClk dvi2rgb_0_PixelClk_1 -4.207 -14932.303 6290 6290 0.054 0.000 0 6290 hdmi_i/dvi2rgb_0/U0/RefClk dvi2rgb_0_PixelClk_1 0.707 0.000 0 1 0.126 0.000 0 1 clk_pll_i dvi2rgb_0_PixelClk_1 8.436 0.000 0 42 mmcm_clkout0 dvi2rgb_0_PixelClk_1 5.048 0.000 0 5 mmcm_clkout1 dvi2rgb_0_PixelClk_1 -2.196 -39.098 21 21 -0.373 -0.835 4 21 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** axi_dynclk_0_PXL_CLK_O axi_dynclk_0_PXL_CLK_O 4.983 0.000 0 6 0.440 0.000 0 6 **async_default** clk_pll_i axi_dynclk_0_PXL_CLK_O 6.675 0.000 0 2 0.315 0.000 0 2 **async_default** axi_dynclk_0_PXL_CLK_O clk_pll_i -2.099 -9.064 5 5 3.052 0.000 0 5 **async_default** clk_pll_i clk_pll_i 5.859 0.000 0 98 0.593 0.000 0 98 **async_default** mmcm_clkout0 clk_pll_i -3.327 -16.121 5 5 0.624 0.000 0 5 **async_default** dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK 27.438 0.000 0 100 0.351 0.000 0 100 **async_default** dvi2rgb_0_PixelClk dvi2rgb_0_PixelClk 4.027 0.000 0 3 0.651 0.000 0 3 **async_default** dvi2rgb_0_PixelClk_1 dvi2rgb_0_PixelClk -2.013 -5.807 3 3 0.598 0.000 0 3 **async_default** dvi2rgb_0_PixelClk dvi2rgb_0_PixelClk_1 -2.013 -5.806 3 3 0.598 0.000 0 3 **async_default** dvi2rgb_0_PixelClk_1 dvi2rgb_0_PixelClk_1 10.467 0.000 0 3 0.651 0.000 0 3 **async_default** hdmi_i/dvi2rgb_0/U0/RefClk hdmi_i/dvi2rgb_0/U0/RefClk 2.813 0.000 0 3 0.384 0.000 0 3 **async_default** mmcm_clkout0 mmcm_clkout0 1.895 0.000 0 8 0.413 0.000 0 8 **async_default** mmcm_clkout1 mmcm_clkout1 1.636 0.000 0 97 0.360 0.000 0 97 **default** clk_pll_i 2.241 0.000 0 1 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: TMDS_IN_clk_p To Clock: TMDS_IN_clk_p Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 1.530ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: TMDS_IN_clk_p Waveform(ns): { 0.000 3.030 } Period(ns): 6.060 Sources: { TMDS_IN_clk_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 6.060 4.811 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 6.060 93.940 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKIN1 Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 1.500 3.030 1.530 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.500 3.030 1.530 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: CLKFBIN To Clock: CLKFBIN Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 4.811ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: CLKFBIN Waveform(ns): { 0.000 3.030 } Period(ns): 6.060 Sources: { hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 6.060 4.811 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKFBOUT Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 6.060 93.940 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: CLK_OUT_5x_hdmi_clk To Clock: CLK_OUT_5x_hdmi_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 15 Failing Endpoints, Worst Slack -0.455ns, Total Violation -6.404ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: CLK_OUT_5x_hdmi_clk Waveform(ns): { 0.000 0.606 } Period(ns): 1.212 Sources: { hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a ISERDESE2/CLK n/a 1.667 1.212 -0.455 ILOGIC_X1Y132 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/InputSERDES_X/DeserializerMaster/CLK Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 1.212 212.148 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 --------------------------------------------------------------------------------------------------- From Clock: dvi2rgb_0_PixelClk To Clock: dvi2rgb_0_PixelClk Setup : 0 Failing Endpoints, Worst Slack 1.833ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.107ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 1.174ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.833ns (required time - arrival time) Source: hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int_reg[5]/C (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Destination: hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9]/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: dvi2rgb_0_PixelClk Path Type: Setup (Max at Slow Process Corner) Requirement: 6.060ns (dvi2rgb_0_PixelClk rise@6.060ns - dvi2rgb_0_PixelClk rise@0.000ns) Data Path Delay: 4.220ns (logic 2.772ns (65.680%) route 1.448ns (34.320%)) Logic Levels: 7 (CARRY4=5 LUT2=1 LUT3=1) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.965ns = ( 11.025 - 6.060 ) Source Clock Delay (SCD): 5.244ns Clock Pessimism Removal (CPR): 0.264ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.960 0.960 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.233 2.193 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.089 2.282 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 1.025 3.307 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.982 4.289 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.955 5.244 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/clk SLICE_X127Y125 FDRE r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y125 FDRE (Prop_fdre_C_Q) 0.456 5.700 f hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int_reg[5]/Q net (fo=16, routed) 0.798 6.498 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int[5] SLICE_X127Y126 LUT2 (Prop_lut2_I0_O) 0.124 6.622 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[0]_i_13/O net (fo=1, routed) 0.000 6.622 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[0]_i_13_n_0 SLICE_X127Y126 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 7.172 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_3/CO[3] net (fo=1, routed) 0.000 7.172 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_3_n_0 SLICE_X127Y127 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 7.443 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_2/CO[0] net (fo=24, routed) 0.650 8.094 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_2_n_3 SLICE_X127Y129 LUT3 (Prop_lut3_I1_O) 0.373 8.467 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[3]_i_8/O net (fo=1, routed) 0.000 8.467 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[3]_i_8_n_0 SLICE_X127Y129 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 9.017 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 9.017 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[3]_i_1_n_0 SLICE_X127Y130 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 9.131 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[7]_i_1/CO[3] net (fo=1, routed) 0.000 9.131 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[7]_i_1_n_0 SLICE_X127Y131 CARRY4 (Prop_carry4_CI_O[1]) 0.334 9.465 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[11]_i_1/O[1] net (fo=1, routed) 0.000 9.465 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[9] SLICE_X127Y131 FDRE r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9]/D ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 6.060 6.060 r V4 0.000 6.060 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 6.060 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.916 6.976 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.162 8.138 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.084 8.222 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.960 9.182 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.918 10.100 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.925 11.025 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/clk SLICE_X127Y131 FDRE r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9]/C clock pessimism 0.264 11.289 clock uncertainty -0.053 11.236 SLICE_X127Y131 FDRE (Setup_fdre_C_D) 0.062 11.298 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9] ------------------------------------------------------------------- required time 11.298 arrival time -9.465 ------------------------------------------------------------------- slack 1.833 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.107ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/shifted_data_in_reg[8][20]/C (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2] (rising edge-triggered cell RAMB36E1 clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: dvi2rgb_0_PixelClk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (dvi2rgb_0_PixelClk rise@0.000ns - dvi2rgb_0_PixelClk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.148ns (34.549%) route 0.280ns (65.451%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.263ns Source Clock Delay (SCD): 1.894ns Clock Pessimism Removal (CPR): 0.291ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.481 0.481 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.440 0.921 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.051 0.972 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.363 1.335 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.270 1.605 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.289 1.894 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/out SLICE_X152Y104 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/shifted_data_in_reg[8][20]/C ------------------------------------------------------------------- ------------------- SLICE_X152Y104 FDRE (Prop_fdre_C_Q) 0.148 2.042 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/shifted_data_in_reg[8][20]/Q net (fo=1, routed) 0.280 2.322 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/CAP_TRIGGER_O_reg[2] RAMB36_X8Y20 RAMB36E1 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2] ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.529 0.529 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.480 1.009 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.054 1.063 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.402 1.465 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.431 1.896 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.367 2.263 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/out RAMB36_X8Y20 RAMB36E1 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK clock pessimism -0.291 1.973 RAMB36_X8Y20 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[2]) 0.243 2.216 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ------------------------------------------------------------------- required time -2.216 arrival time 2.322 ------------------------------------------------------------------- slack 0.107 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: dvi2rgb_0_PixelClk Waveform(ns): { 0.000 2.424 } Period(ns): 6.060 Sources: { hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 6.060 3.484 RAMB36_X8Y21 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 3.636 2.386 SLICE_X158Y140 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/ChannelBondX/pFIFO_reg_0_31_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 2.424 1.174 SLICE_X154Y134 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/ChannelBondX/pFIFO_reg_0_31_0_5/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK To Clock: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK Setup : 0 Failing Endpoints, Worst Slack 25.837ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.084ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 15.250ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 25.837ns (required time - arrival time) Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/C (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns}) Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/D (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns}) Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK Path Type: Setup (Max at Slow Process Corner) Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns) Data Path Delay: 6.582ns (logic 0.978ns (14.858%) route 5.604ns (85.142%)) Logic Levels: 4 (LUT4=1 LUT5=1 LUT6=2) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.325ns = ( 37.325 - 33.000 ) Source Clock Delay (SCD): 5.065ns Clock Pessimism Removal (CPR): 0.428ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge) 0.000 0.000 r BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK net (fo=1, routed) 3.112 3.112 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.208 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O net (fo=483, routed) 1.856 5.065 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0] SLICE_X109Y92 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y92 FDRE (Prop_fdre_C_Q) 0.456 5.521 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]/Q net (fo=9, routed) 1.778 7.298 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/shift_reg_in_reg[17][0] SLICE_X100Y86 LUT5 (Prop_lut5_I3_O) 0.124 7.422 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/iTDO_i_8/O net (fo=1, routed) 0.998 8.420 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/iTDO_i_8_n_0 SLICE_X99Y93 LUT6 (Prop_lut6_I0_O) 0.124 8.544 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/iTDO_i_4/O net (fo=1, routed) 0.803 9.347 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/shift_reg_in_reg[17] SLICE_X98Y97 LUT6 (Prop_lut6_I2_O) 0.124 9.471 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/iTDO_i_2/O net (fo=1, routed) 0.566 10.037 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]_0 SLICE_X97Y97 LUT4 (Prop_lut4_I3_O) 0.150 10.187 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTDO_i_1/O net (fo=1, routed) 1.460 11.647 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_next SLICE_X74Y102 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/D ------------------------------------------------------------------- ------------------- (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge) 33.000 33.000 r BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK net (fo=1, routed) 2.697 35.697 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 35.788 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O net (fo=483, routed) 1.536 37.325 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0] SLICE_X74Y102 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/C clock pessimism 0.428 37.753 clock uncertainty -0.035 37.717 SLICE_X74Y102 FDRE (Setup_fdre_C_D) -0.233 37.484 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg ------------------------------------------------------------------- required time 37.484 arrival time -11.647 ------------------------------------------------------------------- slack 25.837 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.084ns (arrival time - required time) Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[13]/C (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns}) Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_15/RAMA/I (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns}) Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns) Data Path Delay: 0.270ns (logic 0.141ns (52.315%) route 0.129ns (47.685%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.566ns Source Clock Delay (SCD): 2.104ns Clock Pessimism Removal (CPR): 0.423ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge) 0.000 0.000 r BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK net (fo=1, routed) 1.422 1.422 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.448 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O net (fo=483, routed) 0.655 2.104 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/m_bscan_tck[0] SLICE_X115Y87 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X115Y87 FDCE (Prop_fdce_C_Q) 0.141 2.245 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[13]/Q net (fo=2, routed) 0.129 2.373 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_15/DIA0 SLICE_X116Y88 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_15/RAMA/I ------------------------------------------------------------------- ------------------- (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge) 0.000 0.000 r BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK net (fo=1, routed) 1.605 1.605 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.634 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O net (fo=483, routed) 0.932 2.566 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_15/WCLK SLICE_X116Y88 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_15/RAMA/CLK clock pessimism -0.423 2.143 SLICE_X116Y88 RAMD32 (Hold_ramd32_CLK_I) 0.147 2.290 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_15/RAMA ------------------------------------------------------------------- required time -2.290 arrival time 2.373 ------------------------------------------------------------------- slack 0.084 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK Waveform(ns): { 0.000 16.500 } Period(ns): 33.000 Sources: { dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 33.000 30.845 BUFGCTRL_X0Y0 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/I Low Pulse Width Fast RAMD32/CLK n/a 1.250 16.500 15.250 SLICE_X116Y88 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_15/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 16.500 15.250 SLICE_X116Y87 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: hdmi_i/dvi2rgb_0/U0/RefClk To Clock: hdmi_i/dvi2rgb_0/U0/RefClk Setup : 2 Failing Endpoints, Worst Slack -0.097ns, Total Violation -0.152ns Hold : 0 Failing Endpoints, Worst Slack 0.054ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -0.097ns (required time - arrival time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/capture_qual_ctrl_reg[0]/C (rising edge-triggered cell FDRE clocked by hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q/R (rising edge-triggered cell FDRE clocked by hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: hdmi_i/dvi2rgb_0/U0/RefClk Path Type: Setup (Max at Slow Process Corner) Requirement: 5.000ns (hdmi_i/dvi2rgb_0/U0/RefClk rise@5.000ns - hdmi_i/dvi2rgb_0/U0/RefClk rise@0.000ns) Data Path Delay: 4.597ns (logic 0.966ns (21.016%) route 3.631ns (78.984%)) Logic Levels: 3 (LUT3=2 SRLC32E=1) Clock Path Skew: -0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.732ns = ( 6.732 - 5.000 ) Source Clock Delay (SCD): 1.855ns Clock Pessimism Removal (CPR): 0.087ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.855 1.855 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/RefClk SLICE_X129Y68 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/capture_qual_ctrl_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y68 FDRE (Prop_fdre_C_Q) 0.419 2.274 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/capture_qual_ctrl_reg[0]/Q net (fo=1, routed) 0.924 3.199 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/out[0] SLICE_X130Y70 LUT3 (Prop_lut3_I2_O) 0.299 3.498 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/I_YESLUT6.U_SRL32_D_i_2/O net (fo=19, routed) 1.078 4.575 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/A[3] SLICE_X136Y69 SRLC32E (Prop_srlc32e_A[3]_Q) 0.124 4.699 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B/Q net (fo=1, routed) 0.785 5.485 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.SRL_Q_0 SLICE_X136Y66 LUT3 (Prop_lut3_I2_O) 0.124 5.609 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/u_scnt_cmp_q_i_1/O net (fo=3, routed) 0.843 6.452 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/cmp_reset SLICE_X127Y63 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q/R ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 5.000 5.000 r BUFGCTRL_X0Y17 BUFG 0.000 5.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.732 6.732 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/RefClk SLICE_X127Y63 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q/C clock pessimism 0.087 6.819 clock uncertainty -0.035 6.784 SLICE_X127Y63 FDRE (Setup_fdre_C_R) -0.429 6.355 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q ------------------------------------------------------------------- required time 6.355 arrival time -6.452 ------------------------------------------------------------------- slack -0.097 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.054ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sAddr_reg_rep[3]/C (rising edge-triggered cell FDRE clocked by hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sI2C_DataOut_reg[2]/D (rising edge-triggered cell FDRE clocked by hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: hdmi_i/dvi2rgb_0/U0/RefClk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (hdmi_i/dvi2rgb_0/U0/RefClk rise@0.000ns - hdmi_i/dvi2rgb_0/U0/RefClk rise@0.000ns) Data Path Delay: 0.495ns (logic 0.323ns (65.258%) route 0.172ns (34.742%)) Logic Levels: 3 (LUT6=1 MUXF7=1 MUXF8=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.910ns Source Clock Delay (SCD): 0.569ns Clock Pessimism Removal (CPR): 0.005ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 0.569 0.569 hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/RefClk SLICE_X79Y100 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sAddr_reg_rep[3]/C ------------------------------------------------------------------- ------------------- SLICE_X79Y100 FDRE (Prop_fdre_C_Q) 0.128 0.697 r hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sAddr_reg_rep[3]/Q net (fo=32, routed) 0.172 0.869 hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sAddr_0[3] SLICE_X81Y99 LUT6 (Prop_lut6_I4_O) 0.098 0.967 r hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sI2C_DataOut[2]_i_5/O net (fo=1, routed) 0.000 0.967 hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sI2C_DataOut[2]_i_5_n_0 SLICE_X81Y99 MUXF7 (Prop_muxf7_I1_O) 0.074 1.041 r hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sI2C_DataOut_reg[2]_i_2/O net (fo=1, routed) 0.000 1.041 hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sI2C_DataOut_reg[2]_i_2_n_0 SLICE_X81Y99 MUXF8 (Prop_muxf8_I0_O) 0.023 1.064 r hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sI2C_DataOut_reg[2]_i_1/O net (fo=1, routed) 0.000 1.064 hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sI2C_DataOut_reg[2]_i_1_n_0 SLICE_X81Y99 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sI2C_DataOut_reg[2]/D ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 0.910 0.910 hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/RefClk SLICE_X81Y99 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sI2C_DataOut_reg[2]/C clock pessimism -0.005 0.905 SLICE_X81Y99 FDRE (Hold_fdre_C_D) 0.105 1.010 hdmi_i/dvi2rgb_0/U0/GenerateDDC.DDC_EEPROM/sI2C_DataOut_reg[2] ------------------------------------------------------------------- required time -1.010 arrival time 1.064 ------------------------------------------------------------------- slack 0.054 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: hdmi_i/dvi2rgb_0/U0/RefClk Waveform(ns): { 0.000 2.500 } Period(ns): 5.000 Sources: { hdmi_i/dvi2rgb_0/U0/RefClk } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a IDELAYCTRL/REFCLK n/a 3.225 5.000 1.775 IDELAYCTRL_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/IDelayCtrlX/REFCLK Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/IDelayCtrlX/REFCLK Low Pulse Width Slow SRL16E/CLK n/a 0.980 2.500 1.520 SLICE_X140Y70 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/shifted_data_in_reg[7][0]_srl8/CLK High Pulse Width Slow SRL16E/CLK n/a 0.980 2.500 1.520 SLICE_X140Y70 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/shifted_data_in_reg[7][0]_srl8/CLK --------------------------------------------------------------------------------------------------- From Clock: hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK To Clock: hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK Setup : 0 Failing Endpoints, Worst Slack 13.359ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.062ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 15.686ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 13.359ns (required time - arrival time) Source: hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C (falling edge-triggered cell FDRE clocked by hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK {rise@0.000ns fall@16.667ns period=33.333ns}) Destination: hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[5]/D (rising edge-triggered cell FDCE clocked by hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK {rise@0.000ns fall@16.667ns period=33.333ns}) Path Group: hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK Path Type: Setup (Max at Slow Process Corner) Requirement: 16.667ns (hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@33.333ns - hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall@16.667ns) Data Path Delay: 3.179ns (logic 0.733ns (23.054%) route 2.446ns (76.946%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: -0.140ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.224ns = ( 37.557 - 33.333 ) Source Clock Delay (SCD): 4.858ns = ( 21.524 - 16.667 ) Clock Pessimism Removal (CPR): 0.494ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall edge) 16.667 16.667 f BSCAN_X0Y1 BSCANE2 0.000 16.667 f hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK net (fo=1, routed) 2.989 19.656 hdmi_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/drck_i BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.096 19.752 f hdmi_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O net (fo=314, routed) 1.772 21.524 hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Use_BSCAN.PORT_Selector_reg[0] SLICE_X19Y149 FDRE r hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C (IS_INVERTED) ------------------------------------------------------------------- ------------------- SLICE_X19Y149 FDRE (Prop_fdre_C_Q) 0.459 21.983 r hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/Q net (fo=4, routed) 0.608 22.591 hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/sync SLICE_X20Y148 LUT6 (Prop_lut6_I0_O) 0.124 22.715 r hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Dbg_Shift_31_INST_0/O net (fo=9, routed) 1.839 24.554 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Shift SLICE_X49Y149 LUT3 (Prop_lut3_I0_O) 0.150 24.704 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count[5]_i_1/O net (fo=1, routed) 0.000 24.704 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/p_0_in__0[5] SLICE_X49Y149 FDCE r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[5]/D ------------------------------------------------------------------- ------------------- (clock hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge) 33.333 33.333 r BSCAN_X0Y1 BSCANE2 0.000 33.333 r hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK net (fo=1, routed) 2.580 35.913 hdmi_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/drck_i BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 36.004 r hdmi_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O net (fo=314, routed) 1.552 37.557 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk SLICE_X49Y149 FDCE r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[5]/C clock pessimism 0.494 38.051 clock uncertainty -0.035 38.015 SLICE_X49Y149 FDCE (Setup_fdce_C_D) 0.047 38.062 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[5] ------------------------------------------------------------------- required time 38.062 arrival time -24.704 ------------------------------------------------------------------- slack 13.359 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.062ns (arrival time - required time) Source: hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.unchanged_reg/C (rising edge-triggered cell FDCE clocked by hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK {rise@0.000ns fall@16.667ns period=33.333ns}) Destination: hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.status_reg_reg[29]/D (rising edge-triggered cell FDCE clocked by hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK {rise@0.000ns fall@16.667ns period=33.333ns}) Path Group: hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns - hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns) Data Path Delay: 0.393ns (logic 0.141ns (35.864%) route 0.252ns (64.136%)) Logic Levels: 0 Clock Path Skew: 0.268ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.376ns Source Clock Delay (SCD): 1.928ns Clock Pessimism Removal (CPR): 0.180ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge) 0.000 0.000 r BSCAN_X0Y1 BSCANE2 0.000 0.000 r hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK net (fo=1, routed) 1.316 1.316 hdmi_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/drck_i BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 1.342 r hdmi_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O net (fo=314, routed) 0.586 1.928 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk SLICE_X50Y146 FDCE r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.unchanged_reg/C ------------------------------------------------------------------- ------------------- SLICE_X50Y146 FDCE (Prop_fdce_C_Q) 0.141 2.069 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.unchanged_reg/Q net (fo=2, routed) 0.252 2.321 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/unchanged SLICE_X52Y153 FDCE r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.status_reg_reg[29]/D ------------------------------------------------------------------- ------------------- (clock hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge) 0.000 0.000 r BSCAN_X0Y1 BSCANE2 0.000 0.000 r hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK net (fo=1, routed) 1.493 1.493 hdmi_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/drck_i BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 1.522 r hdmi_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O net (fo=314, routed) 0.853 2.376 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk SLICE_X52Y153 FDCE r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.status_reg_reg[29]/C clock pessimism -0.180 2.196 SLICE_X52Y153 FDCE (Hold_fdce_C_D) 0.063 2.259 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.status_reg_reg[29] ------------------------------------------------------------------- required time -2.259 arrival time 2.321 ------------------------------------------------------------------- slack 0.062 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK Waveform(ns): { 0.000 16.667 } Period(ns): 33.333 Sources: { hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 33.333 31.178 BUFGCTRL_X0Y1 hdmi_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/I Low Pulse Width Fast SRL16E/CLK n/a 0.980 16.666 15.686 SLICE_X56Y140 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I/Compare[0].SRLC16E_I/Use_unisim.MB_SRL16CE_I1/CLK High Pulse Width Slow SRL16E/CLK n/a 0.980 16.666 15.686 SLICE_X56Y140 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I/Compare[0].SRLC16E_I/Use_unisim.MB_SRL16CE_I1/CLK --------------------------------------------------------------------------------------------------- From Clock: hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE To Clock: hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE Setup : 0 Failing Endpoints, Worst Slack 7.993ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.519ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 16.166ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 7.993ns (required time - arrival time) Source: hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[3]/C (falling edge-triggered cell FDCE clocked by hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE {rise@0.000ns fall@16.667ns period=33.333ns}) Destination: hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Use_Statistics.Debug_Stat_I/Serial_Dbg_Intf.data_write_TClk_reg/D (rising edge-triggered cell FDCE clocked by hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE {rise@0.000ns fall@16.667ns period=33.333ns}) Path Group: hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE Path Type: Setup (Max at Slow Process Corner) Requirement: 16.667ns (hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@33.333ns - hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@16.667ns) Data Path Delay: 5.157ns (logic 0.734ns (14.233%) route 4.423ns (85.767%)) Logic Levels: 3 (LUT3=2 LUT6=1) Clock Path Skew: -3.321ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.074ns = ( 34.407 - 33.333 ) Source Clock Delay (SCD): 4.555ns = ( 21.221 - 16.667 ) Clock Pessimism Removal (CPR): 0.160ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge) 16.667 16.667 f BSCAN_X0Y1 BSCANE2 0.000 16.667 f hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE net (fo=95, routed) 4.555 21.221 hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK SLICE_X20Y147 FDCE r hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[3]/C (IS_INVERTED) ------------------------------------------------------------------- ------------------- SLICE_X20Y147 FDCE (Prop_fdce_C_Q) 0.362 21.583 r hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[3]/Q net (fo=6, routed) 1.047 22.631 hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q[4] SLICE_X21Y146 LUT3 (Prop_lut3_I2_O) 0.124 22.755 r hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Dbg_Reg_En_0[3]_INST_0/O net (fo=12, routed) 1.529 24.284 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Use_Statistics.Debug_Stat_I/Dbg_Reg_En[3] SLICE_X41Y140 LUT6 (Prop_lut6_I1_O) 0.124 24.408 f hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Use_Statistics.Debug_Stat_I/Serial_Dbg_Intf.data_write_TClk_i_3/O net (fo=3, routed) 0.678 25.086 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Use_Statistics.Debug_Stat_I/Serial_Dbg_Intf.status_reg_reg[1]_0 SLICE_X40Y139 LUT3 (Prop_lut3_I2_O) 0.124 25.210 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Use_Statistics.Debug_Stat_I/Serial_Dbg_Intf.data_write_TClk_i_1/O net (fo=34, routed) 1.168 26.378 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Use_Statistics.Debug_Stat_I/data_Write_Reg_En SLICE_X38Y132 FDCE r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Use_Statistics.Debug_Stat_I/Serial_Dbg_Intf.data_write_TClk_reg/D ------------------------------------------------------------------- ------------------- (clock hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge) 33.333 33.333 r BSCAN_X0Y1 BSCANE2 0.000 33.333 r hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE net (fo=95, routed) 1.074 34.407 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Use_Statistics.Debug_Stat_I/Dbg_Update SLICE_X38Y132 FDCE r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Use_Statistics.Debug_Stat_I/Serial_Dbg_Intf.data_write_TClk_reg/C clock pessimism 0.160 34.567 clock uncertainty -0.035 34.531 SLICE_X38Y132 FDCE (Setup_fdce_C_D) -0.160 34.371 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Use_Statistics.Debug_Stat_I/Serial_Dbg_Intf.data_write_TClk_reg ------------------------------------------------------------------- required time 34.371 arrival time -26.378 ------------------------------------------------------------------- slack 7.993 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.519ns (arrival time - required time) Source: hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C (rising edge-triggered cell FDCE clocked by hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE {rise@0.000ns fall@16.667ns period=33.333ns}) Destination: hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/D (rising edge-triggered cell FDCE clocked by hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE {rise@0.000ns fall@16.667ns period=33.333ns}) Path Group: hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@0.000ns - hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@0.000ns) Data Path Delay: 1.582ns (logic 0.163ns (10.303%) route 1.419ns (89.697%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.192ns Source Clock Delay (SCD): 1.963ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge) 0.000 0.000 r BSCAN_X0Y1 BSCANE2 0.000 0.000 r hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE net (fo=95, routed) 1.963 1.963 hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK SLICE_X18Y148 FDCE r hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X18Y148 FDCE (Prop_fdce_C_Q) 0.118 2.081 r hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/Q net (fo=2, routed) 1.419 3.500 hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/completion_ctrl SLICE_X18Y148 LUT3 (Prop_lut3_I2_O) 0.045 3.545 r hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/completion_ctrl[0]_i_1/O net (fo=1, routed) 0.000 3.545 hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I_n_37 SLICE_X18Y148 FDCE r hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/D ------------------------------------------------------------------- ------------------- (clock hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge) 0.000 0.000 r BSCAN_X0Y1 BSCANE2 0.000 0.000 r hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE net (fo=95, routed) 2.192 2.192 hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK SLICE_X18Y148 FDCE r hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C clock pessimism -0.229 1.963 SLICE_X18Y148 FDCE (Hold_fdce_C_D) 0.063 2.026 hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0] ------------------------------------------------------------------- required time -2.026 arrival time 3.545 ------------------------------------------------------------------- slack 1.519 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE Waveform(ns): { 0.000 16.667 } Period(ns): 33.333 Sources: { hdmi_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a FDCE/C n/a 1.000 33.333 32.333 SLICE_X49Y134 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Use_Trace.Debug_Trace_I/Serial_Dbg_Intf.command_reg_reg[0]/C Low Pulse Width Slow FDCE/C n/a 0.500 16.666 16.166 SLICE_X49Y134 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Use_Trace.Debug_Trace_I/Serial_Dbg_Intf.command_reg_reg[0]/C High Pulse Width Fast FDCE/C n/a 0.500 16.666 16.166 SLICE_X20Y147 hdmi_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[0]/C --------------------------------------------------------------------------------------------------- From Clock: sys_clk_i To Clock: sys_clk_i Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk_i Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { sys_clk_i } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 10.000 8.751 PLLE2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 10.000 42.633 PLLE2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 2.000 5.000 3.000 PLLE2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: freq_refclk To Clock: freq_refclk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: freq_refclk Waveform(ns): { 0.000 0.625 } Period(ns): 1.250 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 1.250 1.250 0.000 PHASER_OUT_PHY_X1Y12 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK Max Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 2.500 1.250 1.250 PHASER_OUT_PHY_X1Y12 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK Low Pulse Width Slow PHASER_REF/CLKIN n/a 0.562 0.625 0.063 PHASER_REF_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN High Pulse Width Slow PHASER_OUT_PHY/FREQREFCLK n/a 0.563 0.625 0.062 PHASER_OUT_PHY_X1Y12 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK --------------------------------------------------------------------------------------------------- From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a ISERDESE2/CLK n/a 1.667 2.500 0.833 ILOGIC_X1Y176 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK --------------------------------------------------------------------------------------------------- From Clock: iserdes_clkdiv To Clock: iserdes_clkdiv Setup : 0 Failing Endpoints, Worst Slack 7.875ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.850ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 7.875ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq/CLKDIVP (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D4[0] (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: iserdes_clkdiv Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (iserdes_clkdiv rise@10.000ns - iserdes_clkdiv rise@0.000ns) Data Path Delay: 1.142ns (logic 0.425ns (37.204%) route 0.717ns (62.796%)) Logic Levels: 0 Clock Path Skew: -0.448ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.961ns = ( 14.961 - 10.000 ) Source Clock Delay (SCD): 5.640ns Clock Pessimism Removal (CPR): 0.231ns Clock Uncertainty: 0.059ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.096ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock iserdes_clkdiv rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 net (fo=7, routed) 0.607 3.526 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk PHASER_IN_PHY_X1Y14 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) 1.493 5.019 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK PHASER_IN_PHY_X1Y14 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) 0.173 5.192 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV net (fo=9, routed) 0.448 5.640 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/iserdes_clkdiv ILOGIC_X1Y179 ISERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq/CLKDIVP ------------------------------------------------------------------- ------------------- ILOGIC_X1Y179 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q4) 0.425 6.065 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq/Q4 net (fo=1, routed) 0.717 6.782 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/if_d4[0] IN_FIFO_X1Y14 IN_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D4[0] ------------------------------------------------------------------- ------------------- (clock iserdes_clkdiv rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 12.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.083 12.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 net (fo=7, routed) 0.576 13.344 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk PHASER_IN_PHY_X1Y14 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) 1.455 14.798 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK PHASER_IN_PHY_X1Y14 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) 0.163 14.961 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV net (fo=9, routed) 0.000 14.961 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv IN_FIFO_X1Y14 IN_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK clock pessimism 0.231 15.192 clock uncertainty -0.059 15.132 IN_FIFO_X1Y14 IN_FIFO (Setup_in_fifo_WRCLK_D4[0]) -0.475 14.657 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo ------------------------------------------------------------------- required time 14.657 arrival time -6.782 ------------------------------------------------------------------- slack 7.875 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.071ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: iserdes_clkdiv Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (iserdes_clkdiv rise@0.000ns - iserdes_clkdiv rise@0.000ns) Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.540ns Source Clock Delay (SCD): 2.253ns Clock Pessimism Removal (CPR): 0.287ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock iserdes_clkdiv rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 net (fo=7, routed) 0.197 0.968 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk PHASER_IN_PHY_X1Y14 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) 1.195 2.163 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK PHASER_IN_PHY_X1Y14 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) 0.090 2.253 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV ------------------------------------------------------------------- ------------------- PHASER_IN_PHY_X1Y14 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) 0.058 2.311 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/WRENABLE net (fo=1, routed) 0.000 2.311 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_wr_enable IN_FIFO_X1Y14 IN_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN ------------------------------------------------------------------- ------------------- (clock iserdes_clkdiv rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 net (fo=7, routed) 0.217 1.225 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk PHASER_IN_PHY_X1Y14 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) 1.219 2.444 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK PHASER_IN_PHY_X1Y14 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) 0.096 2.540 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV net (fo=9, routed) 0.000 2.540 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv IN_FIFO_X1Y14 IN_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK clock pessimism -0.287 2.253 IN_FIFO_X1Y14 IN_FIFO (Hold_in_fifo_WRCLK_WREN) -0.013 2.240 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo ------------------------------------------------------------------- required time -2.240 arrival time 2.311 ------------------------------------------------------------------- slack 0.071 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: iserdes_clkdiv Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a IN_FIFO/WRCLK n/a 5.000 10.000 5.000 IN_FIFO_X1Y14 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK Low Pulse Width Fast IN_FIFO/WRCLK n/a 2.150 5.000 2.850 IN_FIFO_X1Y14 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 5.000 2.850 IN_FIFO_X1Y14 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK --------------------------------------------------------------------------------------------------- From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a ISERDESE2/CLK n/a 1.667 2.500 0.833 ILOGIC_X1Y187 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[0].iserdes_dq_.iserdesdq/CLK --------------------------------------------------------------------------------------------------- From Clock: iserdes_clkdiv_1 To Clock: iserdes_clkdiv_1 Setup : 0 Failing Endpoints, Worst Slack 7.891ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.850ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 7.891ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq/CLKDIVP (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv_1 {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D4[2] (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: iserdes_clkdiv_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (iserdes_clkdiv_1 rise@10.000ns - iserdes_clkdiv_1 rise@0.000ns) Data Path Delay: 1.109ns (logic 0.425ns (38.317%) route 0.684ns (61.683%)) Logic Levels: 0 Clock Path Skew: -0.465ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.951ns = ( 14.951 - 10.000 ) Source Clock Delay (SCD): 5.647ns Clock Pessimism Removal (CPR): 0.231ns Clock Uncertainty: 0.059ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.096ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock iserdes_clkdiv_1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 net (fo=7, routed) 0.597 3.516 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk PHASER_IN_PHY_X1Y15 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) 1.493 5.009 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK PHASER_IN_PHY_X1Y15 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) 0.173 5.182 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV net (fo=9, routed) 0.465 5.647 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/iserdes_clkdiv ILOGIC_X1Y191 ISERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq/CLKDIVP ------------------------------------------------------------------- ------------------- ILOGIC_X1Y191 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q2) 0.425 6.072 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq/Q2 net (fo=1, routed) 0.684 6.756 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/if_d4[2] IN_FIFO_X1Y15 IN_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D4[2] ------------------------------------------------------------------- ------------------- (clock iserdes_clkdiv_1 rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 12.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.083 12.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 net (fo=7, routed) 0.566 13.334 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk PHASER_IN_PHY_X1Y15 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) 1.455 14.788 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK PHASER_IN_PHY_X1Y15 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) 0.163 14.951 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV net (fo=9, routed) 0.000 14.951 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv IN_FIFO_X1Y15 IN_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK clock pessimism 0.231 15.182 clock uncertainty -0.059 15.122 IN_FIFO_X1Y15 IN_FIFO (Setup_in_fifo_WRCLK_D4[2]) -0.475 14.647 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo ------------------------------------------------------------------- required time 14.647 arrival time -6.756 ------------------------------------------------------------------- slack 7.891 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.071ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv_1 {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: iserdes_clkdiv_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (iserdes_clkdiv_1 rise@0.000ns - iserdes_clkdiv_1 rise@0.000ns) Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.534ns Source Clock Delay (SCD): 2.247ns Clock Pessimism Removal (CPR): 0.287ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock iserdes_clkdiv_1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 net (fo=7, routed) 0.191 0.962 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk PHASER_IN_PHY_X1Y15 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) 1.195 2.157 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK PHASER_IN_PHY_X1Y15 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) 0.090 2.247 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV ------------------------------------------------------------------- ------------------- PHASER_IN_PHY_X1Y15 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) 0.058 2.305 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/WRENABLE net (fo=1, routed) 0.000 2.305 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_wr_enable IN_FIFO_X1Y15 IN_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN ------------------------------------------------------------------- ------------------- (clock iserdes_clkdiv_1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 net (fo=7, routed) 0.211 1.219 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk PHASER_IN_PHY_X1Y15 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) 1.219 2.438 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK PHASER_IN_PHY_X1Y15 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) 0.096 2.534 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV net (fo=9, routed) 0.000 2.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv IN_FIFO_X1Y15 IN_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK clock pessimism -0.287 2.247 IN_FIFO_X1Y15 IN_FIFO (Hold_in_fifo_WRCLK_WREN) -0.013 2.234 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo ------------------------------------------------------------------- required time -2.234 arrival time 2.305 ------------------------------------------------------------------- slack 0.071 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: iserdes_clkdiv_1 Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a IN_FIFO/WRCLK n/a 5.000 10.000 5.000 IN_FIFO_X1Y15 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 5.000 2.850 IN_FIFO_X1Y15 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 5.000 2.850 IN_FIFO_X1Y15 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK --------------------------------------------------------------------------------------------------- From Clock: mem_refclk To Clock: mem_refclk Setup : 0 Failing Endpoints, Worst Slack 1.331ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.336ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.625ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.331ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: mem_refclk Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (mem_refclk rise@2.500ns - mem_refclk rise@0.000ns) Data Path Delay: 1.093ns (logic 0.622ns (56.908%) route 0.471ns (43.092%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.357ns = ( 5.857 - 2.500 ) Source Clock Delay (SCD): 3.540ns Clock Pessimism Removal (CPR): 0.184ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.109ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mem_refclk rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.621 3.540 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk PHY_CONTROL_X1Y3 PHY_CONTROL r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK ------------------------------------------------------------------- ------------------- PHY_CONTROL_X1Y3 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) 0.622 4.162 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY net (fo=1, routed) 0.471 4.633 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 PHY_CONTROL_X1Y3 PHY_CONTROL r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY ------------------------------------------------------------------- ------------------- (clock mem_refclk rise edge) 2.500 2.500 r R4 0.000 2.500 r sys_clk_i (IN) net (fo=0) 0.000 2.500 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 5.185 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 5.268 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.589 5.857 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk PHY_CONTROL_X1Y3 PHY_CONTROL r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK clock pessimism 0.184 6.040 clock uncertainty -0.065 5.975 PHY_CONTROL_X1Y3 PHY_CONTROL (Setup_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) -0.011 5.964 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i ------------------------------------------------------------------- required time 5.964 arrival time -4.633 ------------------------------------------------------------------- slack 1.331 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.336ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: mem_refclk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mem_refclk rise@0.000ns - mem_refclk rise@0.000ns) Data Path Delay: 0.459ns (logic 0.313ns (68.192%) route 0.146ns (31.808%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.223ns Source Clock Delay (SCD): 0.966ns Clock Pessimism Removal (CPR): 0.257ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mem_refclk rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.195 0.966 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk PHY_CONTROL_X1Y3 PHY_CONTROL r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK ------------------------------------------------------------------- ------------------- PHY_CONTROL_X1Y3 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) 0.313 1.279 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY net (fo=1, routed) 0.146 1.425 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 PHY_CONTROL_X1Y3 PHY_CONTROL r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY ------------------------------------------------------------------- ------------------- (clock mem_refclk rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.215 1.223 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk PHY_CONTROL_X1Y3 PHY_CONTROL r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK clock pessimism -0.257 0.966 PHY_CONTROL_X1Y3 PHY_CONTROL (Hold_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) 0.123 1.089 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i ------------------------------------------------------------------- required time -1.089 arrival time 1.425 ------------------------------------------------------------------- slack 0.336 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: mem_refclk Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PHY_CONTROL/MEMREFCLK n/a 1.475 2.500 1.025 PHY_CONTROL_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 2.500 157.500 PLLE2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 Low Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.250 0.625 PHY_CONTROL_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK High Pulse Width Fast PHY_CONTROL/MEMREFCLK n/a 0.625 1.250 0.625 PHY_CONTROL_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK --------------------------------------------------------------------------------------------------- From Clock: oserdes_clk To Clock: oserdes_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: oserdes_clk Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a OSERDESE2/CLK n/a 1.667 2.500 0.833 OLOGIC_X1Y151 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK --------------------------------------------------------------------------------------------------- From Clock: oserdes_clkdiv To Clock: oserdes_clkdiv Setup : 0 Failing Endpoints, Worst Slack 8.041ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.090ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.850ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 8.041ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: oserdes_clkdiv Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (oserdes_clkdiv rise@10.000ns - oserdes_clkdiv rise@0.000ns) Data Path Delay: 1.681ns (logic 0.674ns (40.087%) route 1.007ns (59.913%)) Logic Levels: 0 Clock Path Skew: 0.412ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.986ns = ( 15.986 - 10.000 ) Source Clock Delay (SCD): 5.826ns Clock Pessimism Removal (CPR): 0.252ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.109ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.614 3.533 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.136 5.669 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.157 5.826 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV net (fo=12, routed) 0.000 5.826 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv OUT_FIFO_X1Y12 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK ------------------------------------------------------------------- ------------------- OUT_FIFO_X1Y12 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[7]) 0.674 6.500 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q6[7] net (fo=1, routed) 1.007 7.507 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[43] OLOGIC_X1Y150 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 12.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 12.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.582 13.350 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.077 15.426 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.148 15.574 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV net (fo=12, routed) 0.412 15.986 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv OLOGIC_X1Y150 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV clock pessimism 0.252 16.238 clock uncertainty -0.065 16.173 OLOGIC_X1Y150 OSERDESE2 (Setup_oserdese2_CLKDIV_D4) -0.625 15.548 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i ------------------------------------------------------------------- required time 15.548 arrival time -7.507 ------------------------------------------------------------------- slack 8.041 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.090ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: oserdes_clkdiv Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clkdiv rise@0.000ns) Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) Logic Levels: 0 Clock Path Skew: 0.179ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.351ns Source Clock Delay (SCD): 2.865ns Clock Pessimism Removal (CPR): 0.307ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.197 0.968 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.813 2.782 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.083 2.865 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV net (fo=12, routed) 0.000 2.865 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv OUT_FIFO_X1Y12 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK ------------------------------------------------------------------- ------------------- OUT_FIFO_X1Y12 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) 0.138 3.003 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q2[1] net (fo=1, routed) 0.150 3.153 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[9] OLOGIC_X1Y153 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.218 1.226 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.858 3.084 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.088 3.172 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV net (fo=12, routed) 0.179 3.351 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv OLOGIC_X1Y153 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV clock pessimism -0.307 3.044 OLOGIC_X1Y153 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) 0.019 3.063 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i ------------------------------------------------------------------- required time -3.063 arrival time 3.153 ------------------------------------------------------------------- slack 0.090 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: oserdes_clkdiv Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a OUT_FIFO/RDCLK n/a 5.000 10.000 5.000 OUT_FIFO_X1Y12 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 5.000 2.850 OUT_FIFO_X1Y12 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK High Pulse Width Fast OUT_FIFO/RDCLK n/a 2.150 5.000 2.850 OUT_FIFO_X1Y12 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK --------------------------------------------------------------------------------------------------- From Clock: oserdes_clk_1 To Clock: oserdes_clk_1 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: oserdes_clk_1 Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a OSERDESE2/CLK n/a 1.667 2.500 0.833 OLOGIC_X1Y163 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK --------------------------------------------------------------------------------------------------- From Clock: oserdes_clkdiv_1 To Clock: oserdes_clkdiv_1 Setup : 0 Failing Endpoints, Worst Slack 8.564ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.094ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.850ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 8.564ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: oserdes_clkdiv_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (oserdes_clkdiv_1 rise@10.000ns - oserdes_clkdiv_1 rise@0.000ns) Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.997%)) Logic Levels: 0 Clock Path Skew: 0.396ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.960ns = ( 15.960 - 10.000 ) Source Clock Delay (SCD): 5.815ns Clock Pessimism Removal (CPR): 0.251ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.109ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.603 3.522 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.136 5.658 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.157 5.815 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV net (fo=13, routed) 0.000 5.815 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv OUT_FIFO_X1Y13 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK ------------------------------------------------------------------- ------------------- OUT_FIFO_X1Y13 OUT_FIFO (Prop_out_fifo_RDCLK_Q5[4]) 0.674 6.489 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q5[4] net (fo=1, routed) 0.468 6.957 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[40] OLOGIC_X1Y169 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_1 rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 12.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 12.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.572 13.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.077 15.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.148 15.564 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV net (fo=13, routed) 0.396 15.960 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv OLOGIC_X1Y169 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV clock pessimism 0.251 16.211 clock uncertainty -0.065 16.146 OLOGIC_X1Y169 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) -0.625 15.521 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i ------------------------------------------------------------------- required time 15.521 arrival time -6.957 ------------------------------------------------------------------- slack 8.564 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.094ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: oserdes_clkdiv_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clkdiv_1 rise@0.000ns) Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) Logic Levels: 0 Clock Path Skew: 0.175ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.338ns Source Clock Delay (SCD): 2.858ns Clock Pessimism Removal (CPR): 0.305ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.190 0.961 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.813 2.775 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.083 2.858 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV net (fo=13, routed) 0.000 2.858 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv OUT_FIFO_X1Y13 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK ------------------------------------------------------------------- ------------------- OUT_FIFO_X1Y13 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) 0.138 2.996 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q2[1] net (fo=1, routed) 0.150 3.146 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[9] OLOGIC_X1Y165 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.209 1.217 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.858 3.075 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.088 3.163 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV net (fo=13, routed) 0.175 3.338 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv OLOGIC_X1Y165 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV clock pessimism -0.305 3.033 OLOGIC_X1Y165 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) 0.019 3.052 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i ------------------------------------------------------------------- required time -3.052 arrival time 3.146 ------------------------------------------------------------------- slack 0.094 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: oserdes_clkdiv_1 Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a OUT_FIFO/RDCLK n/a 5.000 10.000 5.000 OUT_FIFO_X1Y13 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 5.000 2.850 OUT_FIFO_X1Y13 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK High Pulse Width Fast OUT_FIFO/RDCLK n/a 2.150 5.000 2.850 OUT_FIFO_X1Y13 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK --------------------------------------------------------------------------------------------------- From Clock: oserdes_clk_2 To Clock: oserdes_clk_2 Setup : 0 Failing Endpoints, Worst Slack 0.913ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.413ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.913ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: oserdes_clk_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (oserdes_clk_2 rise@2.500ns - oserdes_clk_2 rise@0.000ns) Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) Logic Levels: 0 Clock Path Skew: 0.400ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.467ns = ( 8.967 - 2.500 ) Source Clock Delay (SCD): 6.349ns Clock Pessimism Removal (CPR): 0.282ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.109ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clk_2 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.614 3.533 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.136 5.669 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) 0.679 6.349 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED ------------------------------------------------------------------- ------------------- PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) 0.562 6.911 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/CTSBUS[0] net (fo=2, routed) 0.475 7.386 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CTSBUS[0] OLOGIC_X1Y182 ODDR r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 ------------------------------------------------------------------- ------------------- (clock oserdes_clk_2 rise edge) 2.500 2.500 r R4 0.000 2.500 r sys_clk_i (IN) net (fo=0) 0.000 2.500 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 5.185 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 5.268 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.582 5.850 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.077 7.926 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) 0.641 8.567 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED net (fo=2, routed) 0.400 8.967 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed OLOGIC_X1Y182 ODDR r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/C clock pessimism 0.282 9.249 clock uncertainty -0.065 9.184 OLOGIC_X1Y182 ODDR (Setup_oddr_C_D1) -0.885 8.299 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts ------------------------------------------------------------------- required time 8.299 arrival time -7.386 ------------------------------------------------------------------- slack 0.913 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.413ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: oserdes_clk_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (oserdes_clk_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) Logic Levels: 0 Clock Path Skew: 0.176ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.833ns Source Clock Delay (SCD): 3.321ns Clock Pessimism Removal (CPR): 0.336ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clk_2 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.197 0.968 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.813 2.782 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) 0.539 3.321 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED ------------------------------------------------------------------- ------------------- PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) 0.346 3.667 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/DQSBUS[1] net (fo=1, routed) 0.150 3.817 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/DQSBUS[1] OLOGIC_X1Y182 ODDR r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 ------------------------------------------------------------------- ------------------- (clock oserdes_clk_2 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.218 1.226 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.858 3.084 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) 0.573 3.657 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED net (fo=2, routed) 0.176 3.833 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed OLOGIC_X1Y182 ODDR r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/C clock pessimism -0.336 3.497 OLOGIC_X1Y182 ODDR (Hold_oddr_C_D2) -0.093 3.404 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs ------------------------------------------------------------------- required time -3.404 arrival time 3.817 ------------------------------------------------------------------- slack 0.413 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: oserdes_clk_2 Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a OSERDESE2/CLK n/a 1.667 2.500 0.833 OLOGIC_X1Y176 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK --------------------------------------------------------------------------------------------------- From Clock: oserdes_clkdiv_2 To Clock: oserdes_clkdiv_2 Setup : 0 Failing Endpoints, Worst Slack 3.571ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.092ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.571ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: oserdes_clkdiv_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 5.000ns (oserdes_clkdiv_2 rise@5.000ns - oserdes_clkdiv_2 rise@0.000ns) Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.997%)) Logic Levels: 0 Clock Path Skew: 0.403ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.977ns = ( 10.977 - 5.000 ) Source Clock Delay (SCD): 5.826ns Clock Pessimism Removal (CPR): 0.252ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.109ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_2 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.614 3.533 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.136 5.669 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.157 5.826 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV net (fo=11, routed) 0.000 5.826 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv OUT_FIFO_X1Y14 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK ------------------------------------------------------------------- ------------------- OUT_FIFO_X1Y14 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) 0.674 6.500 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q6[0] net (fo=1, routed) 0.468 6.968 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[20] OLOGIC_X1Y183 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_2 rise edge) 5.000 5.000 r R4 0.000 5.000 r sys_clk_i (IN) net (fo=0) 0.000 5.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 6.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 7.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 7.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.582 8.350 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.077 10.426 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.148 10.574 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV net (fo=11, routed) 0.403 10.977 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv OLOGIC_X1Y183 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV clock pessimism 0.252 11.229 clock uncertainty -0.065 11.164 OLOGIC_X1Y183 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) -0.625 10.539 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i ------------------------------------------------------------------- required time 10.539 arrival time -6.968 ------------------------------------------------------------------- slack 3.571 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.092ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: oserdes_clkdiv_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clkdiv_2 rise@0.000ns) Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) Logic Levels: 0 Clock Path Skew: 0.177ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.349ns Source Clock Delay (SCD): 2.865ns Clock Pessimism Removal (CPR): 0.307ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_2 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.197 0.968 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.813 2.782 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.083 2.865 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV net (fo=11, routed) 0.000 2.865 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv OUT_FIFO_X1Y14 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK ------------------------------------------------------------------- ------------------- OUT_FIFO_X1Y14 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) 0.138 3.003 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[1] net (fo=1, routed) 0.150 3.153 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[5] OLOGIC_X1Y177 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_2 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.218 1.226 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.858 3.084 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.088 3.172 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV net (fo=11, routed) 0.177 3.349 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv OLOGIC_X1Y177 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV clock pessimism -0.307 3.042 OLOGIC_X1Y177 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) 0.019 3.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i ------------------------------------------------------------------- required time -3.061 arrival time 3.153 ------------------------------------------------------------------- slack 0.092 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: oserdes_clkdiv_2 Waveform(ns): { 0.000 2.500 } Period(ns): 5.000 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a OUT_FIFO/RDCLK n/a 5.000 5.000 0.000 OUT_FIFO_X1Y14 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK Low Pulse Width Fast OUT_FIFO/RDCLK n/a 2.150 2.500 0.350 OUT_FIFO_X1Y14 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 2.500 0.350 OUT_FIFO_X1Y14 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK --------------------------------------------------------------------------------------------------- From Clock: oserdes_clk_3 To Clock: oserdes_clk_3 Setup : 0 Failing Endpoints, Worst Slack 0.929ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.408ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.929ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: oserdes_clk_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (oserdes_clk_3 rise@2.500ns - oserdes_clk_3 rise@0.000ns) Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) Logic Levels: 0 Clock Path Skew: 0.416ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 6.473ns = ( 8.973 - 2.500 ) Source Clock Delay (SCD): 6.338ns Clock Pessimism Removal (CPR): 0.281ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.109ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clk_3 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.603 3.522 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.136 5.658 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) 0.679 6.338 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED ------------------------------------------------------------------- ------------------- PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) 0.562 6.900 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/CTSBUS[0] net (fo=2, routed) 0.475 7.375 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CTSBUS[0] OLOGIC_X1Y194 ODDR r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 ------------------------------------------------------------------- ------------------- (clock oserdes_clk_3 rise edge) 2.500 2.500 r R4 0.000 2.500 r sys_clk_i (IN) net (fo=0) 0.000 2.500 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 3.905 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 5.185 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 5.268 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.572 5.840 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.077 7.916 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) 0.641 8.557 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED net (fo=2, routed) 0.416 8.973 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed OLOGIC_X1Y194 ODDR r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/C clock pessimism 0.281 9.254 clock uncertainty -0.065 9.189 OLOGIC_X1Y194 ODDR (Setup_oddr_C_D1) -0.885 8.304 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts ------------------------------------------------------------------- required time 8.304 arrival time -7.375 ------------------------------------------------------------------- slack 0.929 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.408ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: oserdes_clk_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (oserdes_clk_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) Logic Levels: 0 Clock Path Skew: 0.181ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.829ns Source Clock Delay (SCD): 3.314ns Clock Pessimism Removal (CPR): 0.334ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clk_3 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.190 0.961 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.813 2.775 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) 0.539 3.314 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED ------------------------------------------------------------------- ------------------- PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) 0.346 3.660 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/DQSBUS[1] net (fo=1, routed) 0.150 3.810 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/DQSBUS[1] OLOGIC_X1Y194 ODDR r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 ------------------------------------------------------------------- ------------------- (clock oserdes_clk_3 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.209 1.217 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.858 3.075 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) 0.573 3.648 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED net (fo=2, routed) 0.181 3.829 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed OLOGIC_X1Y194 ODDR r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/C clock pessimism -0.334 3.495 OLOGIC_X1Y194 ODDR (Hold_oddr_C_D2) -0.093 3.402 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs ------------------------------------------------------------------- required time -3.402 arrival time 3.810 ------------------------------------------------------------------- slack 0.408 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: oserdes_clk_3 Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a OSERDESE2/CLK n/a 1.667 2.500 0.833 OLOGIC_X1Y187 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[0].oserdes_dq_.ddr.oserdes_dq_i/CLK --------------------------------------------------------------------------------------------------- From Clock: oserdes_clkdiv_3 To Clock: oserdes_clkdiv_3 Setup : 0 Failing Endpoints, Worst Slack 3.587ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.086ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.587ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: oserdes_clkdiv_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 5.000ns (oserdes_clkdiv_3 rise@5.000ns - oserdes_clkdiv_3 rise@0.000ns) Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.997%)) Logic Levels: 0 Clock Path Skew: 0.419ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.983ns = ( 10.983 - 5.000 ) Source Clock Delay (SCD): 5.815ns Clock Pessimism Removal (CPR): 0.251ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.109ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_3 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.603 3.522 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.136 5.658 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.157 5.815 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV net (fo=11, routed) 0.000 5.815 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv OUT_FIFO_X1Y15 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK ------------------------------------------------------------------- ------------------- OUT_FIFO_X1Y15 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) 0.674 6.489 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q6[0] net (fo=1, routed) 0.468 6.957 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[20] OLOGIC_X1Y195 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_3 rise edge) 5.000 5.000 r R4 0.000 5.000 r sys_clk_i (IN) net (fo=0) 0.000 5.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 6.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 7.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 7.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.572 8.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.077 10.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.148 10.564 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV net (fo=11, routed) 0.419 10.983 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv OLOGIC_X1Y195 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV clock pessimism 0.251 11.234 clock uncertainty -0.065 11.169 OLOGIC_X1Y195 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) -0.625 10.544 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i ------------------------------------------------------------------- required time 10.544 arrival time -6.957 ------------------------------------------------------------------- slack 3.587 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.086ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: oserdes_clkdiv_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clkdiv_3 rise@0.000ns) Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) Logic Levels: 0 Clock Path Skew: 0.183ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.346ns Source Clock Delay (SCD): 2.858ns Clock Pessimism Removal (CPR): 0.305ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_3 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.190 0.961 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.813 2.775 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.083 2.858 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV net (fo=11, routed) 0.000 2.858 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv OUT_FIFO_X1Y15 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK ------------------------------------------------------------------- ------------------- OUT_FIFO_X1Y15 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) 0.138 2.996 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q2[1] net (fo=1, routed) 0.150 3.146 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[9] OLOGIC_X1Y189 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_3 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.209 1.217 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.858 3.075 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.088 3.163 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV net (fo=11, routed) 0.183 3.346 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv OLOGIC_X1Y189 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV clock pessimism -0.305 3.041 OLOGIC_X1Y189 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) 0.019 3.060 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i ------------------------------------------------------------------- required time -3.060 arrival time 3.146 ------------------------------------------------------------------- slack 0.086 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: oserdes_clkdiv_3 Waveform(ns): { 0.000 2.500 } Period(ns): 5.000 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a OUT_FIFO/RDCLK n/a 5.000 5.000 0.000 OUT_FIFO_X1Y15 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK Low Pulse Width Fast OUT_FIFO/RDCLK n/a 2.150 2.500 0.350 OUT_FIFO_X1Y15 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 2.500 0.350 OUT_FIFO_X1Y15 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK --------------------------------------------------------------------------------------------------- From Clock: pll_clk3_out To Clock: pll_clk3_out Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: pll_clk3_out Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFH/I n/a 2.155 10.000 7.845 BUFHCE_X1Y36 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/I Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_pll_i To Clock: clk_pll_i Setup : 6 Failing Endpoints, Worst Slack -0.152ns, Total Violation -0.471ns Hold : 0 Failing Endpoints, Worst Slack 0.052ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -0.152ns (required time - arrival time) Source: hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Tag_RAM_Module/Not_Using_XPM.Using_B36_S36.The_BRAMs[0].RAMB36_I1/Using_FPGA.Native/CLKARDCLK (rising edge-triggered cell RAMB36E1 clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/stream_addr_reg[2]/D (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_pll_i Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_pll_i rise@10.000ns - clk_pll_i rise@0.000ns) Data Path Delay: 10.022ns (logic 5.692ns (56.795%) route 4.330ns (43.205%)) Logic Levels: 14 (CARRY4=8 LUT2=1 LUT3=1 LUT4=1 LUT6=3) Clock Path Skew: -0.178ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.969ns = ( 14.969 - 10.000 ) Source Clock Delay (SCD): 5.346ns Clock Pessimism Removal (CPR): 0.199ns Clock Uncertainty: 0.060ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.098ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.716 5.346 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Tag_RAM_Module/Not_Using_XPM.Using_B36_S36.The_BRAMs[0].RAMB36_I1/Clk RAMB36_X2Y28 RAMB36E1 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Tag_RAM_Module/Not_Using_XPM.Using_B36_S36.The_BRAMs[0].RAMB36_I1/Using_FPGA.Native/CLKARDCLK ------------------------------------------------------------------- ------------------- RAMB36_X2Y28 RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[10]) 2.454 7.800 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Tag_RAM_Module/Not_Using_XPM.Using_B36_S36.The_BRAMs[0].RAMB36_I1/Using_FPGA.Native/DOADO[10] net (fo=2, routed) 0.911 8.711 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Tag_RAM_Module/Not_Using_XPM.Using_B36_S36.The_BRAMs[0].RAMB36_I1/D[1] SLICE_X43Y145 LUT6 (Prop_lut6_I3_O) 0.124 8.835 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Tag_RAM_Module/Not_Using_XPM.Using_B36_S36.The_BRAMs[0].RAMB36_I1/Using_FPGA.Native_i_1__182/O net (fo=1, routed) 0.000 8.835 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_FPGA_FSL_1.tag_hit_comparator/Using_Extra_Carry.MUXCY_EXTRA_I/lopt_3 SLICE_X43Y145 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 9.385 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_FPGA_FSL_1.tag_hit_comparator/Using_Extra_Carry.MUXCY_EXTRA_I/Using_FPGA.Native_CARRY4/CO[3] net (fo=1, routed) 0.000 9.385 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_FPGA_FSL_1.tag_hit_comparator/Comp_Carry_Chain[3].MUXCY_I/carry_chain_2 SLICE_X43Y146 CARRY4 (Prop_carry4_CI_CO[1]) 0.157 9.542 f hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_FPGA_FSL_1.tag_hit_comparator/Comp_Carry_Chain[3].MUXCY_I/Using_FPGA.Native_CARRY4/CO[1] net (fo=7, routed) 0.723 10.265 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_FPGA_FSL_1.tag_hit_comparator/Comp_Carry_Chain[4].MUXCY_I/req_Addr_reg[3] SLICE_X45Y149 LUT3 (Prop_lut3_I0_O) 0.323 10.588 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_FPGA_FSL_1.tag_hit_comparator/Comp_Carry_Chain[4].MUXCY_I/req_Addr[3]_i_1/O net (fo=29, routed) 0.839 11.427 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Victim_Cache.victim_cache_I1/E[0] SLICE_X46Y152 LUT6 (Prop_lut6_I5_O) 0.326 11.753 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Victim_Cache.victim_cache_I1/Using_FPGA.Native_i_3__41/O net (fo=7, routed) 0.480 12.233 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Victim_Cache.victim_cache_I1/cache_req_raw SLICE_X47Y154 LUT4 (Prop_lut4_I1_O) 0.124 12.357 f hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Victim_Cache.victim_cache_I1/Using_AXI.M_AXI_ARADDR_I[31]_i_4/O net (fo=37, routed) 0.493 12.850 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Victim_Cache.victim_cache_I1/in[1] SLICE_X49Y151 LUT6 (Prop_lut6_I0_O) 0.124 12.974 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Victim_Cache.victim_cache_I1/Using_FPGA.Native_I1_i_2__4/O net (fo=56, routed) 0.403 13.377 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Victim_Cache.victim_cache_I1/clear_stream_cache_fetch SLICE_X50Y151 LUT2 (Prop_lut2_I0_O) 0.124 13.501 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Victim_Cache.victim_cache_I1/Using_FPGA.Native_I1_i_2__3/O net (fo=1, routed) 0.481 13.982 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Addr_Handler[23].MUXCY_XOR_I/CI SLICE_X48Y150 CARRY4 (Prop_carry4_CYINIT_CO[3]) 0.595 14.577 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Addr_Handler[23].MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4/CO[3] net (fo=1, routed) 0.000 14.577 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Addr_Handler[19].MUXCY_XOR_I/Not_Using_TLBS.instr_Addr_1_reg[23] SLICE_X48Y151 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 14.694 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Addr_Handler[19].MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4/CO[3] net (fo=1, routed) 0.000 14.694 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Addr_Handler[15].MUXCY_XOR_I/Not_Using_TLBS.instr_Addr_1_reg[19] SLICE_X48Y152 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 14.811 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Addr_Handler[15].MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4/CO[3] net (fo=1, routed) 0.000 14.811 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Addr_Handler[11].MUXCY_XOR_I/Not_Using_TLBS.instr_Addr_1_reg[15] SLICE_X48Y153 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 14.928 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Addr_Handler[11].MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4/CO[3] net (fo=1, routed) 0.000 14.928 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Addr_Handler[7].MUXCY_XOR_I/Not_Using_TLBS.instr_Addr_1_reg[11] SLICE_X48Y154 CARRY4 (Prop_carry4_CI_CO[3]) 0.117 15.045 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Addr_Handler[7].MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4/CO[3] net (fo=1, routed) 0.000 15.045 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Addr_Handler[3].MUXCY_XOR_I/Not_Using_TLBS.instr_Addr_1_reg[7] SLICE_X48Y155 CARRY4 (Prop_carry4_CI_O[1]) 0.323 15.368 r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Addr_Handler[3].MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4/O[1] net (fo=1, routed) 0.000 15.368 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/stream_addr_I[2] SLICE_X48Y155 FDRE r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/stream_addr_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 12.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 12.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.289 14.057 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.081 14.138 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.904 15.042 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.425 11.617 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.723 13.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.538 14.969 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/Clk SLICE_X48Y155 FDRE r hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/stream_addr_reg[2]/C clock pessimism 0.199 15.168 clock uncertainty -0.060 15.108 SLICE_X48Y155 FDRE (Setup_fdre_C_D) 0.109 15.217 hdmi_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Using_Stream.stream_cache_I1/stream_addr_reg[2] ------------------------------------------------------------------- required time 15.217 arrival time -15.368 ------------------------------------------------------------------- slack -0.152 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.052ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall1_r_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0]/D (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_pll_i Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) Data Path Delay: 0.464ns (logic 0.141ns (30.384%) route 0.323ns (69.616%)) Logic Levels: 0 Clock Path Skew: 0.360ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.150ns Source Clock Delay (SCD): 1.522ns Clock Pessimism Removal (CPR): 0.267ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.591 1.522 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/CLK SLICE_X133Y193 FDRE r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall1_r_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y193 FDRE (Prop_fdre_C_Q) 0.141 1.663 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall1_r_reg[2]/Q net (fo=1, routed) 0.323 1.986 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] SLICE_X124Y203 FDRE r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0]/D ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.472 1.480 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.043 1.523 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.538 2.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.475 0.586 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.579 1.164 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.193 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.956 2.150 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/CLK SLICE_X124Y203 FDRE r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0]/C clock pessimism -0.267 1.883 SLICE_X124Y203 FDRE (Hold_fdre_C_D) 0.052 1.935 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0] ------------------------------------------------------------------- required time -1.935 arrival time 1.986 ------------------------------------------------------------------- slack 0.052 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_pll_i Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a OUT_FIFO/WRCLK n/a 5.000 10.000 5.000 OUT_FIFO_X1Y12 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y1 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKIN1 Low Pulse Width Fast MMCME2_ADV/DCLK n/a 2.500 5.000 2.501 MMCME2_ADV_X1Y1 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/DCLK High Pulse Width Slow MMCME2_ADV/DCLK n/a 2.500 5.000 2.500 MMCME2_ADV_X1Y1 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/DCLK --------------------------------------------------------------------------------------------------- From Clock: mmcm_clk To Clock: mmcm_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.333ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: mmcm_clk Waveform(ns): { 0.000 1.000 } Period(ns): 2.000 Sources: { hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a OSERDESE2/CLK n/a 1.667 2.000 0.333 OLOGIC_X1Y148 hdmi_i/rgb2dvi_0/U0/ClockSerializer/SerializerMaster/CLK Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 2.000 211.360 MMCME2_ADV_X1Y1 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 --------------------------------------------------------------------------------------------------- From Clock: axi_dynclk_0_PXL_CLK_O To Clock: axi_dynclk_0_PXL_CLK_O Setup : 0 Failing Endpoints, Worst Slack 2.131ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.106ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.131ns (required time - arrival time) Source: hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.soft_resetn_reg/C (rising edge-triggered cell FDRE clocked by axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Destination: hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/GEN_HAS_IRQ.intr_err_reg[5]/R (rising edge-triggered cell FDRE clocked by axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Path Group: axi_dynclk_0_PXL_CLK_O Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (axi_dynclk_0_PXL_CLK_O rise@10.000ns - axi_dynclk_0_PXL_CLK_O rise@0.000ns) Data Path Delay: 7.281ns (logic 0.580ns (7.966%) route 6.701ns (92.034%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.004ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 11.417ns = ( 21.417 - 10.000 ) Source Clock Delay (SCD): 12.134ns Clock Pessimism Removal (CPR): 0.713ns Clock Uncertainty: 0.060ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.097ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_dynclk_0_PXL_CLK_O rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.918 5.549 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/REF_CLK_I MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.088 5.637 r hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 3.038 8.675 hdmi_i/axi_dynclk_0/U0/mmcm_clk BUFMRCE_X1Y2 BUFMR (Prop_bufmr_I_O) 0.103 8.778 r hdmi_i/axi_dynclk_0/U0/GenerateBUFMR.BUFMR_inst/O net (fo=2, routed) 1.394 10.172 hdmi_i/axi_dynclk_0/U0/I BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.982 11.154 r hdmi_i/axi_dynclk_0/U0/BUFR_inst/O net (fo=3041, routed) 0.980 12.134 hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/vid_aclk SLICE_X111Y115 FDRE r hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.soft_resetn_reg/C ------------------------------------------------------------------- ------------------- SLICE_X111Y115 FDRE (Prop_fdre_C_Q) 0.456 12.590 f hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.soft_resetn_reg/Q net (fo=60, routed) 1.871 14.461 hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/resetn_out SLICE_X121Y112 LUT1 (Prop_lut1_I0_O) 0.124 14.585 r hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/GEN_HAS_IRQ.irq_i_1/O net (fo=1004, routed) 4.830 19.415 hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/GEN_HAS_IRQ.irq_i_1_n_0 SLICE_X90Y104 FDRE r hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/GEN_HAS_IRQ.intr_err_reg[5]/R ------------------------------------------------------------------- ------------------- (clock axi_dynclk_0_PXL_CLK_O rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 12.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 12.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.289 14.057 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.081 14.138 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.904 15.042 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.425 11.617 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.723 13.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.792 15.223 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/REF_CLK_I MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.083 15.306 r hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 2.848 18.154 hdmi_i/axi_dynclk_0/U0/mmcm_clk BUFMRCE_X1Y2 BUFMR (Prop_bufmr_I_O) 0.097 18.251 r hdmi_i/axi_dynclk_0/U0/GenerateBUFMR.BUFMR_inst/O net (fo=2, routed) 1.289 19.540 hdmi_i/axi_dynclk_0/U0/I BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.918 20.458 r hdmi_i/axi_dynclk_0/U0/BUFR_inst/O net (fo=3041, routed) 0.959 21.417 hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/vid_aclk SLICE_X90Y104 FDRE r hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/GEN_HAS_IRQ.intr_err_reg[5]/C clock pessimism 0.713 22.130 clock uncertainty -0.060 22.070 SLICE_X90Y104 FDRE (Setup_fdre_C_R) -0.524 21.546 hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/GEN_HAS_IRQ.intr_err_reg[5] ------------------------------------------------------------------- required time 21.546 arrival time -19.415 ------------------------------------------------------------------- slack 2.131 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.106ns (arrival time - required time) Source: hdmi_i/rgb2dvi_0/U0/DataEncoders[2].DataEncoder/q_m_2_reg[3]/C (rising edge-triggered cell FDRE clocked by axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Destination: hdmi_i/rgb2dvi_0/U0/DataEncoders[2].DataEncoder/pDataOutRaw_reg[3]/D (rising edge-triggered cell FDRE clocked by axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Path Group: axi_dynclk_0_PXL_CLK_O Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (axi_dynclk_0_PXL_CLK_O rise@0.000ns - axi_dynclk_0_PXL_CLK_O rise@0.000ns) Data Path Delay: 0.240ns (logic 0.186ns (77.467%) route 0.054ns (22.534%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 4.742ns Source Clock Delay (SCD): 3.641ns Clock Pessimism Removal (CPR): 1.088ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_dynclk_0_PXL_CLK_O rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.671 1.603 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/REF_CLK_I MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.050 1.653 r hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.945 2.598 hdmi_i/axi_dynclk_0/U0/mmcm_clk BUFMRCE_X1Y2 BUFMR (Prop_bufmr_I_O) 0.033 2.631 r hdmi_i/axi_dynclk_0/U0/GenerateBUFMR.BUFMR_inst/O net (fo=2, routed) 0.487 3.118 hdmi_i/axi_dynclk_0/U0/I BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.270 3.388 r hdmi_i/axi_dynclk_0/U0/BUFR_inst/O net (fo=3041, routed) 0.253 3.641 hdmi_i/rgb2dvi_0/U0/DataEncoders[2].DataEncoder/PixelClk SLICE_X163Y122 FDRE r hdmi_i/rgb2dvi_0/U0/DataEncoders[2].DataEncoder/q_m_2_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X163Y122 FDRE (Prop_fdre_C_Q) 0.141 3.782 r hdmi_i/rgb2dvi_0/U0/DataEncoders[2].DataEncoder/q_m_2_reg[3]/Q net (fo=1, routed) 0.054 3.836 hdmi_i/rgb2dvi_0/U0/DataEncoders[2].DataEncoder/q_m_2_reg_n_0_[3] SLICE_X162Y122 LUT2 (Prop_lut2_I1_O) 0.045 3.881 r hdmi_i/rgb2dvi_0/U0/DataEncoders[2].DataEncoder/pDataOutRaw[3]_i_1__1/O net (fo=1, routed) 0.000 3.881 hdmi_i/rgb2dvi_0/U0/DataEncoders[2].DataEncoder/pDataOutRaw[3]_i_1__1_n_0 SLICE_X162Y122 FDRE r hdmi_i/rgb2dvi_0/U0/DataEncoders[2].DataEncoder/pDataOutRaw_reg[3]/D ------------------------------------------------------------------- ------------------- (clock axi_dynclk_0_PXL_CLK_O rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.472 1.480 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.043 1.523 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.538 2.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.475 0.586 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.579 1.164 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.193 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.944 2.137 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/REF_CLK_I MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.053 2.190 r hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.256 3.446 hdmi_i/axi_dynclk_0/U0/mmcm_clk BUFMRCE_X1Y2 BUFMR (Prop_bufmr_I_O) 0.035 3.481 r hdmi_i/axi_dynclk_0/U0/GenerateBUFMR.BUFMR_inst/O net (fo=2, routed) 0.544 4.025 hdmi_i/axi_dynclk_0/U0/I BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.431 4.456 r hdmi_i/axi_dynclk_0/U0/BUFR_inst/O net (fo=3041, routed) 0.286 4.742 hdmi_i/rgb2dvi_0/U0/DataEncoders[2].DataEncoder/PixelClk SLICE_X162Y122 FDRE r hdmi_i/rgb2dvi_0/U0/DataEncoders[2].DataEncoder/pDataOutRaw_reg[3]/C clock pessimism -1.088 3.654 SLICE_X162Y122 FDRE (Hold_fdre_C_D) 0.121 3.775 hdmi_i/rgb2dvi_0/U0/DataEncoders[2].DataEncoder/pDataOutRaw_reg[3] ------------------------------------------------------------------- required time -3.775 arrival time 3.881 ------------------------------------------------------------------- slack 0.106 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: axi_dynclk_0_PXL_CLK_O Waveform(ns): { 0.000 4.000 } Period(ns): 10.000 Sources: { hdmi_i/axi_dynclk_0/U0/BUFR_inst/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a FIFO36E1/RDCLK n/a 2.576 10.000 7.424 RAMB36_X6Y25 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RDCLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 6.000 4.750 SLICE_X152Y116 hdmi_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_sync_fifo.FIFO_INST/XPM_FIFO_SYNC_INST/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 4.000 2.750 SLICE_X152Y116 hdmi_i/v_axi4s_vid_out_0/inst/COUPLER_INST/generate_sync_fifo.FIFO_INST/XPM_FIFO_SYNC_INST/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: mmcm_fbclk_out To Clock: mmcm_fbclk_out Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 8.751ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: mmcm_fbclk_out Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y1 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKFBOUT Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y1 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: mmcm_clkout0 To Clock: mmcm_clkout0 Setup : 0 Failing Endpoints, Worst Slack 0.920ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.104ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.145ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.920ns (required time - arrival time) Source: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/WRCLK (rising edge-triggered cell FIFO36E1 clocked by mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Destination: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/WREN (rising edge-triggered cell FIFO36E1 clocked by mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Path Group: mmcm_clkout0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.250ns (mmcm_clkout0 rise@6.250ns - mmcm_clkout0 rise@0.000ns) Data Path Delay: 4.504ns (logic 1.289ns (28.618%) route 3.215ns (71.382%)) Logic Levels: 2 (LUT5=2) Clock Path Skew: -0.285ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.111ns = ( 11.361 - 6.250 ) Source Clock Delay (SCD): 5.602ns Clock Pessimism Removal (CPR): 0.206ns Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.133ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout0 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0 net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout0 BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_0/O net (fo=624, routed) 1.972 5.602 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/s_axis_s2mm_aclk RAMB36_X7Y19 FIFO36E1 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/WRCLK ------------------------------------------------------------------- ------------------- RAMB36_X7Y19 FIFO36E1 (Prop_fifo36e1_WRCLK_FULL) 1.041 6.643 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/FULL net (fo=1, routed) 1.100 7.743 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/sig_s_ready_out_reg_1 SLICE_X141Y113 LUT5 (Prop_lut5_I4_O) 0.124 7.867 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_13__0/O net (fo=2, routed) 0.752 8.619 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/fifo_full_i SLICE_X141Y125 LUT5 (Prop_lut5_I1_O) 0.124 8.743 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1_i_3__2/O net (fo=5, routed) 1.364 10.106 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/WR_EN RAMB36_X7Y20 FIFO36E1 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/WREN ------------------------------------------------------------------- ------------------- (clock mmcm_clkout0 rise edge) 6.250 6.250 r R4 0.000 6.250 r sys_clk_i (IN) net (fo=0) 0.000 6.250 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 7.655 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 8.935 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 9.018 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.289 10.307 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.081 10.388 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.904 11.292 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.425 7.867 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0 net (fo=1, routed) 1.723 9.590 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout0 BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 9.681 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_0/O net (fo=624, routed) 1.680 11.361 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/s_axis_s2mm_aclk RAMB36_X7Y20 FIFO36E1 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/WRCLK clock pessimism 0.206 11.567 clock uncertainty -0.075 11.492 RAMB36_X7Y20 FIFO36E1 (Setup_fifo36e1_WRCLK_WREN) -0.466 11.026 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1 ------------------------------------------------------------------- required time 11.026 arrival time -10.106 ------------------------------------------------------------------- slack 0.920 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.104ns (arrival time - required time) Source: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_AXIS_S2MM_DWIDTH_CONV.AXIS_S2MM_DWIDTH_CONVERTER_I/GEN_DWIDTH_FLUSH_SOF.S2MM_AXIS_DWIDTH_CONVERTER_I/gen_downsizer_conversion.axisc_downsizer_0/r1_data_reg[13]/C (rising edge-triggered cell FDRE clocked by mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Destination: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/DI[4] (rising edge-triggered cell FIFO36E1 clocked by mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Path Group: mmcm_clkout0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns) Data Path Delay: 0.456ns (logic 0.186ns (40.830%) route 0.270ns (59.170%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.055ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.120ns Source Clock Delay (SCD): 1.547ns Clock Pessimism Removal (CPR): 0.518ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout0 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0 net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout0 BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_0/O net (fo=624, routed) 0.616 1.547 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_AXIS_S2MM_DWIDTH_CONV.AXIS_S2MM_DWIDTH_CONVERTER_I/GEN_DWIDTH_FLUSH_SOF.S2MM_AXIS_DWIDTH_CONVERTER_I/gen_downsizer_conversion.axisc_downsizer_0/s_axis_s2mm_aclk SLICE_X141Y115 FDRE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_AXIS_S2MM_DWIDTH_CONV.AXIS_S2MM_DWIDTH_CONVERTER_I/GEN_DWIDTH_FLUSH_SOF.S2MM_AXIS_DWIDTH_CONVERTER_I/gen_downsizer_conversion.axisc_downsizer_0/r1_data_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y115 FDRE (Prop_fdre_C_Q) 0.141 1.688 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_AXIS_S2MM_DWIDTH_CONV.AXIS_S2MM_DWIDTH_CONVERTER_I/GEN_DWIDTH_FLUSH_SOF.S2MM_AXIS_DWIDTH_CONVERTER_I/gen_downsizer_conversion.axisc_downsizer_0/r1_data_reg[13]/Q net (fo=1, routed) 0.109 1.797 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_AXIS_S2MM_DWIDTH_CONV.AXIS_S2MM_DWIDTH_CONVERTER_I/GEN_DWIDTH_FLUSH_SOF.S2MM_AXIS_DWIDTH_CONVERTER_I/gen_downsizer_conversion.axisc_downsizer_0/r1_data[13] SLICE_X141Y115 LUT5 (Prop_lut5_I2_O) 0.045 1.842 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_AXIS_S2MM_DWIDTH_CONV.AXIS_S2MM_DWIDTH_CONVERTER_I/GEN_DWIDTH_FLUSH_SOF.S2MM_AXIS_DWIDTH_CONVERTER_I/gen_downsizer_conversion.axisc_downsizer_0/gf36e1_inst.sngfifo36e1_i_4__5/O net (fo=1, routed) 0.160 2.003 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/p_91_out[4] RAMB36_X7Y23 FIFO36E1 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/DI[4] ------------------------------------------------------------------- ------------------- (clock mmcm_clkout0 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.472 1.480 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.043 1.523 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.538 2.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.475 0.586 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0 net (fo=1, routed) 0.579 1.164 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout0 BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 1.193 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_0/O net (fo=624, routed) 0.927 2.120 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/s_axis_s2mm_aclk RAMB36_X7Y23 FIFO36E1 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/WRCLK clock pessimism -0.518 1.603 RAMB36_X7Y23 FIFO36E1 (Hold_fifo36e1_WRCLK_DI[4]) 0.296 1.899 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[2].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1 ------------------------------------------------------------------- required time -1.899 arrival time 2.003 ------------------------------------------------------------------- slack 0.104 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: mmcm_clkout0 Waveform(ns): { 0.000 3.125 } Period(ns): 6.250 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a FIFO36E1/WRCLK n/a 2.576 6.250 3.674 RAMB36_X7Y22 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/WRCLK Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 6.250 207.110 MMCME2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0 Low Pulse Width Slow SRL16E/CLK n/a 0.980 3.125 2.145 SLICE_X136Y108 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_fb_reg[1]_srl4/CLK High Pulse Width Slow SRL16E/CLK n/a 0.980 3.125 2.145 SLICE_X148Y132 hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_rd_inst/gen_pipe_bit[1].pipe_bit_inst/d_out_reg_srl2/CLK --------------------------------------------------------------------------------------------------- From Clock: mmcm_clkout1 To Clock: mmcm_clkout1 Setup : 81 Failing Endpoints, Worst Slack -0.975ns, Total Violation -18.395ns Hold : 0 Failing Endpoints, Worst Slack 0.081ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -0.975ns (required time - arrival time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[2]/C (rising edge-triggered cell FDRE clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/read_addr_reg[1]/CE (rising edge-triggered cell FDRE clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: mmcm_clkout1 Path Type: Setup (Max at Slow Process Corner) Requirement: 5.000ns (mmcm_clkout1 rise@5.000ns - mmcm_clkout1 rise@0.000ns) Data Path Delay: 5.797ns (logic 1.514ns (26.115%) route 4.283ns (73.885%)) Logic Levels: 4 (LUT2=1 LUT5=1 LUT6=2) Clock Path Skew: 0.100ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.310ns = ( 10.310 - 5.000 ) Source Clock Delay (SCD): 5.497ns Clock Pessimism Removal (CPR): 0.287ns Clock Uncertainty: 0.073ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.127ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.866 5.497 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1] SLICE_X135Y93 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X135Y93 FDRE (Prop_fdre_C_Q) 0.419 5.916 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_daddr_r_reg[2]/Q net (fo=104, routed) 1.414 7.330 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/s_daddr[2] SLICE_X151Y96 LUT2 (Prop_lut2_I0_O) 0.325 7.655 f hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_reg[15]_i_3__3/O net (fo=3, routed) 0.976 8.630 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/G_1PIPE_IFACE.s_daddr_r_reg[2] SLICE_X149Y94 LUT6 (Prop_lut6_I5_O) 0.326 8.956 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/current_state[5]_i_2/O net (fo=6, routed) 0.890 9.847 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/read_data_en SLICE_X159Y97 LUT5 (Prop_lut5_I1_O) 0.118 9.965 f hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/current_state[6]_i_2/O net (fo=2, routed) 0.448 10.412 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/current_state[6]_i_2_n_0 SLICE_X157Y95 LUT6 (Prop_lut6_I0_O) 0.326 10.738 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/read_addr[10]_i_1/O net (fo=11, routed) 0.556 11.294 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/read_addr SLICE_X156Y95 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/read_addr_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 5.000 5.000 r R4 0.000 5.000 r sys_clk_i (IN) net (fo=0) 0.000 5.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 6.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 7.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 7.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.289 9.057 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.081 9.138 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.904 10.042 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -3.425 6.617 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 1.723 8.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.879 10.310 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/s_dclk_o SLICE_X156Y95 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/read_addr_reg[1]/C clock pessimism 0.287 10.597 clock uncertainty -0.073 10.524 SLICE_X156Y95 FDRE (Setup_fdre_C_CE) -0.205 10.319 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/read_addr_reg[1] ------------------------------------------------------------------- required time 10.319 arrival time -11.294 ------------------------------------------------------------------- slack -0.975 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.081ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/input_data_reg[5]/C (rising edge-triggered cell FDRE clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/reg_stream_ffe/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]/D (rising edge-triggered cell FDRE clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: mmcm_clkout1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mmcm_clkout1 rise@0.000ns - mmcm_clkout1 rise@0.000ns) Data Path Delay: 0.540ns (logic 0.226ns (41.887%) route 0.314ns (58.113%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.338ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.159ns Source Clock Delay (SCD): 1.554ns Clock Pessimism Removal (CPR): 0.267ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 0.623 1.554 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/s_dclk_o SLICE_X155Y105 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/input_data_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X155Y105 FDRE (Prop_fdre_C_Q) 0.128 1.682 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/input_data_reg[5]/Q net (fo=1, routed) 0.314 1.996 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/input_data[5] SLICE_X154Y99 LUT3 (Prop_lut3_I2_O) 0.098 2.094 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/xsdb_memory_read_inst/xsdb_reg[5]_i_1/O net (fo=1, routed) 0.000 2.094 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/reg_stream_ffe/I_EN_STAT_EQ1.U_STAT/D[5] SLICE_X154Y99 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/reg_stream_ffe/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.472 1.480 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.043 1.523 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.538 2.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -1.475 0.586 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 0.579 1.164 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 1.193 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 0.966 2.159 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/reg_stream_ffe/I_EN_STAT_EQ1.U_STAT/s_dclk_o SLICE_X154Y99 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/reg_stream_ffe/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5]/C clock pessimism -0.267 1.892 SLICE_X154Y99 FDRE (Hold_fdre_C_D) 0.121 2.013 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/reg_stream_ffe/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[5] ------------------------------------------------------------------- required time -2.013 arrival time 2.094 ------------------------------------------------------------------- slack 0.081 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: mmcm_clkout1 Waveform(ns): { 0.000 2.500 } Period(ns): 5.000 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a XADC/DCLK n/a 4.000 5.000 1.000 XADC_X0Y0 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.XADC_inst/DCLK Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 2.500 1.250 SLICE_X108Y86 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 2.500 1.250 SLICE_X108Y86 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: pll_clkfbout To Clock: pll_clkfbout Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 8.751ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: pll_clkfbout Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 PLLE2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 10.000 42.633 PLLE2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: sync_pulse To Clock: sync_pulse Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 1.250ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sync_pulse Waveform(ns): { 1.094 3.594 } Period(ns): 40.000 Sources: { hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 40.000 38.751 PLLE2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 40.000 120.000 PLLE2_ADV_X1Y3 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 High Pulse Width Slow PHASER_OUT_PHY/SYNCIN n/a 1.250 2.500 1.250 PHASER_OUT_PHY_X1Y12 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/SYNCIN --------------------------------------------------------------------------------------------------- From Clock: tmds_clk_pin To Clock: tmds_clk_pin Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 4.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: tmds_clk_pin Waveform(ns): { 0.000 6.250 } Period(ns): 12.500 Sources: { TMDS_IN_clk_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 12.500 11.251 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 12.500 87.500 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.500 6.250 4.750 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 1.500 6.250 4.750 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: CLKFBIN_1 To Clock: CLKFBIN_1 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 11.251ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: CLKFBIN_1 Waveform(ns): { 0.000 6.250 } Period(ns): 12.500 Sources: { hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 12.500 11.251 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKFBOUT Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 12.500 87.500 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: CLK_OUT_5x_hdmi_clk_1 To Clock: CLK_OUT_5x_hdmi_clk_1 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: CLK_OUT_5x_hdmi_clk_1 Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a ISERDESE2/CLK n/a 1.667 2.500 0.833 ILOGIC_X1Y132 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/InputSERDES_X/DeserializerMaster/CLK Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 2.500 210.860 MMCME2_ADV_X1Y2 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 --------------------------------------------------------------------------------------------------- From Clock: dvi2rgb_0_PixelClk_1 To Clock: dvi2rgb_0_PixelClk_1 Setup : 0 Failing Endpoints, Worst Slack 8.273ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.107ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 8.273ns (required time - arrival time) Source: hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int_reg[5]/C (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Destination: hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9]/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: dvi2rgb_0_PixelClk_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 12.500ns (dvi2rgb_0_PixelClk_1 rise@12.500ns - dvi2rgb_0_PixelClk_1 rise@0.000ns) Data Path Delay: 4.220ns (logic 2.772ns (65.680%) route 1.448ns (34.320%)) Logic Levels: 7 (CARRY4=5 LUT2=1 LUT3=1) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.965ns = ( 17.465 - 12.500 ) Source Clock Delay (SCD): 5.244ns Clock Pessimism Removal (CPR): 0.264ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.960 0.960 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.233 2.193 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.089 2.282 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 1.025 3.307 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.982 4.289 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.955 5.244 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/clk SLICE_X127Y125 FDRE r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y125 FDRE (Prop_fdre_C_Q) 0.456 5.700 f hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int_reg[5]/Q net (fo=16, routed) 0.798 6.498 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int[5] SLICE_X127Y126 LUT2 (Prop_lut2_I0_O) 0.124 6.622 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[0]_i_13/O net (fo=1, routed) 0.000 6.622 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[0]_i_13_n_0 SLICE_X127Y126 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 7.172 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_3/CO[3] net (fo=1, routed) 0.000 7.172 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_3_n_0 SLICE_X127Y127 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 7.443 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_2/CO[0] net (fo=24, routed) 0.650 8.094 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_2_n_3 SLICE_X127Y129 LUT3 (Prop_lut3_I1_O) 0.373 8.467 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[3]_i_8/O net (fo=1, routed) 0.000 8.467 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[3]_i_8_n_0 SLICE_X127Y129 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 9.017 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 9.017 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[3]_i_1_n_0 SLICE_X127Y130 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 9.131 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[7]_i_1/CO[3] net (fo=1, routed) 0.000 9.131 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[7]_i_1_n_0 SLICE_X127Y131 CARRY4 (Prop_carry4_CI_O[1]) 0.334 9.465 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[11]_i_1/O[1] net (fo=1, routed) 0.000 9.465 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[9] SLICE_X127Y131 FDRE r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9]/D ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 12.500 12.500 r V4 0.000 12.500 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 12.500 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.916 13.416 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.162 14.578 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.084 14.662 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.960 15.622 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.918 16.540 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.925 17.465 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/clk SLICE_X127Y131 FDRE r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9]/C clock pessimism 0.264 17.729 clock uncertainty -0.053 17.676 SLICE_X127Y131 FDRE (Setup_fdre_C_D) 0.062 17.738 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9] ------------------------------------------------------------------- required time 17.738 arrival time -9.465 ------------------------------------------------------------------- slack 8.273 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.107ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/shifted_data_in_reg[8][20]/C (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2] (rising edge-triggered cell RAMB36E1 clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: dvi2rgb_0_PixelClk_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (dvi2rgb_0_PixelClk_1 rise@0.000ns - dvi2rgb_0_PixelClk_1 rise@0.000ns) Data Path Delay: 0.428ns (logic 0.148ns (34.549%) route 0.280ns (65.451%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.263ns Source Clock Delay (SCD): 1.894ns Clock Pessimism Removal (CPR): 0.291ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.481 0.481 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.440 0.921 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.051 0.972 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.363 1.335 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.270 1.605 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.289 1.894 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/out SLICE_X152Y104 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/shifted_data_in_reg[8][20]/C ------------------------------------------------------------------- ------------------- SLICE_X152Y104 FDRE (Prop_fdre_C_Q) 0.148 2.042 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/shifted_data_in_reg[8][20]/Q net (fo=1, routed) 0.280 2.322 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/CAP_TRIGGER_O_reg[2] RAMB36_X8Y20 RAMB36E1 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2] ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.529 0.529 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.480 1.009 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.054 1.063 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.402 1.465 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.431 1.896 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.367 2.263 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/out RAMB36_X8Y20 RAMB36E1 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK clock pessimism -0.291 1.973 RAMB36_X8Y20 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[2]) 0.243 2.216 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ------------------------------------------------------------------- required time -2.216 arrival time 2.322 ------------------------------------------------------------------- slack 0.107 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: dvi2rgb_0_PixelClk_1 Waveform(ns): { 0.000 5.000 } Period(ns): 12.500 Sources: { hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 12.500 9.924 RAMB36_X8Y21 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 7.500 6.250 SLICE_X146Y134 hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X154Y134 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/ChannelBondX/pFIFO_reg_0_31_0_5/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: hdmi_i/dvi2rgb_0/U0/RefClk To Clock: dvi2rgb_0_PixelClk Setup : 1 Failing Endpoint , Worst Slack -1.773ns, Total Violation -1.773ns Hold : 0 Failing Endpoints, Worst Slack 0.126ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -1.773ns (required time - arrival time) Source: hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C (rising edge-triggered cell FDCE clocked by hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: dvi2rgb_0_PixelClk Path Type: Setup (Max at Slow Process Corner) Requirement: 0.020ns (dvi2rgb_0_PixelClk rise@1315.020ns - hdmi_i/dvi2rgb_0/U0/RefClk rise@1315.000ns) Data Path Delay: 4.527ns (logic 0.580ns (12.811%) route 3.947ns (87.189%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 2.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.865ns = ( 1319.885 - 1315.020 ) Source Clock Delay (SCD): 2.007ns = ( 1317.007 - 1315.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.155ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.101ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 1315.000 1315.000 r BUFGCTRL_X0Y17 BUFG 0.000 1315.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 2.007 1317.007 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/RefClk SLICE_X160Y94 FDCE r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C ------------------------------------------------------------------- ------------------- SLICE_X160Y94 FDCE (Prop_fdce_C_Q) 0.456 1317.464 f hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/Q net (fo=4, routed) 3.947 1321.411 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/dcm_locked SLICE_X149Y143 LUT4 (Prop_lut4_I2_O) 0.124 1321.535 r hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int0/O net (fo=1, routed) 0.000 1321.535 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int0__0 SLICE_X149Y143 FDRE r hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 1315.020 1315.020 r V4 0.000 1315.020 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 1315.020 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.916 1315.936 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.162 1317.098 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.084 1317.182 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.960 1318.142 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.918 1319.060 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.825 1319.885 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/slowest_sync_clk SLICE_X149Y143 FDRE r hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/C clock pessimism 0.000 1319.885 clock uncertainty -0.155 1319.730 SLICE_X149Y143 FDRE (Setup_fdre_C_D) 0.031 1319.761 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg ------------------------------------------------------------------- required time 1319.761 arrival time -1321.535 ------------------------------------------------------------------- slack -1.773 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.126ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C (rising edge-triggered cell FDCE clocked by hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: dvi2rgb_0_PixelClk Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (dvi2rgb_0_PixelClk rise@0.000ns - hdmi_i/dvi2rgb_0/U0/RefClk rise@0.000ns) Data Path Delay: 3.827ns (logic 0.467ns (12.202%) route 3.360ns (87.798%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 3.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.157ns Source Clock Delay (SCD): 1.881ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.155ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.101ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.881 1.881 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/RefClk SLICE_X160Y94 FDCE r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C ------------------------------------------------------------------- ------------------- SLICE_X160Y94 FDCE (Prop_fdce_C_Q) 0.367 2.248 f hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/Q net (fo=4, routed) 3.360 5.608 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/dcm_locked SLICE_X149Y143 LUT4 (Prop_lut4_I2_O) 0.100 5.708 r hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int0/O net (fo=1, routed) 0.000 5.708 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int0__0 SLICE_X149Y143 FDRE r hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.960 0.960 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.233 2.193 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.089 2.282 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 1.025 3.307 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.982 4.289 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.868 5.157 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/slowest_sync_clk SLICE_X149Y143 FDRE r hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/C clock pessimism 0.000 5.157 clock uncertainty 0.155 5.312 SLICE_X149Y143 FDRE (Hold_fdre_C_D) 0.270 5.582 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg ------------------------------------------------------------------- required time -5.582 arrival time 5.708 ------------------------------------------------------------------- slack 0.126 --------------------------------------------------------------------------------------------------- From Clock: clk_pll_i To Clock: dvi2rgb_0_PixelClk Setup : 0 Failing Endpoints, Worst Slack 8.436ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 8.436ns (required time - arrival time) Source: hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.proc_sync1_reg[38]/C (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2VIDCLK_I/data_sync_reg[0][38]/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: dvi2rgb_0_PixelClk Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) Data Path Delay: 1.471ns (logic 0.456ns (30.998%) route 1.015ns (69.002%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X131Y135 0.000 0.000 r hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.proc_sync1_reg[38]/C SLICE_X131Y135 FDRE (Prop_fdre_C_Q) 0.456 0.456 r hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.proc_sync1_reg[38]/Q net (fo=1, routed) 1.015 1.471 hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2VIDCLK_I/AXI4_LITE_INTERFACE.proc_sync1_reg[44][38] SLICE_X110Y135 FDRE r hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2VIDCLK_I/data_sync_reg[0][38]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 SLICE_X110Y135 FDRE (Setup_fdre_C_D) -0.093 9.907 hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2VIDCLK_I/data_sync_reg[0][38] ------------------------------------------------------------------- required time 9.907 arrival time -1.471 ------------------------------------------------------------------- slack 8.436 --------------------------------------------------------------------------------------------------- From Clock: mmcm_clkout0 To Clock: dvi2rgb_0_PixelClk Setup : 0 Failing Endpoints, Worst Slack 5.048ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.048ns (required time - arrival time) Source: hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Destination: hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: dvi2rgb_0_PixelClk Path Type: Setup (Max at Slow Process Corner) Requirement: 6.250ns (MaxDelay Path 6.250ns) Data Path Delay: 1.186ns (logic 0.456ns (38.450%) route 0.730ns (61.550%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.250ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X147Y133 0.000 0.000 r hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C SLICE_X147Y133 FDRE (Prop_fdre_C_Q) 0.456 0.456 r hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q net (fo=1, routed) 0.730 1.186 hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3] SLICE_X146Y139 FDRE r hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 6.250 6.250 SLICE_X146Y139 FDRE (Setup_fdre_C_D) -0.016 6.234 hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- required time 6.234 arrival time -1.186 ------------------------------------------------------------------- slack 5.048 --------------------------------------------------------------------------------------------------- From Clock: mmcm_clkout1 To Clock: dvi2rgb_0_PixelClk Setup : 21 Failing Endpoints, Worst Slack -4.676ns, Total Violation -91.180ns Hold : 4 Failing Endpoints, Worst Slack -0.373ns, Total Violation -0.835ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -4.676ns (required time - arrival time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_srlB/S2/CLK (rising edge-triggered cell SRL16E clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: dvi2rgb_0_PixelClk Path Type: Setup (Max at Slow Process Corner) Requirement: 0.020ns (dvi2rgb_0_PixelClk rise@1315.020ns - mmcm_clkout1 rise@1315.000ns) Data Path Delay: 3.850ns (logic 2.546ns (66.133%) route 1.304ns (33.867%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: -0.660ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.803ns = ( 1319.823 - 1315.020 ) Source Clock Delay (SCD): 5.464ns = ( 1320.464 - 1315.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.205ns Phase Error (PE): 0.153ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 1315.000 1315.000 r R4 0.000 1315.000 r sys_clk_i (IN) net (fo=0) 0.000 1315.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1316.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 1317.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 1317.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 1319.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 1319.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 1320.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -3.633 1316.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 1.808 1318.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 1318.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.833 1320.463 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_srlB/CLK SLICE_X158Y101 SRL16E r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_srlB/S2/CLK ------------------------------------------------------------------- ------------------- SLICE_X158Y101 SRL16E (Prop_srl16e_CLK_Q) 1.632 1322.095 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_srlB/S2/Q net (fo=1, routed) 0.573 1322.668 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/mux_di[1] SLICE_X158Y100 CARRY4 (Prop_carry4_DI[1]_CO[3]) 0.795 1323.463 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_carry4_inst/CO[3] net (fo=1, routed) 0.731 1324.194 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/shift_en_reg SLICE_X160Y100 LUT2 (Prop_lut2_I1_O) 0.119 1324.313 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/u_wcnt_lcmp_q_i_1/O net (fo=1, routed) 0.000 1324.313 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp SLICE_X160Y100 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q/D ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 1315.020 1315.020 r V4 0.000 1315.020 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 1315.020 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.916 1315.936 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.162 1317.098 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.084 1317.182 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.960 1318.142 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.918 1319.060 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.763 1319.823 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/out SLICE_X160Y100 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q/C clock pessimism 0.000 1319.823 clock uncertainty -0.261 1319.562 SLICE_X160Y100 FDRE (Setup_fdre_C_D) 0.075 1319.637 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q ------------------------------------------------------------------- required time 1319.637 arrival time -1324.313 ------------------------------------------------------------------- slack -4.676 Min Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -0.373ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/S2/CLK (rising edge-triggered cell SRL16E clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: dvi2rgb_0_PixelClk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (dvi2rgb_0_PixelClk rise@0.000ns - mmcm_clkout1 rise@0.000ns) Data Path Delay: 0.612ns (logic 0.612ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 2 (CARRY4=2) Clock Path Skew: 0.669ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.222ns Source Clock Delay (SCD): 1.553ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.205ns Phase Error (PE): 0.153ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 0.622 1.553 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/CLK SLICE_X150Y103 SRL16E r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/S2/CLK ------------------------------------------------------------------- ------------------- SLICE_X150Y103 SRL16E (Prop_srl16e_CLK_Q) 0.488 2.041 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/S2/Q net (fo=1, routed) 0.000 2.041 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/mux_di[2] SLICE_X150Y103 CARRY4 (Prop_carry4_DI[2]_CO[3]) 0.084 2.125 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_carry4_inst/CO[3] net (fo=1, routed) 0.000 2.125 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/DOUT_O SLICE_X150Y104 CARRY4 (Prop_carry4_CI_CO[3]) 0.040 2.165 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_carry4_inst/CO[3] net (fo=1, routed) 0.000 2.165 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/muxcy_lo[3] SLICE_X150Y104 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.529 0.529 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.480 1.009 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.054 1.063 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.402 1.465 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.431 1.896 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.326 2.222 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/rMMCM_LckdRisingFlag_reg SLICE_X150Y104 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/C clock pessimism 0.000 2.222 clock uncertainty 0.261 2.483 SLICE_X150Y104 FDRE (Hold_fdre_C_D) 0.055 2.538 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ------------------------------------------------------------------- required time -2.538 arrival time 2.165 ------------------------------------------------------------------- slack -0.373 --------------------------------------------------------------------------------------------------- From Clock: dvi2rgb_0_PixelClk_1 To Clock: dvi2rgb_0_PixelClk Setup : 6290 Failing Endpoints, Worst Slack -4.207ns, Total Violation -14935.253ns Hold : 0 Failing Endpoints, Worst Slack 0.054ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -4.207ns (required time - arrival time) Source: hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int_reg[5]/C (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Destination: hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9]/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: dvi2rgb_0_PixelClk Path Type: Setup (Max at Slow Process Corner) Requirement: 0.020ns (dvi2rgb_0_PixelClk rise@3587.520ns - dvi2rgb_0_PixelClk_1 rise@3587.500ns) Data Path Delay: 4.220ns (logic 2.772ns (65.680%) route 1.448ns (34.320%)) Logic Levels: 7 (CARRY4=5 LUT2=1 LUT3=1) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.965ns = ( 3592.485 - 3587.520 ) Source Clock Delay (SCD): 5.244ns = ( 3592.744 - 3587.500 ) Clock Pessimism Removal (CPR): 0.264ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 3587.500 3587.500 r V4 0.000 3587.500 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 3587.500 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.960 3588.460 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.233 3589.693 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.089 3589.782 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 1.025 3590.807 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.982 3591.789 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.955 3592.744 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/clk SLICE_X127Y125 FDRE r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y125 FDRE (Prop_fdre_C_Q) 0.456 3593.200 f hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int_reg[5]/Q net (fo=16, routed) 0.798 3593.998 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int[5] SLICE_X127Y126 LUT2 (Prop_lut2_I0_O) 0.124 3594.122 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[0]_i_13/O net (fo=1, routed) 0.000 3594.122 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[0]_i_13_n_0 SLICE_X127Y126 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3594.672 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_3/CO[3] net (fo=1, routed) 0.000 3594.672 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_3_n_0 SLICE_X127Y127 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 3594.943 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_2/CO[0] net (fo=24, routed) 0.650 3595.594 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_2_n_3 SLICE_X127Y129 LUT3 (Prop_lut3_I1_O) 0.373 3595.967 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[3]_i_8/O net (fo=1, routed) 0.000 3595.967 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[3]_i_8_n_0 SLICE_X127Y129 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 3596.517 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 3596.517 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[3]_i_1_n_0 SLICE_X127Y130 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 3596.631 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[7]_i_1/CO[3] net (fo=1, routed) 0.000 3596.631 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[7]_i_1_n_0 SLICE_X127Y131 CARRY4 (Prop_carry4_CI_O[1]) 0.334 3596.965 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[11]_i_1/O[1] net (fo=1, routed) 0.000 3596.965 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[9] SLICE_X127Y131 FDRE r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9]/D ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 3587.520 3587.520 r V4 0.000 3587.520 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 3587.520 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.916 3588.436 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.162 3589.598 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.084 3589.682 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.960 3590.642 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.918 3591.560 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.925 3592.485 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/clk SLICE_X127Y131 FDRE r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9]/C clock pessimism 0.264 3592.749 clock uncertainty -0.053 3592.695 SLICE_X127Y131 FDRE (Setup_fdre_C_D) 0.062 3592.757 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9] ------------------------------------------------------------------- required time 3592.757 arrival time -3596.965 ------------------------------------------------------------------- slack -4.207 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.054ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/shifted_data_in_reg[8][20]/C (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2] (rising edge-triggered cell RAMB36E1 clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: dvi2rgb_0_PixelClk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (dvi2rgb_0_PixelClk rise@0.000ns - dvi2rgb_0_PixelClk_1 rise@0.000ns) Data Path Delay: 0.428ns (logic 0.148ns (34.549%) route 0.280ns (65.451%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.263ns Source Clock Delay (SCD): 1.894ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.481 0.481 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.440 0.921 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.051 0.972 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.363 1.335 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.270 1.605 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.289 1.894 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/out SLICE_X152Y104 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/shifted_data_in_reg[8][20]/C ------------------------------------------------------------------- ------------------- SLICE_X152Y104 FDRE (Prop_fdre_C_Q) 0.148 2.042 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/shifted_data_in_reg[8][20]/Q net (fo=1, routed) 0.280 2.322 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/CAP_TRIGGER_O_reg[2] RAMB36_X8Y20 RAMB36E1 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2] ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.529 0.529 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.480 1.009 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.054 1.063 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.402 1.465 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.431 1.896 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.367 2.263 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/out RAMB36_X8Y20 RAMB36E1 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK clock pessimism -0.291 1.973 clock uncertainty 0.053 2.026 RAMB36_X8Y20 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[2]) 0.243 2.269 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ------------------------------------------------------------------- required time -2.269 arrival time 2.322 ------------------------------------------------------------------- slack 0.054 --------------------------------------------------------------------------------------------------- From Clock: mmcm_clkout1 To Clock: hdmi_i/dvi2rgb_0/U0/RefClk Setup : 17 Failing Endpoints, Worst Slack -2.757ns, Total Violation -24.135ns Hold : 0 Failing Endpoints, Worst Slack 1.263ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -2.757ns (required time - arrival time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_srlA/S2/CLK (rising edge-triggered cell SRL16E clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q/D (rising edge-triggered cell FDRE clocked by hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: hdmi_i/dvi2rgb_0/U0/RefClk Path Type: Setup (Max at Slow Process Corner) Requirement: 5.000ns (hdmi_i/dvi2rgb_0/U0/RefClk rise@5.000ns - mmcm_clkout1 rise@0.000ns) Data Path Delay: 3.991ns (logic 2.488ns (62.335%) route 1.503ns (37.665%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: -3.655ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.732ns = ( 6.732 - 5.000 ) Source Clock Delay (SCD): 5.491ns Clock Pessimism Removal (CPR): 0.103ns Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.125ns Phase Error (PE): 0.114ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.860 5.491 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_srlA/CLK SLICE_X124Y63 SRL16E r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_srlA/S2/CLK ------------------------------------------------------------------- ------------------- SLICE_X124Y63 SRL16E (Prop_srl16e_CLK_Q) 1.617 7.108 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_srlA/S2/Q net (fo=1, routed) 0.524 7.631 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/mux_di[0] SLICE_X124Y62 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.754 8.385 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_carry4_inst/CO[3] net (fo=1, routed) 0.980 9.365 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/shift_en_reg SLICE_X127Y63 LUT2 (Prop_lut2_I1_O) 0.117 9.482 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/u_wcnt_hcmp_q_i_1/O net (fo=1, routed) 0.000 9.482 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp SLICE_X127Y63 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q/D ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 5.000 5.000 r BUFGCTRL_X0Y17 BUFG 0.000 5.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.732 6.732 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/RefClk SLICE_X127Y63 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q/C clock pessimism 0.103 6.835 clock uncertainty -0.186 6.650 SLICE_X127Y63 FDRE (Setup_fdre_C_D) 0.075 6.725 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_hcmp_q ------------------------------------------------------------------- required time 6.725 arrival time -9.482 ------------------------------------------------------------------- slack -2.757 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.263ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[0].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/S2/CLK (rising edge-triggered cell SRL16E clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[0].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D (rising edge-triggered cell FDRE clocked by hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: hdmi_i/dvi2rgb_0/U0/RefClk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (hdmi_i/dvi2rgb_0/U0/RefClk rise@0.000ns - mmcm_clkout1 rise@0.000ns) Data Path Delay: 0.572ns (logic 0.572ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: -0.932ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.924ns Source Clock Delay (SCD): 1.583ns Clock Pessimism Removal (CPR): 0.272ns Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.125ns Phase Error (PE): 0.114ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 0.651 1.583 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[0].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/CLK SLICE_X120Y71 SRL16E r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[0].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/S2/CLK ------------------------------------------------------------------- ------------------- SLICE_X120Y71 SRL16E (Prop_srl16e_CLK_Q) 0.488 2.071 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[0].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/S2/Q net (fo=1, routed) 0.000 2.071 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[0].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/mux_di[2] SLICE_X120Y71 CARRY4 (Prop_carry4_DI[2]_CO[3]) 0.084 2.155 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[0].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_carry4_inst/CO[3] net (fo=1, routed) 0.000 2.155 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[0].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/muxcy_lo[3] SLICE_X120Y71 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[0].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 0.924 0.924 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[0].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/RefClk SLICE_X120Y71 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[0].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/C clock pessimism -0.272 0.651 clock uncertainty 0.186 0.837 SLICE_X120Y71 FDRE (Hold_fdre_C_D) 0.055 0.892 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_RefClkx/U0/ila_core_inst/u_trig/U_TM/N_DDR_MODE.G_NMU[0].U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ------------------------------------------------------------------- required time -0.892 arrival time 2.155 ------------------------------------------------------------------- slack 1.263 --------------------------------------------------------------------------------------------------- From Clock: clk_pll_i To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Setup : 0 Failing Endpoints, Worst Slack 6.998ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 38.139ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 6.998ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.750ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall@13.750ns - clk_pll_i rise@0.000ns) Data Path Delay: 6.358ns (logic 3.867ns (60.818%) route 2.491ns (39.182%)) Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) Clock Path Skew: -0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.207ns = ( 6.457 - 1.250 ) Source Clock Delay (SCD): 5.366ns Clock Pessimism Removal (CPR): 0.152ns Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.096ns Phase Error (PE): 0.162ns Timing Exception: MultiCycle Path Setup -end 6 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.736 5.366 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/CLK SLICE_X141Y187 FDRE r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y187 FDRE (Prop_fdre_C_Q) 0.456 5.822 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q net (fo=36, routed) 2.491 8.314 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[1].u_iobuf_dq/IBUFDISABLE H4 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) 2.596 10.910 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[1].u_iobuf_dq/IBUF/O net (fo=2, routed) 0.000 10.910 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[0] IDELAY_X1Y176 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) 0.815 11.725 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2/DATAOUT net (fo=1, routed) 0.000 11.725 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_1 ILOGIC_X1Y176 ISERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY ------------------------------------------------------------------- ------------------- (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall edge) 13.750 13.750 f R4 0.000 13.750 f sys_clk_i (IN) net (fo=0) 0.000 13.750 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 15.155 f hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 16.435 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.083 16.518 f hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 net (fo=7, routed) 0.576 17.094 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk PHASER_IN_PHY_X1Y14 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) 1.455 18.548 f hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK net (fo=16, routed) 0.409 18.957 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CLKB0 ILOGIC_X1Y176 ISERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) clock pessimism 0.152 19.109 clock uncertainty -0.221 18.888 ILOGIC_X1Y176 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) -0.165 18.723 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq ------------------------------------------------------------------- required time 18.723 arrival time -11.725 ------------------------------------------------------------------- slack 6.998 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 38.139ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[9].iserdes_dq_.iserdesdq/DDLY (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk Path Type: Hold (Min at Fast Process Corner) Requirement: -37.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise@12.500ns - clk_pll_i rise@50.000ns) Data Path Delay: 1.762ns (logic 1.068ns (60.625%) route 0.694ns (39.375%)) Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) Clock Path Skew: 0.845ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.624ns Source Clock Delay (SCD): 1.542ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.096ns Phase Error (PE): 0.162ns Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 50.000 50.000 r R4 0.000 50.000 r sys_clk_i (IN) net (fo=0) 0.000 50.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 50.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 50.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 50.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 51.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 51.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 51.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.156 50.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.531 50.905 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 50.931 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.611 51.542 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/CLK SLICE_X141Y187 FDRE r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y187 FDRE (Prop_fdre_C_Q) 0.141 51.683 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q net (fo=36, routed) 0.694 52.377 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[4].u_iobuf_dq/IBUFDISABLE K1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) 0.684 53.061 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[4].u_iobuf_dq/IBUF/O net (fo=2, routed) 0.000 53.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[7] IDELAY_X1Y186 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) 0.243 53.304 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[9].iserdes_dq_.idelay_dq.idelaye2/DATAOUT net (fo=1, routed) 0.000 53.304 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_9 ILOGIC_X1Y186 ISERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[9].iserdes_dq_.iserdesdq/DDLY ------------------------------------------------------------------- ------------------- (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise edge) 12.500 12.500 r R4 0.000 12.500 r sys_clk_i (IN) net (fo=0) 0.000 12.500 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 12.931 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 13.455 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.053 13.508 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 net (fo=7, routed) 0.217 13.725 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk PHASER_IN_PHY_X1Y14 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) 1.219 14.944 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK net (fo=16, routed) 0.180 15.124 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/A_rst_primitives_reg_0 ILOGIC_X1Y186 ISERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[9].iserdes_dq_.iserdesdq/CLK clock pessimism -0.237 14.887 clock uncertainty 0.221 15.108 ILOGIC_X1Y186 ISERDESE2 (Hold_iserdese2_CLK_DDLY) 0.056 15.164 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[9].iserdes_dq_.iserdesdq ------------------------------------------------------------------- required time -15.164 arrival time 53.304 ------------------------------------------------------------------- slack 38.139 --------------------------------------------------------------------------------------------------- From Clock: clk_pll_i To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Setup : 0 Failing Endpoints, Worst Slack 6.546ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 38.061ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 6.546ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[9].iserdes_dq_.iserdesdq/DDLY (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 13.750ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall@13.750ns - clk_pll_i rise@0.000ns) Data Path Delay: 6.821ns (logic 3.867ns (56.693%) route 2.954ns (43.308%)) Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) Clock Path Skew: 0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.217ns = ( 6.467 - 1.250 ) Source Clock Delay (SCD): 5.366ns Clock Pessimism Removal (CPR): 0.152ns Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.096ns Phase Error (PE): 0.162ns Timing Exception: MultiCycle Path Setup -end 6 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.736 5.366 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/CLK SLICE_X141Y187 FDRE r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y187 FDRE (Prop_fdre_C_Q) 0.456 5.822 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q net (fo=36, routed) 2.954 8.776 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[15].u_iobuf_dq/IBUFDISABLE B1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) 2.596 11.372 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[15].u_iobuf_dq/IBUF/O net (fo=2, routed) 0.000 11.372 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[7] IDELAY_X1Y198 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) 0.815 12.187 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[9].iserdes_dq_.idelay_dq.idelaye2/DATAOUT net (fo=1, routed) 0.000 12.187 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_9 ILOGIC_X1Y198 ISERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[9].iserdes_dq_.iserdesdq/DDLY ------------------------------------------------------------------- ------------------- (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall edge) 13.750 13.750 f R4 0.000 13.750 f sys_clk_i (IN) net (fo=0) 0.000 13.750 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 15.155 f hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 16.435 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.083 16.518 f hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 net (fo=7, routed) 0.566 17.084 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk PHASER_IN_PHY_X1Y15 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) 1.455 18.538 f hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK net (fo=16, routed) 0.429 18.967 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CLKB0_1 ILOGIC_X1Y198 ISERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[9].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) clock pessimism 0.152 19.119 clock uncertainty -0.221 18.898 ILOGIC_X1Y198 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) -0.165 18.733 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[9].iserdes_dq_.iserdesdq ------------------------------------------------------------------- required time 18.733 arrival time -12.187 ------------------------------------------------------------------- slack 6.546 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 38.061ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[0].iserdes_dq_.iserdesdq/DDLY (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk Path Type: Hold (Min at Fast Process Corner) Requirement: -37.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise@12.500ns - clk_pll_i rise@50.000ns) Data Path Delay: 1.679ns (logic 1.068ns (63.612%) route 0.611ns (36.388%)) Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) Clock Path Skew: 0.841ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.620ns Source Clock Delay (SCD): 1.542ns Clock Pessimism Removal (CPR): 0.237ns Clock Uncertainty: 0.221ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.096ns Phase Error (PE): 0.162ns Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 50.000 50.000 r R4 0.000 50.000 r sys_clk_i (IN) net (fo=0) 0.000 50.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 50.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 50.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 50.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 51.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 51.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 51.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.156 50.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.531 50.905 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 50.931 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.611 51.542 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/CLK SLICE_X141Y187 FDRE r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C ------------------------------------------------------------------- ------------------- SLICE_X141Y187 FDRE (Prop_fdre_C_Q) 0.141 51.683 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q net (fo=36, routed) 0.611 52.294 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[8].u_iobuf_dq/IBUFDISABLE E3 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) 0.684 52.978 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[8].u_iobuf_dq/IBUF/O net (fo=2, routed) 0.000 52.978 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[0] IDELAY_X1Y187 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) 0.243 53.221 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[0].iserdes_dq_.idelay_dq.idelaye2/DATAOUT net (fo=1, routed) 0.000 53.221 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_0 ILOGIC_X1Y187 ISERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[0].iserdes_dq_.iserdesdq/DDLY ------------------------------------------------------------------- ------------------- (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise edge) 12.500 12.500 r R4 0.000 12.500 r sys_clk_i (IN) net (fo=0) 0.000 12.500 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 12.931 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 13.455 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) 0.053 13.508 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 net (fo=7, routed) 0.211 13.719 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk PHASER_IN_PHY_X1Y15 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) 1.219 14.938 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK net (fo=16, routed) 0.182 15.120 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/A_rst_primitives_reg_0 ILOGIC_X1Y187 ISERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[0].iserdes_dq_.iserdesdq/CLK clock pessimism -0.237 14.883 clock uncertainty 0.221 15.104 ILOGIC_X1Y187 ISERDESE2 (Hold_iserdese2_CLK_DDLY) 0.056 15.160 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[0].iserdes_dq_.iserdesdq ------------------------------------------------------------------- required time -15.160 arrival time 53.221 ------------------------------------------------------------------- slack 38.061 --------------------------------------------------------------------------------------------------- From Clock: sync_pulse To Clock: mem_refclk Setup : 0 Failing Endpoints, Worst Slack 0.973ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.668ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.973ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 (clock source 'sync_pulse' {rise@1.094ns fall@3.594ns period=40.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: mem_refclk Path Type: Setup (Max at Slow Process Corner) Requirement: 1.406ns (mem_refclk rise@5.000ns - sync_pulse fall@3.594ns) Data Path Delay: 0.621ns (logic 0.000ns (0.000%) route 0.621ns (100.000%)) Logic Levels: 0 Clock Path Skew: 0.589ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.357ns = ( 8.357 - 5.000 ) Source Clock Delay (SCD): 2.919ns = ( 6.513 - 3.594 ) Clock Pessimism Removal (CPR): 0.152ns Clock Uncertainty: 0.219ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.186ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sync_pulse fall edge) 3.594 3.594 f R4 0.000 3.594 f sys_clk_i (IN) net (fo=0) 0.000 3.594 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 5.069 f hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 6.425 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) 0.088 6.513 f hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 net (fo=7, routed) 0.621 7.134 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse PHY_CONTROL_X1Y3 PHY_CONTROL f hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN ------------------------------------------------------------------- ------------------- (clock mem_refclk rise edge) 5.000 5.000 r R4 0.000 5.000 r sys_clk_i (IN) net (fo=0) 0.000 5.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 6.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 7.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 7.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.589 8.357 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk PHY_CONTROL_X1Y3 PHY_CONTROL r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK clock pessimism 0.152 8.508 clock uncertainty -0.219 8.289 PHY_CONTROL_X1Y3 PHY_CONTROL (Setup_phy_control_MEMREFCLK_SYNCIN) -0.182 8.107 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i ------------------------------------------------------------------- required time 8.107 arrival time -7.134 ------------------------------------------------------------------- slack 0.973 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.668ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 (clock source 'sync_pulse' {rise@1.094ns fall@3.594ns period=40.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: mem_refclk Path Type: Hold (Min at Slow Process Corner) Requirement: -1.094ns (mem_refclk rise@0.000ns - sync_pulse rise@1.094ns) Data Path Delay: 0.589ns (logic 0.000ns (0.000%) route 0.589ns (100.000%)) Logic Levels: 0 Clock Path Skew: 0.621ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.540ns Source Clock Delay (SCD): 2.768ns = ( 3.861 - 1.094 ) Clock Pessimism Removal (CPR): 0.152ns Clock Uncertainty: 0.219ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.186ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sync_pulse rise edge) 1.094 1.094 r R4 0.000 1.094 r sys_clk_i (IN) net (fo=0) 0.000 1.094 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 2.498 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 3.778 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk ------------------------------------------------------------------- ------------------- PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) 0.083 3.861 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 net (fo=7, routed) 0.589 4.450 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse PHY_CONTROL_X1Y3 PHY_CONTROL r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN ------------------------------------------------------------------- ------------------- (clock mem_refclk rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.621 3.540 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk PHY_CONTROL_X1Y3 PHY_CONTROL r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK clock pessimism -0.152 3.389 clock uncertainty 0.219 3.608 PHY_CONTROL_X1Y3 PHY_CONTROL (Hold_phy_control_MEMREFCLK_SYNCIN) 0.174 3.782 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i ------------------------------------------------------------------- required time -3.782 arrival time 4.450 ------------------------------------------------------------------- slack 0.668 --------------------------------------------------------------------------------------------------- From Clock: oserdes_clk To Clock: oserdes_clkdiv Setup : 0 Failing Endpoints, Worst Slack 1.594ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.594ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: oserdes_clkdiv Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (oserdes_clkdiv rise@10.000ns - oserdes_clk rise@7.500ns) Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.574ns = ( 15.574 - 10.000 ) Source Clock Delay (SCD): 5.669ns = ( 13.169 - 7.500 ) Clock Pessimism Removal (CPR): 0.243ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.109ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clk rise edge) 7.500 7.500 r R4 0.000 7.500 r sys_clk_i (IN) net (fo=0) 0.000 7.500 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 8.975 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 10.331 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 10.419 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.614 11.033 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.136 13.169 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK ------------------------------------------------------------------- ------------------- PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) 0.338 13.507 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE net (fo=1, routed) 0.000 13.507 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable OUT_FIFO_X1Y12 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 12.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 12.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.582 13.350 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.077 15.426 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.148 15.574 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV net (fo=12, routed) 0.000 15.574 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv OUT_FIFO_X1Y12 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK clock pessimism 0.243 15.817 clock uncertainty -0.065 15.752 OUT_FIFO_X1Y12 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) -0.651 15.101 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo ------------------------------------------------------------------- required time 15.101 arrival time -13.507 ------------------------------------------------------------------- slack 1.594 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.095ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: oserdes_clkdiv Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clk rise@0.000ns) Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.172ns Source Clock Delay (SCD): 2.782ns Clock Pessimism Removal (CPR): 0.302ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clk rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.197 0.968 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.813 2.782 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK ------------------------------------------------------------------- ------------------- PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) 0.172 2.954 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE net (fo=1, routed) 0.000 2.954 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable OUT_FIFO_X1Y12 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.218 1.226 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.858 3.084 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK PHASER_OUT_PHY_X1Y12 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.088 3.172 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV net (fo=12, routed) 0.000 3.172 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv OUT_FIFO_X1Y12 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK clock pessimism -0.302 2.870 OUT_FIFO_X1Y12 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) -0.011 2.859 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo ------------------------------------------------------------------- required time -2.859 arrival time 2.954 ------------------------------------------------------------------- slack 0.095 --------------------------------------------------------------------------------------------------- From Clock: oserdes_clk_1 To Clock: oserdes_clkdiv_1 Setup : 0 Failing Endpoints, Worst Slack 1.594ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.594ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: oserdes_clkdiv_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (oserdes_clkdiv_1 rise@10.000ns - oserdes_clk_1 rise@7.500ns) Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.564ns = ( 15.564 - 10.000 ) Source Clock Delay (SCD): 5.658ns = ( 13.158 - 7.500 ) Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.109ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clk_1 rise edge) 7.500 7.500 r R4 0.000 7.500 r sys_clk_i (IN) net (fo=0) 0.000 7.500 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 8.975 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 10.331 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 10.419 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.603 11.022 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.136 13.158 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK ------------------------------------------------------------------- ------------------- PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) 0.338 13.496 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE net (fo=1, routed) 0.000 13.496 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable OUT_FIFO_X1Y13 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_1 rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 12.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 12.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.572 13.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.077 15.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.148 15.564 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV net (fo=13, routed) 0.000 15.564 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv OUT_FIFO_X1Y13 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK clock pessimism 0.242 15.806 clock uncertainty -0.065 15.741 OUT_FIFO_X1Y13 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) -0.651 15.090 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo ------------------------------------------------------------------- required time 15.090 arrival time -13.496 ------------------------------------------------------------------- slack 1.594 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.095ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: oserdes_clkdiv_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clk_1 rise@0.000ns) Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.163ns Source Clock Delay (SCD): 2.775ns Clock Pessimism Removal (CPR): 0.300ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clk_1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.190 0.961 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.813 2.775 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK ------------------------------------------------------------------- ------------------- PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) 0.172 2.947 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE net (fo=1, routed) 0.000 2.947 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable OUT_FIFO_X1Y13 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.209 1.217 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.858 3.075 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK PHASER_OUT_PHY_X1Y13 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.088 3.163 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV net (fo=13, routed) 0.000 3.163 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv OUT_FIFO_X1Y13 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK clock pessimism -0.300 2.863 OUT_FIFO_X1Y13 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) -0.011 2.852 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo ------------------------------------------------------------------- required time -2.852 arrival time 2.947 ------------------------------------------------------------------- slack 0.095 --------------------------------------------------------------------------------------------------- From Clock: oserdes_clk_2 To Clock: oserdes_clkdiv_2 Setup : 0 Failing Endpoints, Worst Slack 1.278ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.076ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.278ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[9].oserdes_dq_.ddr.oserdes_dq_i/RST (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: oserdes_clkdiv_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 5.000ns (oserdes_clkdiv_2 rise@5.000ns - oserdes_clk_2 rise@0.000ns) Data Path Delay: 3.362ns (logic 0.517ns (15.379%) route 2.845ns (84.621%)) Logic Levels: 0 Clock Path Skew: 0.554ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.980ns = ( 10.980 - 5.000 ) Source Clock Delay (SCD): 5.669ns = ( 8.169 - 2.500 ) Clock Pessimism Removal (CPR): 0.243ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.109ns Phase Error (PE): 0.000ns Timing Exception: MultiCycle Path Setup -start 2 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clk_2 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.614 3.533 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.136 5.669 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK ------------------------------------------------------------------- ------------------- PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) 0.517 6.186 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OSERDESRST net (fo=10, routed) 2.845 9.031 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/po_oserdes_rst OLOGIC_X1Y186 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[9].oserdes_dq_.ddr.oserdes_dq_i/RST ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_2 rise edge) 5.000 5.000 r R4 0.000 5.000 r sys_clk_i (IN) net (fo=0) 0.000 5.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 6.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 7.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 7.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.582 8.350 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.077 10.426 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.148 10.574 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV net (fo=11, routed) 0.406 10.980 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv OLOGIC_X1Y186 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[9].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV clock pessimism 0.243 11.223 clock uncertainty -0.065 11.158 OLOGIC_X1Y186 OSERDESE2 (Setup_oserdese2_CLKDIV_RST) -0.849 10.309 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[9].oserdes_dq_.ddr.oserdes_dq_i ------------------------------------------------------------------- required time 10.309 arrival time -9.031 ------------------------------------------------------------------- slack 1.278 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.076ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: oserdes_clkdiv_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) Data Path Delay: 0.900ns (logic 0.272ns (30.232%) route 0.628ns (69.768%)) Logic Levels: 0 Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.349ns Source Clock Delay (SCD): 2.782ns Clock Pessimism Removal (CPR): 0.302ns Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clk_2 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.197 0.968 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.813 2.782 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK ------------------------------------------------------------------- ------------------- PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) 0.272 3.054 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OSERDESRST net (fo=10, routed) 0.628 3.681 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/po_oserdes_rst OLOGIC_X1Y177 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_2 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.218 1.226 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.858 3.084 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK PHASER_OUT_PHY_X1Y14 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.088 3.172 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV net (fo=11, routed) 0.177 3.349 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv OLOGIC_X1Y177 OSERDESE2 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV clock pessimism -0.302 3.047 OLOGIC_X1Y177 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) 0.559 3.606 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i ------------------------------------------------------------------- required time -3.606 arrival time 3.681 ------------------------------------------------------------------- slack 0.076 --------------------------------------------------------------------------------------------------- From Clock: oserdes_clk_3 To Clock: oserdes_clkdiv_3 Setup : 0 Failing Endpoints, Worst Slack 1.594ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.594ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: oserdes_clkdiv_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (oserdes_clkdiv_3 rise@5.000ns - oserdes_clk_3 rise@2.500ns) Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.148ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.564ns = ( 10.564 - 5.000 ) Source Clock Delay (SCD): 5.658ns = ( 8.158 - 2.500 ) Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.109ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clk_3 rise edge) 2.500 2.500 r R4 0.000 2.500 r sys_clk_i (IN) net (fo=0) 0.000 2.500 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 3.975 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 5.331 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.088 5.419 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.603 6.022 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.136 8.158 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK ------------------------------------------------------------------- ------------------- PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) 0.338 8.496 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE net (fo=1, routed) 0.000 8.496 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable OUT_FIFO_X1Y15 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_3 rise edge) 5.000 5.000 r R4 0.000 5.000 r sys_clk_i (IN) net (fo=0) 0.000 5.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 6.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 7.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.083 7.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.572 8.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 2.077 10.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.148 10.564 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV net (fo=11, routed) 0.000 10.564 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv OUT_FIFO_X1Y15 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK clock pessimism 0.242 10.806 clock uncertainty -0.065 10.741 OUT_FIFO_X1Y15 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) -0.651 10.090 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo ------------------------------------------------------------------- required time 10.090 arrival time -8.496 ------------------------------------------------------------------- slack 1.594 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.095ns (arrival time - required time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: oserdes_clkdiv_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.088ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 3.163ns Source Clock Delay (SCD): 2.775ns Clock Pessimism Removal (CPR): 0.300ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock oserdes_clk_3 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.190 0.961 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.813 2.775 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK ------------------------------------------------------------------- ------------------- PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) 0.172 2.947 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE net (fo=1, routed) 0.000 2.947 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable OUT_FIFO_X1Y15 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN ------------------------------------------------------------------- ------------------- (clock oserdes_clkdiv_3 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 net (fo=7, routed) 0.209 1.217 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) 1.858 3.075 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK PHASER_OUT_PHY_X1Y15 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) 0.088 3.163 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV net (fo=11, routed) 0.000 3.163 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv OUT_FIFO_X1Y15 OUT_FIFO r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK clock pessimism -0.300 2.863 OUT_FIFO_X1Y15 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) -0.011 2.852 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo ------------------------------------------------------------------- required time -2.852 arrival time 2.947 ------------------------------------------------------------------- slack 0.095 --------------------------------------------------------------------------------------------------- From Clock: dvi2rgb_0_PixelClk To Clock: clk_pll_i Setup : 0 Failing Endpoints, Worst Slack 3.977ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.977ns (required time - arrival time) Source: hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.write_ack_reg/C (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Destination: hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2PROCCLK_I/data_sync_reg[0][33]/D (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_pll_i Path Type: Setup (Max at Slow Process Corner) Requirement: 6.060ns (MaxDelay Path 6.060ns) Data Path Delay: 1.803ns (logic 0.419ns (23.233%) route 1.384ns (76.767%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.060ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X111Y135 0.000 0.000 r hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.write_ack_reg/C SLICE_X111Y135 FDRE (Prop_fdre_C_Q) 0.419 0.419 r hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.write_ack_reg/Q net (fo=2, routed) 1.384 1.803 hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2PROCCLK_I/in_data[33] SLICE_X126Y136 FDRE r hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2PROCCLK_I/data_sync_reg[0][33]/D ------------------------------------------------------------------- ------------------- max delay 6.060 6.060 SLICE_X126Y136 FDRE (Setup_fdre_C_D) -0.280 5.780 hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2PROCCLK_I/data_sync_reg[0][33] ------------------------------------------------------------------- required time 5.780 arrival time -1.803 ------------------------------------------------------------------- slack 3.977 --------------------------------------------------------------------------------------------------- From Clock: axi_dynclk_0_PXL_CLK_O To Clock: clk_pll_i Setup : 0 Failing Endpoints, Worst Slack 8.248ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 8.248ns (required time - arrival time) Source: hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.read_ack_d_reg[4]/C (rising edge-triggered cell FDRE clocked by axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Destination: hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2PROCCLK_I/data_sync_reg[0][32]/D (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_pll_i Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) Data Path Delay: 1.705ns (logic 0.456ns (26.753%) route 1.249ns (73.247%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X99Y132 0.000 0.000 r hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.read_ack_d_reg[4]/C SLICE_X99Y132 FDRE (Prop_fdre_C_Q) 0.456 0.456 r hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.read_ack_d_reg[4]/Q net (fo=1, routed) 1.249 1.705 hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2PROCCLK_I/in_data[32] SLICE_X120Y127 FDRE r hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2PROCCLK_I/data_sync_reg[0][32]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 SLICE_X120Y127 FDRE (Setup_fdre_C_D) -0.047 9.953 hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2PROCCLK_I/data_sync_reg[0][32] ------------------------------------------------------------------- required time 9.953 arrival time -1.705 ------------------------------------------------------------------- slack 8.248 --------------------------------------------------------------------------------------------------- From Clock: mmcm_clkout1 To Clock: clk_pll_i Setup : 0 Failing Endpoints, Worst Slack 18.871ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 18.871ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[5]/C (rising edge-triggered cell FDRE clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_pll_i Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (MaxDelay Path 20.000ns) Data Path Delay: 1.082ns (logic 0.456ns (42.156%) route 0.626ns (57.844%)) Logic Levels: 0 Timing Exception: MaxDelay Path 20.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X27Y218 0.000 0.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[5]/C SLICE_X27Y218 FDRE (Prop_fdre_C_Q) 0.456 0.456 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[5]/Q net (fo=1, routed) 0.626 1.082 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[5] SLICE_X28Y221 FDRE r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[5]/D ------------------------------------------------------------------- ------------------- max delay 20.000 20.000 SLICE_X28Y221 FDRE (Setup_fdre_C_D) -0.047 19.953 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[5] ------------------------------------------------------------------- required time 19.953 arrival time -1.082 ------------------------------------------------------------------- slack 18.871 --------------------------------------------------------------------------------------------------- From Clock: dvi2rgb_0_PixelClk_1 To Clock: clk_pll_i Setup : 0 Failing Endpoints, Worst Slack 3.977ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.977ns (required time - arrival time) Source: hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.write_ack_reg/C (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Destination: hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2PROCCLK_I/data_sync_reg[0][33]/D (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_pll_i Path Type: Setup (Max at Slow Process Corner) Requirement: 6.060ns (MaxDelay Path 6.060ns) Data Path Delay: 1.803ns (logic 0.419ns (23.233%) route 1.384ns (76.767%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.060ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X111Y135 0.000 0.000 r hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.write_ack_reg/C SLICE_X111Y135 FDRE (Prop_fdre_C_Q) 0.419 0.419 r hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.write_ack_reg/Q net (fo=2, routed) 1.384 1.803 hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2PROCCLK_I/in_data[33] SLICE_X126Y136 FDRE r hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2PROCCLK_I/data_sync_reg[0][33]/D ------------------------------------------------------------------- ------------------- max delay 6.060 6.060 SLICE_X126Y136 FDRE (Setup_fdre_C_D) -0.280 5.780 hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2PROCCLK_I/data_sync_reg[0][33] ------------------------------------------------------------------- required time 5.780 arrival time -1.803 ------------------------------------------------------------------- slack 3.977 --------------------------------------------------------------------------------------------------- From Clock: clk_pll_i To Clock: axi_dynclk_0_PXL_CLK_O Setup : 0 Failing Endpoints, Worst Slack 8.839ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 8.839ns (required time - arrival time) Source: hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.proc_sync1_reg[43]/C (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2VIDCLK_I/data_sync_reg[0][43]/D (rising edge-triggered cell FDRE clocked by axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Path Group: axi_dynclk_0_PXL_CLK_O Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) Data Path Delay: 1.058ns (logic 0.456ns (43.096%) route 0.602ns (56.904%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X101Y122 0.000 0.000 r hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.proc_sync1_reg[43]/C SLICE_X101Y122 FDRE (Prop_fdre_C_Q) 0.456 0.456 r hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.proc_sync1_reg[43]/Q net (fo=1, routed) 0.602 1.058 hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2VIDCLK_I/AXI4_LITE_INTERFACE.proc_sync1_reg[44][43] SLICE_X99Y122 FDRE r hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2VIDCLK_I/data_sync_reg[0][43]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 SLICE_X99Y122 FDRE (Setup_fdre_C_D) -0.103 9.897 hdmi_i/v_tc_0/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2VIDCLK_I/data_sync_reg[0][43] ------------------------------------------------------------------- required time 9.897 arrival time -1.058 ------------------------------------------------------------------- slack 8.839 --------------------------------------------------------------------------------------------------- From Clock: dvi2rgb_0_PixelClk To Clock: mmcm_clkout0 Setup : 0 Failing Endpoints, Worst Slack 4.862ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.862ns (required time - arrival time) Source: hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Destination: hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Path Group: mmcm_clkout0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.060ns (MaxDelay Path 6.060ns) Data Path Delay: 1.103ns (logic 0.456ns (41.350%) route 0.647ns (58.650%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.060ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X147Y134 0.000 0.000 r hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C SLICE_X147Y134 FDRE (Prop_fdre_C_Q) 0.456 0.456 r hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q net (fo=1, routed) 0.647 1.103 hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3] SLICE_X149Y131 FDRE r hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 6.060 6.060 SLICE_X149Y131 FDRE (Setup_fdre_C_D) -0.095 5.965 hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- required time 5.965 arrival time -1.103 ------------------------------------------------------------------- slack 4.862 --------------------------------------------------------------------------------------------------- From Clock: dvi2rgb_0_PixelClk_1 To Clock: mmcm_clkout0 Setup : 0 Failing Endpoints, Worst Slack 4.862ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.862ns (required time - arrival time) Source: hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Destination: hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Path Group: mmcm_clkout0 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.060ns (MaxDelay Path 6.060ns) Data Path Delay: 1.103ns (logic 0.456ns (41.350%) route 0.647ns (58.650%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.060ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X147Y134 0.000 0.000 r hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C SLICE_X147Y134 FDRE (Prop_fdre_C_Q) 0.456 0.456 r hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q net (fo=1, routed) 0.647 1.103 hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3] SLICE_X149Y131 FDRE r hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 6.060 6.060 SLICE_X149Y131 FDRE (Setup_fdre_C_D) -0.095 5.965 hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- required time 5.965 arrival time -1.103 ------------------------------------------------------------------- slack 4.862 --------------------------------------------------------------------------------------------------- From Clock: clk_pll_i To Clock: mmcm_clkout1 Setup : 0 Failing Endpoints, Worst Slack 12.088ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 12.088ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D (rising edge-triggered cell FDRE clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: mmcm_clkout1 Path Type: Setup (Max at Slow Process Corner) Requirement: 20.000ns (MaxDelay Path 20.000ns) Data Path Delay: 7.817ns (logic 0.456ns (5.833%) route 7.361ns (94.167%)) Logic Levels: 0 Timing Exception: MaxDelay Path 20.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X151Y213 0.000 0.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C SLICE_X151Y213 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q net (fo=51, routed) 7.361 7.817 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/rstdiv0_sync_r1_reg_rep SLICE_X32Y218 FDRE r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D ------------------------------------------------------------------- ------------------- max delay 20.000 20.000 SLICE_X32Y218 FDRE (Setup_fdre_C_D) -0.095 19.905 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg ------------------------------------------------------------------- required time 19.905 arrival time -7.817 ------------------------------------------------------------------- slack 12.088 --------------------------------------------------------------------------------------------------- From Clock: dvi2rgb_0_PixelClk To Clock: dvi2rgb_0_PixelClk_1 Setup : 6290 Failing Endpoints, Worst Slack -4.207ns, Total Violation -14932.303ns Hold : 0 Failing Endpoints, Worst Slack 0.054ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -4.207ns (required time - arrival time) Source: hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int_reg[5]/C (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Destination: hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9]/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: dvi2rgb_0_PixelClk_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 0.020ns (dvi2rgb_0_PixelClk_1 rise@200.000ns - dvi2rgb_0_PixelClk rise@199.980ns) Data Path Delay: 4.220ns (logic 2.772ns (65.680%) route 1.448ns (34.320%)) Logic Levels: 7 (CARRY4=5 LUT2=1 LUT3=1) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.965ns = ( 204.965 - 200.000 ) Source Clock Delay (SCD): 5.244ns = ( 205.224 - 199.980 ) Clock Pessimism Removal (CPR): 0.264ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 199.980 199.980 r V4 0.000 199.980 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 199.980 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.960 200.940 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.233 202.173 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.089 202.262 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 1.025 203.287 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.982 204.269 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.955 205.224 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/clk SLICE_X127Y125 FDRE r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y125 FDRE (Prop_fdre_C_Q) 0.456 205.680 f hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int_reg[5]/Q net (fo=16, routed) 0.798 206.478 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_hactive_start_int[5] SLICE_X127Y126 LUT2 (Prop_lut2_I0_O) 0.124 206.602 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[0]_i_13/O net (fo=1, routed) 0.000 206.602 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[0]_i_13_n_0 SLICE_X127Y126 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 207.152 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_3/CO[3] net (fo=1, routed) 0.000 207.152 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_3_n_0 SLICE_X127Y127 CARRY4 (Prop_carry4_CI_CO[0]) 0.271 207.423 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_2/CO[0] net (fo=24, routed) 0.650 208.074 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[0]_i_2_n_3 SLICE_X127Y129 LUT3 (Prop_lut3_I1_O) 0.373 208.447 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[3]_i_8/O net (fo=1, routed) 0.000 208.447 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[3]_i_8_n_0 SLICE_X127Y129 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.550 208.997 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[3]_i_1/CO[3] net (fo=1, routed) 0.000 208.997 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[3]_i_1_n_0 SLICE_X127Y130 CARRY4 (Prop_carry4_CI_CO[3]) 0.114 209.111 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[7]_i_1/CO[3] net (fo=1, routed) 0.000 209.111 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[7]_i_1_n_0 SLICE_X127Y131 CARRY4 (Prop_carry4_CI_O[1]) 0.334 209.445 r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[11]_i_1/O[1] net (fo=1, routed) 0.000 209.445 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2[9] SLICE_X127Y131 FDRE r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9]/D ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 200.000 200.000 r V4 0.000 200.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 200.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.916 200.916 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.162 202.078 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.084 202.162 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.960 203.122 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.918 204.040 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.925 204.965 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/clk SLICE_X127Y131 FDRE r hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9]/C clock pessimism 0.264 205.229 clock uncertainty -0.053 205.176 SLICE_X127Y131 FDRE (Setup_fdre_C_D) 0.062 205.238 hdmi_i/v_tc_1/U0/U_TC_TOP/GEN_DETECTION.U_tc_DET/det_v0fp_start_hori_int2_reg[9] ------------------------------------------------------------------- required time 205.238 arrival time -209.445 ------------------------------------------------------------------- slack -4.207 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.054ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/shifted_data_in_reg[8][20]/C (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2] (rising edge-triggered cell RAMB36E1 clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: dvi2rgb_0_PixelClk_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (dvi2rgb_0_PixelClk_1 rise@0.000ns - dvi2rgb_0_PixelClk rise@0.000ns) Data Path Delay: 0.428ns (logic 0.148ns (34.549%) route 0.280ns (65.451%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.263ns Source Clock Delay (SCD): 1.894ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.481 0.481 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.440 0.921 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.051 0.972 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.363 1.335 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.270 1.605 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.289 1.894 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/out SLICE_X152Y104 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/shifted_data_in_reg[8][20]/C ------------------------------------------------------------------- ------------------- SLICE_X152Y104 FDRE (Prop_fdre_C_Q) 0.148 2.042 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/shifted_data_in_reg[8][20]/Q net (fo=1, routed) 0.280 2.322 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/CAP_TRIGGER_O_reg[2] RAMB36_X8Y20 RAMB36E1 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2] ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.529 0.529 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.480 1.009 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.054 1.063 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.402 1.465 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.431 1.896 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.367 2.263 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/out RAMB36_X8Y20 RAMB36E1 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK clock pessimism -0.291 1.973 clock uncertainty 0.053 2.026 RAMB36_X8Y20 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[2]) 0.243 2.269 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ------------------------------------------------------------------- required time -2.269 arrival time 2.322 ------------------------------------------------------------------- slack 0.054 --------------------------------------------------------------------------------------------------- From Clock: hdmi_i/dvi2rgb_0/U0/RefClk To Clock: dvi2rgb_0_PixelClk_1 Setup : 0 Failing Endpoints, Worst Slack 0.707ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.126ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.707ns (required time - arrival time) Source: hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C (rising edge-triggered cell FDCE clocked by hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: dvi2rgb_0_PixelClk_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (dvi2rgb_0_PixelClk_1 rise@12.500ns - hdmi_i/dvi2rgb_0/U0/RefClk rise@10.000ns) Data Path Delay: 4.527ns (logic 0.580ns (12.811%) route 3.947ns (87.189%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 2.858ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.865ns = ( 17.365 - 12.500 ) Source Clock Delay (SCD): 2.007ns = ( 12.007 - 10.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.155ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.101ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 10.000 10.000 r BUFGCTRL_X0Y17 BUFG 0.000 10.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 2.007 12.007 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/RefClk SLICE_X160Y94 FDCE r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C ------------------------------------------------------------------- ------------------- SLICE_X160Y94 FDCE (Prop_fdce_C_Q) 0.456 12.463 f hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/Q net (fo=4, routed) 3.947 16.411 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/dcm_locked SLICE_X149Y143 LUT4 (Prop_lut4_I2_O) 0.124 16.535 r hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int0/O net (fo=1, routed) 0.000 16.535 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int0__0 SLICE_X149Y143 FDRE r hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 12.500 12.500 r V4 0.000 12.500 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 12.500 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.916 13.416 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.162 14.578 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.084 14.662 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.960 15.622 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.918 16.540 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.825 17.365 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/slowest_sync_clk SLICE_X149Y143 FDRE r hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/C clock pessimism 0.000 17.365 clock uncertainty -0.155 17.211 SLICE_X149Y143 FDRE (Setup_fdre_C_D) 0.031 17.242 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg ------------------------------------------------------------------- required time 17.242 arrival time -16.535 ------------------------------------------------------------------- slack 0.707 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.126ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C (rising edge-triggered cell FDCE clocked by hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: dvi2rgb_0_PixelClk_1 Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (dvi2rgb_0_PixelClk_1 rise@0.000ns - hdmi_i/dvi2rgb_0/U0/RefClk rise@0.000ns) Data Path Delay: 3.827ns (logic 0.467ns (12.202%) route 3.360ns (87.798%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 3.276ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.157ns Source Clock Delay (SCD): 1.881ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.155ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.101ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.881 1.881 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/RefClk SLICE_X160Y94 FDCE r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C ------------------------------------------------------------------- ------------------- SLICE_X160Y94 FDCE (Prop_fdce_C_Q) 0.367 2.248 f hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/Q net (fo=4, routed) 3.360 5.608 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/dcm_locked SLICE_X149Y143 LUT4 (Prop_lut4_I2_O) 0.100 5.708 r hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int0/O net (fo=1, routed) 0.000 5.708 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int0__0 SLICE_X149Y143 FDRE r hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/D ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.960 0.960 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.233 2.193 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.089 2.282 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 1.025 3.307 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.982 4.289 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.868 5.157 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/slowest_sync_clk SLICE_X149Y143 FDRE r hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg/C clock pessimism 0.000 5.157 clock uncertainty 0.155 5.312 SLICE_X149Y143 FDRE (Hold_fdre_C_D) 0.270 5.582 hdmi_i/rst_mig_7series_0_pxl/U0/EXT_LPF/lpf_int_reg ------------------------------------------------------------------- required time -5.582 arrival time 5.708 ------------------------------------------------------------------- slack 0.126 --------------------------------------------------------------------------------------------------- From Clock: clk_pll_i To Clock: dvi2rgb_0_PixelClk_1 Setup : 0 Failing Endpoints, Worst Slack 8.436ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 8.436ns (required time - arrival time) Source: hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.proc_sync1_reg[38]/C (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2VIDCLK_I/data_sync_reg[0][38]/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: dvi2rgb_0_PixelClk_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) Data Path Delay: 1.471ns (logic 0.456ns (30.998%) route 1.015ns (69.002%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X131Y135 0.000 0.000 r hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.proc_sync1_reg[38]/C SLICE_X131Y135 FDRE (Prop_fdre_C_Q) 0.456 0.456 r hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.proc_sync1_reg[38]/Q net (fo=1, routed) 1.015 1.471 hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2VIDCLK_I/AXI4_LITE_INTERFACE.proc_sync1_reg[44][38] SLICE_X110Y135 FDRE r hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2VIDCLK_I/data_sync_reg[0][38]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 SLICE_X110Y135 FDRE (Setup_fdre_C_D) -0.093 9.907 hdmi_i/v_tc_1/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.SYNC2VIDCLK_I/data_sync_reg[0][38] ------------------------------------------------------------------- required time 9.907 arrival time -1.471 ------------------------------------------------------------------- slack 8.436 --------------------------------------------------------------------------------------------------- From Clock: mmcm_clkout0 To Clock: dvi2rgb_0_PixelClk_1 Setup : 0 Failing Endpoints, Worst Slack 5.048ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.048ns (required time - arrival time) Source: hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Destination: hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: dvi2rgb_0_PixelClk_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 6.250ns (MaxDelay Path 6.250ns) Data Path Delay: 1.186ns (logic 0.456ns (38.450%) route 0.730ns (61.550%)) Logic Levels: 0 Timing Exception: MaxDelay Path 6.250ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X147Y133 0.000 0.000 r hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C SLICE_X147Y133 FDRE (Prop_fdre_C_Q) 0.456 0.456 r hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q net (fo=1, routed) 0.730 1.186 hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3] SLICE_X146Y139 FDRE r hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 6.250 6.250 SLICE_X146Y139 FDRE (Setup_fdre_C_D) -0.016 6.234 hdmi_i/v_vid_in_axi4s_0/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- required time 6.234 arrival time -1.186 ------------------------------------------------------------------- slack 5.048 --------------------------------------------------------------------------------------------------- From Clock: mmcm_clkout1 To Clock: dvi2rgb_0_PixelClk_1 Setup : 21 Failing Endpoints, Worst Slack -2.196ns, Total Violation -39.098ns Hold : 4 Failing Endpoints, Worst Slack -0.373ns, Total Violation -0.835ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -2.196ns (required time - arrival time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_srlB/S2/CLK (rising edge-triggered cell SRL16E clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: dvi2rgb_0_PixelClk_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (dvi2rgb_0_PixelClk_1 rise@12.500ns - mmcm_clkout1 rise@10.000ns) Data Path Delay: 3.850ns (logic 2.546ns (66.133%) route 1.304ns (33.867%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: -0.660ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.803ns = ( 17.303 - 12.500 ) Source Clock Delay (SCD): 5.464ns = ( 15.464 - 10.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.205ns Phase Error (PE): 0.153ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 11.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 12.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 12.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 14.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 14.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 15.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -3.633 11.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 1.808 13.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 13.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.833 15.464 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_srlB/CLK SLICE_X158Y101 SRL16E r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_srlB/S2/CLK ------------------------------------------------------------------- ------------------- SLICE_X158Y101 SRL16E (Prop_srl16e_CLK_Q) 1.632 17.096 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_srlB/S2/Q net (fo=1, routed) 0.573 17.669 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/mux_di[1] SLICE_X158Y100 CARRY4 (Prop_carry4_DI[1]_CO[3]) 0.795 18.464 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_carry4_inst/CO[3] net (fo=1, routed) 0.731 19.194 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/shift_en_reg SLICE_X160Y100 LUT2 (Prop_lut2_I1_O) 0.119 19.313 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/u_wcnt_lcmp_q_i_1/O net (fo=1, routed) 0.000 19.313 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp SLICE_X160Y100 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q/D ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 12.500 12.500 r V4 0.000 12.500 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 12.500 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.916 13.416 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.162 14.578 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.084 14.662 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.960 15.622 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.918 16.540 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.763 17.303 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/out SLICE_X160Y100 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q/C clock pessimism 0.000 17.303 clock uncertainty -0.261 17.042 SLICE_X160Y100 FDRE (Setup_fdre_C_D) 0.075 17.117 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/u_wcnt_lcmp_q ------------------------------------------------------------------- required time 17.117 arrival time -19.313 ------------------------------------------------------------------- slack -2.196 Min Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -0.373ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/S2/CLK (rising edge-triggered cell SRL16E clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D (rising edge-triggered cell FDRE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: dvi2rgb_0_PixelClk_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (dvi2rgb_0_PixelClk_1 rise@0.000ns - mmcm_clkout1 rise@0.000ns) Data Path Delay: 0.612ns (logic 0.612ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 2 (CARRY4=2) Clock Path Skew: 0.669ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.222ns Source Clock Delay (SCD): 1.553ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.205ns Phase Error (PE): 0.153ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 0.622 1.553 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/CLK SLICE_X150Y103 SRL16E r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/S2/CLK ------------------------------------------------------------------- ------------------- SLICE_X150Y103 SRL16E (Prop_srl16e_CLK_Q) 0.488 2.041 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/S2/Q net (fo=1, routed) 0.000 2.041 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/mux_di[2] SLICE_X150Y103 CARRY4 (Prop_carry4_DI[2]_CO[3]) 0.084 2.125 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_carry4_inst/CO[3] net (fo=1, routed) 0.000 2.125 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/DOUT_O SLICE_X150Y104 CARRY4 (Prop_carry4_CI_CO[3]) 0.040 2.165 r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/u_carry4_inst/CO[3] net (fo=1, routed) 0.000 2.165 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/muxcy_lo[3] SLICE_X150Y104 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/D ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.529 0.529 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.480 1.009 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.054 1.063 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.402 1.465 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.431 1.896 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.326 2.222 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/rMMCM_LckdRisingFlag_reg SLICE_X150Y104 FDRE r hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg/C clock pessimism 0.000 2.222 clock uncertainty 0.261 2.483 SLICE_X150Y104 FDRE (Hold_fdre_C_D) 0.055 2.538 hdmi_i/dvi2rgb_0/U0/GenerateDebug.ILA_PixClkx/U0/ila_core_inst/u_trig/N_DDR_TC.N_DDR_TC_INST[0].U_TC/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/DUT/I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE/I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg ------------------------------------------------------------------- required time -2.538 arrival time 2.165 ------------------------------------------------------------------- slack -0.373 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: axi_dynclk_0_PXL_CLK_O To Clock: axi_dynclk_0_PXL_CLK_O Setup : 0 Failing Endpoints, Worst Slack 4.983ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.440ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.983ns (required time - arrival time) Source: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_rd_rst_reg[0]/C (rising edge-triggered cell FDRE clocked by axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Destination: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST (recovery check against rising-edge clock axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (axi_dynclk_0_PXL_CLK_O rise@10.000ns - axi_dynclk_0_PXL_CLK_O rise@0.000ns) Data Path Delay: 2.622ns (logic 0.642ns (24.489%) route 1.980ns (75.511%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 11.436ns = ( 21.436 - 10.000 ) Source Clock Delay (SCD): 12.117ns Clock Pessimism Removal (CPR): 0.713ns Clock Uncertainty: 0.060ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.097ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_dynclk_0_PXL_CLK_O rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.918 5.549 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/REF_CLK_I MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.088 5.637 r hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 3.038 8.675 hdmi_i/axi_dynclk_0/U0/mmcm_clk BUFMRCE_X1Y2 BUFMR (Prop_bufmr_I_O) 0.103 8.778 r hdmi_i/axi_dynclk_0/U0/GenerateBUFMR.BUFMR_inst/O net (fo=2, routed) 1.394 10.172 hdmi_i/axi_dynclk_0/U0/I BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.982 11.154 r hdmi_i/axi_dynclk_0/U0/BUFR_inst/O net (fo=3041, routed) 0.963 12.117 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/m_axis_mm2s_aclk SLICE_X136Y139 FDRE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_rd_rst_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X136Y139 FDRE (Prop_fdre_C_Q) 0.518 12.635 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_rd_rst_reg[0]/Q net (fo=1, routed) 0.415 13.049 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/power_on_rd_rst[0] SLICE_X135Y139 LUT2 (Prop_lut2_I1_O) 0.124 13.173 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/gf36e1_inst.sngfifo36e1_i_2__2/O net (fo=5, routed) 1.565 14.738 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/RST RAMB36_X6Y25 FIFO36E1 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST ------------------------------------------------------------------- ------------------- (clock axi_dynclk_0_PXL_CLK_O rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 12.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 12.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.289 14.057 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.081 14.138 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.904 15.042 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.425 11.617 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.723 13.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.792 15.223 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/REF_CLK_I MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.083 15.306 r hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 2.848 18.154 hdmi_i/axi_dynclk_0/U0/mmcm_clk BUFMRCE_X1Y2 BUFMR (Prop_bufmr_I_O) 0.097 18.251 r hdmi_i/axi_dynclk_0/U0/GenerateBUFMR.BUFMR_inst/O net (fo=2, routed) 1.289 19.540 hdmi_i/axi_dynclk_0/U0/I BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.918 20.458 r hdmi_i/axi_dynclk_0/U0/BUFR_inst/O net (fo=3041, routed) 0.978 21.436 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/m_axis_mm2s_aclk RAMB36_X6Y25 FIFO36E1 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RDCLK clock pessimism 0.713 22.149 clock uncertainty -0.060 22.089 RAMB36_X6Y25 FIFO36E1 (Recov_fifo36e1_RDCLK_RST) -2.368 19.721 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1 ------------------------------------------------------------------- required time 19.721 arrival time -14.738 ------------------------------------------------------------------- slack 4.983 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.440ns (arrival time - required time) Source: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg2_reg/C (rising edge-triggered cell FDPE clocked by axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Destination: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg_reg/PRE (removal check against rising-edge clock axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axi_dynclk_0_PXL_CLK_O rise@0.000ns - axi_dynclk_0_PXL_CLK_O rise@0.000ns) Data Path Delay: 0.306ns (logic 0.128ns (41.788%) route 0.178ns (58.212%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 4.815ns Source Clock Delay (SCD): 3.709ns Clock Pessimism Removal (CPR): 1.091ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_dynclk_0_PXL_CLK_O rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.671 1.603 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/REF_CLK_I MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.050 1.653 r hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.945 2.598 hdmi_i/axi_dynclk_0/U0/mmcm_clk BUFMRCE_X1Y2 BUFMR (Prop_bufmr_I_O) 0.033 2.631 r hdmi_i/axi_dynclk_0/U0/GenerateBUFMR.BUFMR_inst/O net (fo=2, routed) 0.487 3.118 hdmi_i/axi_dynclk_0/U0/I BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.270 3.388 r hdmi_i/axi_dynclk_0/U0/BUFR_inst/O net (fo=3041, routed) 0.321 3.709 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/m_axis_mm2s_aclk SLICE_X135Y140 FDPE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y140 FDPE (Prop_fdpe_C_Q) 0.128 3.837 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg2_reg/Q net (fo=1, routed) 0.178 4.015 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rd_rst_reg2 SLICE_X135Y139 FDPE f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg_reg/PRE ------------------------------------------------------------------- ------------------- (clock axi_dynclk_0_PXL_CLK_O rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.472 1.480 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.043 1.523 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.538 2.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.475 0.586 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.579 1.164 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.193 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.944 2.137 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/REF_CLK_I MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.053 2.190 r hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.256 3.446 hdmi_i/axi_dynclk_0/U0/mmcm_clk BUFMRCE_X1Y2 BUFMR (Prop_bufmr_I_O) 0.035 3.481 r hdmi_i/axi_dynclk_0/U0/GenerateBUFMR.BUFMR_inst/O net (fo=2, routed) 0.544 4.025 hdmi_i/axi_dynclk_0/U0/I BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.431 4.456 r hdmi_i/axi_dynclk_0/U0/BUFR_inst/O net (fo=3041, routed) 0.359 4.815 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/m_axis_mm2s_aclk SLICE_X135Y139 FDPE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg_reg/C clock pessimism -1.091 3.724 SLICE_X135Y139 FDPE (Remov_fdpe_C_PRE) -0.149 3.575 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg_reg ------------------------------------------------------------------- required time -3.575 arrival time 4.015 ------------------------------------------------------------------- slack 0.440 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_pll_i To Clock: axi_dynclk_0_PXL_CLK_O Setup : 0 Failing Endpoints, Worst Slack 6.675ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.315ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 6.675ns (required time - arrival time) Source: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg/C (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg1_reg/PRE (recovery check against rising-edge clock axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (axi_dynclk_0_PXL_CLK_O rise@10.000ns - clk_pll_i rise@0.000ns) Data Path Delay: 8.840ns (logic 0.419ns (4.740%) route 8.421ns (95.260%)) Logic Levels: 0 Clock Path Skew: 6.261ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 11.385ns = ( 21.385 - 10.000 ) Source Clock Delay (SCD): 5.324ns Clock Pessimism Removal (CPR): 0.199ns Clock Uncertainty: 0.211ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.097ns Phase Error (PE): 0.151ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.693 5.324 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/m_axi_mm2s_aclk SLICE_X133Y143 FDRE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y143 FDRE (Prop_fdre_C_Q) 0.419 5.743 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg/Q net (fo=2, routed) 8.421 14.164 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/s_axis_fifo_ainit_nosync_reg SLICE_X135Y140 FDPE f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg1_reg/PRE ------------------------------------------------------------------- ------------------- (clock axi_dynclk_0_PXL_CLK_O rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 12.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 12.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.289 14.057 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.081 14.138 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.904 15.042 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.425 11.617 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.723 13.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.792 15.223 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/REF_CLK_I MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.083 15.306 r hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 2.848 18.154 hdmi_i/axi_dynclk_0/U0/mmcm_clk BUFMRCE_X1Y2 BUFMR (Prop_bufmr_I_O) 0.097 18.251 r hdmi_i/axi_dynclk_0/U0/GenerateBUFMR.BUFMR_inst/O net (fo=2, routed) 1.289 19.540 hdmi_i/axi_dynclk_0/U0/I BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.918 20.458 r hdmi_i/axi_dynclk_0/U0/BUFR_inst/O net (fo=3041, routed) 0.927 21.385 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/m_axis_mm2s_aclk SLICE_X135Y140 FDPE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg1_reg/C clock pessimism 0.199 21.584 clock uncertainty -0.211 21.373 SLICE_X135Y140 FDPE (Recov_fdpe_C_PRE) -0.534 20.839 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg1_reg ------------------------------------------------------------------- required time 20.839 arrival time -14.164 ------------------------------------------------------------------- slack 6.675 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.315ns (arrival time - required time) Source: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg/C (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg1_reg/PRE (removal check against rising-edge clock axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (axi_dynclk_0_PXL_CLK_O rise@0.000ns - clk_pll_i rise@0.000ns) Data Path Delay: 3.402ns (logic 0.128ns (3.762%) route 3.274ns (96.238%)) Logic Levels: 0 Clock Path Skew: 3.026ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 4.816ns Source Clock Delay (SCD): 1.528ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.211ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.097ns Phase Error (PE): 0.151ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.597 1.528 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/m_axi_mm2s_aclk SLICE_X133Y143 FDRE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg/C ------------------------------------------------------------------- ------------------- SLICE_X133Y143 FDRE (Prop_fdre_C_Q) 0.128 1.656 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.s_axis_fifo_ainit_nosync_reg_reg/Q net (fo=2, routed) 3.274 4.931 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/s_axis_fifo_ainit_nosync_reg SLICE_X135Y140 FDPE f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg1_reg/PRE ------------------------------------------------------------------- ------------------- (clock axi_dynclk_0_PXL_CLK_O rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.472 1.480 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.043 1.523 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.538 2.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.475 0.586 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.579 1.164 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.193 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.944 2.137 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/REF_CLK_I MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.053 2.190 r hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.256 3.446 hdmi_i/axi_dynclk_0/U0/mmcm_clk BUFMRCE_X1Y2 BUFMR (Prop_bufmr_I_O) 0.035 3.481 r hdmi_i/axi_dynclk_0/U0/GenerateBUFMR.BUFMR_inst/O net (fo=2, routed) 0.544 4.025 hdmi_i/axi_dynclk_0/U0/I BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.431 4.456 r hdmi_i/axi_dynclk_0/U0/BUFR_inst/O net (fo=3041, routed) 0.360 4.816 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/m_axis_mm2s_aclk SLICE_X135Y140 FDPE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg1_reg/C clock pessimism -0.262 4.554 clock uncertainty 0.211 4.765 SLICE_X135Y140 FDPE (Remov_fdpe_C_PRE) -0.149 4.616 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg1_reg ------------------------------------------------------------------- required time -4.616 arrival time 4.931 ------------------------------------------------------------------- slack 0.315 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: axi_dynclk_0_PXL_CLK_O To Clock: clk_pll_i Setup : 5 Failing Endpoints, Worst Slack -2.099ns, Total Violation -9.064ns Hold : 0 Failing Endpoints, Worst Slack 3.052ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -2.099ns (required time - arrival time) Source: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_rd_rst_reg[0]/C (rising edge-triggered cell FDRE clocked by axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Destination: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (clk_pll_i rise@10.000ns - axi_dynclk_0_PXL_CLK_O rise@0.000ns) Data Path Delay: 2.622ns (logic 0.642ns (24.489%) route 1.980ns (75.511%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -6.900ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.018ns = ( 15.018 - 10.000 ) Source Clock Delay (SCD): 12.117ns Clock Pessimism Removal (CPR): 0.199ns Clock Uncertainty: 0.210ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.096ns Phase Error (PE): 0.151ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_dynclk_0_PXL_CLK_O rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.918 5.549 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/REF_CLK_I MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.088 5.637 r hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 3.038 8.675 hdmi_i/axi_dynclk_0/U0/mmcm_clk BUFMRCE_X1Y2 BUFMR (Prop_bufmr_I_O) 0.103 8.778 r hdmi_i/axi_dynclk_0/U0/GenerateBUFMR.BUFMR_inst/O net (fo=2, routed) 1.394 10.172 hdmi_i/axi_dynclk_0/U0/I BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.982 11.154 r hdmi_i/axi_dynclk_0/U0/BUFR_inst/O net (fo=3041, routed) 0.963 12.117 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/m_axis_mm2s_aclk SLICE_X136Y139 FDRE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_rd_rst_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X136Y139 FDRE (Prop_fdre_C_Q) 0.518 12.635 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_rd_rst_reg[0]/Q net (fo=1, routed) 0.415 13.049 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/power_on_rd_rst[0] SLICE_X135Y139 LUT2 (Prop_lut2_I1_O) 0.124 13.173 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/gf36e1_inst.sngfifo36e1_i_2__2/O net (fo=5, routed) 1.565 14.738 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/RST RAMB36_X6Y25 FIFO36E1 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 12.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 12.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.289 14.057 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.081 14.138 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.904 15.042 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.425 11.617 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.723 13.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.587 15.018 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/m_axi_mm2s_aclk RAMB36_X6Y25 FIFO36E1 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/WRCLK clock pessimism 0.199 15.217 clock uncertainty -0.210 15.007 RAMB36_X6Y25 FIFO36E1 (Recov_fifo36e1_WRCLK_RST) -2.368 12.639 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[1].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1 ------------------------------------------------------------------- required time 12.639 arrival time -14.738 ------------------------------------------------------------------- slack -2.099 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.052ns (arrival time - required time) Source: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg_reg/C (rising edge-triggered cell FDPE clocked by axi_dynclk_0_PXL_CLK_O {rise@0.000ns fall@4.000ns period=10.000ns}) Destination: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_pll_i rise@0.000ns - axi_dynclk_0_PXL_CLK_O rise@0.000ns) Data Path Delay: 0.816ns (logic 0.186ns (22.781%) route 0.630ns (77.219%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -1.857ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.112ns Source Clock Delay (SCD): 3.708ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.210ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.096ns Phase Error (PE): 0.151ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock axi_dynclk_0_PXL_CLK_O rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.671 1.603 hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/REF_CLK_I MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.050 1.653 r hdmi_i/axi_dynclk_0/U0/Inst_mmcme2_drp/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.945 2.598 hdmi_i/axi_dynclk_0/U0/mmcm_clk BUFMRCE_X1Y2 BUFMR (Prop_bufmr_I_O) 0.033 2.631 r hdmi_i/axi_dynclk_0/U0/GenerateBUFMR.BUFMR_inst/O net (fo=2, routed) 0.487 3.118 hdmi_i/axi_dynclk_0/U0/I BUFR_X1Y8 BUFR (Prop_bufr_I_O) 0.270 3.388 r hdmi_i/axi_dynclk_0/U0/BUFR_inst/O net (fo=3041, routed) 0.320 3.708 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/m_axis_mm2s_aclk SLICE_X135Y139 FDPE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg_reg/C ------------------------------------------------------------------- ------------------- SLICE_X135Y139 FDPE (Prop_fdpe_C_Q) 0.141 3.849 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg_reg/Q net (fo=3, routed) 0.125 3.974 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rd_rst_reg SLICE_X135Y139 LUT2 (Prop_lut2_I0_O) 0.045 4.019 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/gf36e1_inst.sngfifo36e1_i_2__2/O net (fo=5, routed) 0.505 4.524 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/RST RAMB36_X7Y25 FIFO36E1 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.472 1.480 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.043 1.523 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.538 2.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.475 0.586 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.579 1.164 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.193 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.919 2.112 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/m_axi_mm2s_aclk RAMB36_X7Y25 FIFO36E1 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/WRCLK clock pessimism -0.262 1.851 clock uncertainty 0.210 2.061 RAMB36_X7Y25 FIFO36E1 (Remov_fifo36e1_WRCLK_RST) -0.589 1.472 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[5].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1 ------------------------------------------------------------------- required time -1.472 arrival time 4.524 ------------------------------------------------------------------- slack 3.052 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_pll_i To Clock: clk_pll_i Setup : 0 Failing Endpoints, Worst Slack 5.859ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.593ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.859ns (required time - arrival time) Source: hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/CLR (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (clk_pll_i rise@10.000ns - clk_pll_i rise@0.000ns) Data Path Delay: 3.537ns (logic 0.773ns (21.856%) route 2.764ns (78.144%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.139ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.967ns = ( 14.967 - 10.000 ) Source Clock Delay (SCD): 5.384ns Clock Pessimism Removal (CPR): 0.279ns Clock Uncertainty: 0.060ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.098ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.754 5.384 hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk SLICE_X22Y194 FDPE r hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X22Y194 FDPE (Prop_fdpe_C_Q) 0.478 5.862 f hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/Q net (fo=3, routed) 0.883 6.745 hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst_wr_reg2 SLICE_X23Y194 LUT3 (Prop_lut3_I2_O) 0.295 7.040 f hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gc0.count_d1[4]_i_2/O net (fo=32, routed) 1.881 8.921 hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AS[0] SLICE_X54Y194 FDCE f hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 10.000 10.000 r R4 0.000 10.000 r sys_clk_i (IN) net (fo=0) 0.000 10.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 11.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 12.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 12.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.289 14.057 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.081 14.138 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.904 15.042 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.425 11.617 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.723 13.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 13.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.536 14.967 hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk SLICE_X54Y194 FDCE r hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2]/C clock pessimism 0.279 15.245 clock uncertainty -0.060 15.185 SLICE_X54Y194 FDCE (Recov_fdce_C_CLR) -0.405 14.780 hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[2] ------------------------------------------------------------------- required time 14.780 arrival time -8.921 ------------------------------------------------------------------- slack 5.859 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.593ns (arrival time - required time) Source: hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) Data Path Delay: 0.562ns (logic 0.186ns (33.115%) route 0.376ns (66.885%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.138ns Source Clock Delay (SCD): 1.602ns Clock Pessimism Removal (CPR): 0.500ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.670 1.602 hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk SLICE_X45Y206 FDRE r hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y206 FDRE (Prop_fdre_C_Q) 0.141 1.743 f hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q net (fo=3, routed) 0.181 1.924 hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/sckt_wr_rst_cc[0] SLICE_X45Y206 LUT3 (Prop_lut3_I0_O) 0.045 1.969 f hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gc0.count_d1[4]_i_2/O net (fo=32, routed) 0.194 2.163 hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0] SLICE_X46Y205 FDCE f hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.472 1.480 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.043 1.523 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.538 2.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.475 0.586 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.579 1.164 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.193 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.944 2.138 hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk SLICE_X46Y205 FDCE r hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/C clock pessimism -0.500 1.638 SLICE_X46Y205 FDCE (Remov_fdce_C_CLR) -0.067 1.571 hdmi_i/axi_mem_intercon/m00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1] ------------------------------------------------------------------- required time -1.571 arrival time 2.163 ------------------------------------------------------------------- slack 0.593 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: mmcm_clkout0 To Clock: clk_pll_i Setup : 5 Failing Endpoints, Worst Slack -3.327ns, Total Violation -16.121ns Hold : 0 Failing Endpoints, Worst Slack 0.624ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -3.327ns (required time - arrival time) Source: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_wr_rst_reg[0]/C (rising edge-triggered cell FDRE clocked by mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Destination: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 1.250ns (clk_pll_i rise@20.000ns - mmcm_clkout0 rise@18.750ns) Data Path Delay: 2.070ns (logic 0.580ns (28.016%) route 1.490ns (71.984%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.269ns = ( 25.269 - 20.000 ) Source Clock Delay (SCD): 5.323ns = ( 24.073 - 18.750 ) Clock Pessimism Removal (CPR): 0.109ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout0 rise edge) 18.750 18.750 r R4 0.000 18.750 r sys_clk_i (IN) net (fo=0) 0.000 18.750 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 20.225 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 21.581 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 21.669 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 23.039 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 23.166 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 24.109 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.633 20.476 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0 net (fo=1, routed) 1.808 22.284 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout0 BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 22.380 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_0/O net (fo=624, routed) 1.692 24.073 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/s_axis_s2mm_aclk SLICE_X139Y109 FDRE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_wr_rst_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y109 FDRE (Prop_fdre_C_Q) 0.456 24.529 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_wr_rst_reg[0]/Q net (fo=3, routed) 0.588 25.117 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/power_on_wr_rst[0] SLICE_X138Y111 LUT2 (Prop_lut2_I1_O) 0.124 25.241 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/gf36e1_inst.sngfifo36e1_i_2__3/O net (fo=3, routed) 0.902 26.143 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/RST RAMB36_X7Y19 FIFO36E1 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 20.000 20.000 r R4 0.000 20.000 r sys_clk_i (IN) net (fo=0) 0.000 20.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 21.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 22.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 22.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.289 24.057 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.081 24.138 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.904 25.042 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -3.425 21.617 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 1.723 23.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 23.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 1.838 25.269 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/m_axi_s2mm_aclk RAMB36_X7Y19 FIFO36E1 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RDCLK clock pessimism 0.109 25.378 clock uncertainty -0.194 25.184 RAMB36_X7Y19 FIFO36E1 (Recov_fifo36e1_RDCLK_RST) -2.368 22.816 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1 ------------------------------------------------------------------- required time 22.816 arrival time -26.143 ------------------------------------------------------------------- slack -3.327 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.624ns (arrival time - required time) Source: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_reg_reg/C (rising edge-triggered cell FDPE clocked by mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Destination: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_pll_i rise@0.000ns - mmcm_clkout0 rise@0.000ns) Data Path Delay: 0.619ns (logic 0.186ns (30.069%) route 0.433ns (69.931%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.126ns Source Clock Delay (SCD): 1.526ns Clock Pessimism Removal (CPR): 0.211ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout0 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0 net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout0 BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_0/O net (fo=624, routed) 0.595 1.526 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/s_axis_s2mm_aclk SLICE_X139Y110 FDPE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_reg_reg/C ------------------------------------------------------------------- ------------------- SLICE_X139Y110 FDPE (Prop_fdpe_C_Q) 0.141 1.667 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_reg_reg/Q net (fo=5, routed) 0.191 1.858 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/wr_rst_reg SLICE_X139Y108 LUT2 (Prop_lut2_I0_O) 0.045 1.903 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/gf36e1_inst.sngfifo36e1_i_2__3_replica_1/O net (fo=1, routed) 0.241 2.145 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/RST_repN_1_alias RAMB36_X7Y21 FIFO36E1 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST ------------------------------------------------------------------- ------------------- (clock clk_pll_i rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.472 1.480 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.043 1.523 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.538 2.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.475 0.586 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT net (fo=1, routed) 0.579 1.164 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/clk_pll_i BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.193 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O net (fo=24767, routed) 0.933 2.126 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/m_axi_s2mm_aclk RAMB36_X7Y21 FIFO36E1 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RDCLK clock pessimism -0.211 1.915 clock uncertainty 0.194 2.109 RAMB36_X7Y21 FIFO36E1 (Remov_fifo36e1_RDCLK_RST) -0.589 1.520 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[3].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1 ------------------------------------------------------------------- required time -1.520 arrival time 2.145 ------------------------------------------------------------------- slack 0.624 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK To Clock: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK Setup : 0 Failing Endpoints, Worst Slack 27.438ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.351ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 27.438ns (required time - arrival time) Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns}) Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns) Data Path Delay: 5.186ns (logic 0.828ns (15.966%) route 4.358ns (84.034%)) Logic Levels: 3 (LUT1=1 LUT4=1 LUT6=1) Clock Path Skew: 0.065ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.505ns = ( 37.505 - 33.000 ) Source Clock Delay (SCD): 4.869ns Clock Pessimism Removal (CPR): 0.428ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge) 0.000 0.000 r BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK net (fo=1, routed) 3.112 3.112 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 3.208 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O net (fo=483, routed) 1.660 4.869 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck SLICE_X67Y110 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y110 FDRE (Prop_fdre_C_Q) 0.456 5.325 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[2]/Q net (fo=1, routed) 0.855 6.180 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[2] SLICE_X67Y110 LUT6 (Prop_lut6_I3_O) 0.124 6.304 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O net (fo=5, routed) 0.753 7.057 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0 SLICE_X70Y107 LUT4 (Prop_lut4_I0_O) 0.124 7.181 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O net (fo=2, routed) 2.092 9.273 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/state_reg[1]_0 SLICE_X96Y97 LUT1 (Prop_lut1_I0_O) 0.124 9.397 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_2/O net (fo=10, routed) 0.658 10.055 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n SLICE_X97Y97 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge) 33.000 33.000 r BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK net (fo=1, routed) 2.697 35.697 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 35.788 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O net (fo=483, routed) 1.717 37.505 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0] SLICE_X97Y97 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/C clock pessimism 0.428 37.933 clock uncertainty -0.035 37.898 SLICE_X97Y97 FDCE (Recov_fdce_C_CLR) -0.405 37.493 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12] ------------------------------------------------------------------- required time 37.493 arrival time -10.055 ------------------------------------------------------------------- slack 27.438 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.351ns (arrival time - required time) Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns}) Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns) Data Path Delay: 0.299ns (logic 0.164ns (54.821%) route 0.135ns (45.179%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.553ns Source Clock Delay (SCD): 2.094ns Clock Pessimism Removal (CPR): 0.444ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge) 0.000 0.000 r BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK net (fo=1, routed) 1.422 1.422 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.448 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O net (fo=483, routed) 0.645 2.094 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/m_bscan_tck[0] SLICE_X100Y84 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X100Y84 FDPE (Prop_fdpe_C_Q) 0.164 2.258 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q net (fo=18, routed) 0.135 2.393 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/out[1] SLICE_X100Y85 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge) 0.000 0.000 r BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK net (fo=1, routed) 1.605 1.605 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.634 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O net (fo=483, routed) 0.919 2.553 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/m_bscan_tck[0] SLICE_X100Y85 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/C clock pessimism -0.444 2.109 SLICE_X100Y85 FDCE (Remov_fdce_C_CLR) -0.067 2.042 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0] ------------------------------------------------------------------- required time -2.042 arrival time 2.393 ------------------------------------------------------------------- slack 0.351 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: dvi2rgb_0_PixelClk To Clock: dvi2rgb_0_PixelClk Setup : 0 Failing Endpoints, Worst Slack 4.027ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.651ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.027ns (required time - arrival time) Source: hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C (rising edge-triggered cell FDPE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Destination: hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg/PRE (recovery check against rising-edge clock dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.060ns (dvi2rgb_0_PixelClk rise@6.060ns - dvi2rgb_0_PixelClk rise@0.000ns) Data Path Delay: 1.459ns (logic 0.419ns (28.725%) route 1.040ns (71.275%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.854ns = ( 10.914 - 6.060 ) Source Clock Delay (SCD): 5.090ns Clock Pessimism Removal (CPR): 0.249ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.960 0.960 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.233 2.193 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.089 2.282 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 1.025 3.307 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.982 4.289 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.801 5.090 hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/OutClk SLICE_X163Y139 FDPE r hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X163Y139 FDPE (Prop_fdpe_C_Q) 0.419 5.509 f hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/Q net (fo=28, routed) 1.040 6.549 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/aRst SLICE_X155Y131 FDPE f hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg/PRE ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 6.060 6.060 r V4 0.000 6.060 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 6.060 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.916 6.976 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.162 8.138 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.084 8.222 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.960 9.182 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.918 10.100 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.814 10.914 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/PixelClk SLICE_X155Y131 FDPE r hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg/C clock pessimism 0.249 11.163 clock uncertainty -0.053 11.110 SLICE_X155Y131 FDPE (Recov_fdpe_C_PRE) -0.534 10.576 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg ------------------------------------------------------------------- required time 10.576 arrival time -6.549 ------------------------------------------------------------------- slack 4.027 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.651ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C (rising edge-triggered cell FDPE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Destination: hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg/PRE (removal check against rising-edge clock dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (dvi2rgb_0_PixelClk rise@0.000ns - dvi2rgb_0_PixelClk rise@0.000ns) Data Path Delay: 0.531ns (logic 0.128ns (24.097%) route 0.403ns (75.903%)) Logic Levels: 0 Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.186ns Source Clock Delay (SCD): 1.866ns Clock Pessimism Removal (CPR): 0.291ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.481 0.481 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.440 0.921 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.051 0.972 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.363 1.335 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.270 1.605 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.261 1.866 hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/OutClk SLICE_X163Y139 FDPE r hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X163Y139 FDPE (Prop_fdpe_C_Q) 0.128 1.994 f hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/Q net (fo=28, routed) 0.403 2.397 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/aRst SLICE_X159Y130 FDPE f hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg/PRE ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.529 0.529 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.480 1.009 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.054 1.063 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.402 1.465 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.431 1.896 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.290 2.186 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/PixelClk SLICE_X159Y130 FDPE r hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg/C clock pessimism -0.291 1.895 SLICE_X159Y130 FDPE (Remov_fdpe_C_PRE) -0.149 1.746 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg ------------------------------------------------------------------- required time -1.746 arrival time 2.397 ------------------------------------------------------------------- slack 0.651 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: dvi2rgb_0_PixelClk_1 To Clock: dvi2rgb_0_PixelClk Setup : 3 Failing Endpoints, Worst Slack -2.013ns, Total Violation -5.807ns Hold : 0 Failing Endpoints, Worst Slack 0.598ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -2.013ns (required time - arrival time) Source: hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C (rising edge-triggered cell FDPE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Destination: hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg/PRE (recovery check against rising-edge clock dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 0.020ns (dvi2rgb_0_PixelClk rise@3587.520ns - dvi2rgb_0_PixelClk_1 rise@3587.500ns) Data Path Delay: 1.459ns (logic 0.419ns (28.725%) route 1.040ns (71.275%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.854ns = ( 3592.374 - 3587.520 ) Source Clock Delay (SCD): 5.090ns = ( 3592.590 - 3587.500 ) Clock Pessimism Removal (CPR): 0.249ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 3587.500 3587.500 r V4 0.000 3587.500 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 3587.500 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.960 3588.460 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.233 3589.693 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.089 3589.782 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 1.025 3590.807 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.982 3591.789 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.801 3592.590 hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/OutClk SLICE_X163Y139 FDPE r hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X163Y139 FDPE (Prop_fdpe_C_Q) 0.419 3593.009 f hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/Q net (fo=28, routed) 1.040 3594.049 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/aRst SLICE_X155Y131 FDPE f hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg/PRE ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 3587.520 3587.520 r V4 0.000 3587.520 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 3587.520 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.916 3588.436 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.162 3589.598 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.084 3589.682 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.960 3590.642 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.918 3591.560 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.814 3592.374 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/PixelClk SLICE_X155Y131 FDPE r hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg/C clock pessimism 0.249 3592.623 clock uncertainty -0.053 3592.569 SLICE_X155Y131 FDPE (Recov_fdpe_C_PRE) -0.534 3592.035 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg ------------------------------------------------------------------- required time 3592.035 arrival time -3594.049 ------------------------------------------------------------------- slack -2.013 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.598ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C (rising edge-triggered cell FDPE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Destination: hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg/PRE (removal check against rising-edge clock dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (dvi2rgb_0_PixelClk rise@0.000ns - dvi2rgb_0_PixelClk_1 rise@0.000ns) Data Path Delay: 0.531ns (logic 0.128ns (24.097%) route 0.403ns (75.903%)) Logic Levels: 0 Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.186ns Source Clock Delay (SCD): 1.866ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.481 0.481 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.440 0.921 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.051 0.972 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.363 1.335 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.270 1.605 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.261 1.866 hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/OutClk SLICE_X163Y139 FDPE r hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X163Y139 FDPE (Prop_fdpe_C_Q) 0.128 1.994 f hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/Q net (fo=28, routed) 0.403 2.397 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/aRst SLICE_X159Y130 FDPE f hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg/PRE ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.529 0.529 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.480 1.009 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.054 1.063 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.402 1.465 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.431 1.896 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.290 2.186 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/PixelClk SLICE_X159Y130 FDPE r hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg/C clock pessimism -0.291 1.895 clock uncertainty 0.053 1.948 SLICE_X159Y130 FDPE (Remov_fdpe_C_PRE) -0.149 1.799 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg ------------------------------------------------------------------- required time -1.799 arrival time 2.397 ------------------------------------------------------------------- slack 0.598 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: dvi2rgb_0_PixelClk To Clock: dvi2rgb_0_PixelClk_1 Setup : 3 Failing Endpoints, Worst Slack -2.013ns, Total Violation -5.806ns Hold : 0 Failing Endpoints, Worst Slack 0.598ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (VIOLATED) : -2.013ns (required time - arrival time) Source: hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C (rising edge-triggered cell FDPE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Destination: hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg/PRE (recovery check against rising-edge clock dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 0.020ns (dvi2rgb_0_PixelClk_1 rise@200.000ns - dvi2rgb_0_PixelClk rise@199.980ns) Data Path Delay: 1.459ns (logic 0.419ns (28.725%) route 1.040ns (71.275%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.854ns = ( 204.854 - 200.000 ) Source Clock Delay (SCD): 5.090ns = ( 205.070 - 199.980 ) Clock Pessimism Removal (CPR): 0.249ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 199.980 199.980 r V4 0.000 199.980 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 199.980 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.960 200.940 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.233 202.173 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.089 202.262 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 1.025 203.287 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.982 204.269 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.801 205.070 hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/OutClk SLICE_X163Y139 FDPE r hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X163Y139 FDPE (Prop_fdpe_C_Q) 0.419 205.489 f hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/Q net (fo=28, routed) 1.040 206.529 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/aRst SLICE_X155Y131 FDPE f hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg/PRE ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 200.000 200.000 r V4 0.000 200.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 200.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.916 200.916 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.162 202.078 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.084 202.162 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.960 203.122 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.918 204.040 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.814 204.854 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/PixelClk SLICE_X155Y131 FDPE r hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg/C clock pessimism 0.249 205.103 clock uncertainty -0.053 205.050 SLICE_X155Y131 FDPE (Recov_fdpe_C_PRE) -0.534 204.516 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg ------------------------------------------------------------------- required time 204.516 arrival time -206.529 ------------------------------------------------------------------- slack -2.013 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.598ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C (rising edge-triggered cell FDPE clocked by dvi2rgb_0_PixelClk {rise@0.000ns fall@2.424ns period=6.060ns}) Destination: hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg/PRE (removal check against rising-edge clock dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (dvi2rgb_0_PixelClk_1 rise@0.000ns - dvi2rgb_0_PixelClk rise@0.000ns) Data Path Delay: 0.531ns (logic 0.128ns (24.097%) route 0.403ns (75.903%)) Logic Levels: 0 Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.186ns Source Clock Delay (SCD): 1.866ns Clock Pessimism Removal (CPR): 0.291ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.000ns Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.481 0.481 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.440 0.921 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.051 0.972 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.363 1.335 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.270 1.605 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.261 1.866 hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/OutClk SLICE_X163Y139 FDPE r hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X163Y139 FDPE (Prop_fdpe_C_Q) 0.128 1.994 f hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/Q net (fo=28, routed) 0.403 2.397 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/aRst SLICE_X159Y130 FDPE f hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg/PRE ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.529 0.529 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.480 1.009 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.054 1.063 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.402 1.465 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.431 1.896 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.290 2.186 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/PixelClk SLICE_X159Y130 FDPE r hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg/C clock pessimism -0.291 1.895 clock uncertainty 0.053 1.948 SLICE_X159Y130 FDPE (Remov_fdpe_C_PRE) -0.149 1.799 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg ------------------------------------------------------------------- required time -1.799 arrival time 2.397 ------------------------------------------------------------------- slack 0.598 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: dvi2rgb_0_PixelClk_1 To Clock: dvi2rgb_0_PixelClk_1 Setup : 0 Failing Endpoints, Worst Slack 10.467ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.651ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 10.467ns (required time - arrival time) Source: hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C (rising edge-triggered cell FDPE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Destination: hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg/PRE (recovery check against rising-edge clock dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 12.500ns (dvi2rgb_0_PixelClk_1 rise@12.500ns - dvi2rgb_0_PixelClk_1 rise@0.000ns) Data Path Delay: 1.459ns (logic 0.419ns (28.725%) route 1.040ns (71.275%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.854ns = ( 17.354 - 12.500 ) Source Clock Delay (SCD): 5.090ns Clock Pessimism Removal (CPR): 0.249ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.080ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.960 0.960 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.233 2.193 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.089 2.282 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 1.025 3.307 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.982 4.289 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.801 5.090 hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/OutClk SLICE_X163Y139 FDPE r hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X163Y139 FDPE (Prop_fdpe_C_Q) 0.419 5.509 f hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/Q net (fo=28, routed) 1.040 6.549 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/aRst SLICE_X155Y131 FDPE f hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg/PRE ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 12.500 12.500 r V4 0.000 12.500 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 12.500 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.916 13.416 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 1.162 14.578 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.084 14.662 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.960 15.622 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.918 16.540 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.814 17.354 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/PixelClk SLICE_X155Y131 FDPE r hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg/C clock pessimism 0.249 17.603 clock uncertainty -0.053 17.550 SLICE_X155Y131 FDPE (Recov_fdpe_C_PRE) -0.534 17.016 hdmi_i/dvi2rgb_0/U0/DataDecoders[0].DecoderX/pAlignRst_reg ------------------------------------------------------------------- required time 17.016 arrival time -6.549 ------------------------------------------------------------------- slack 10.467 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.651ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C (rising edge-triggered cell FDPE clocked by dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Destination: hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg/PRE (removal check against rising-edge clock dvi2rgb_0_PixelClk_1 {rise@0.000ns fall@5.000ns period=12.500ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (dvi2rgb_0_PixelClk_1 rise@0.000ns - dvi2rgb_0_PixelClk_1 rise@0.000ns) Data Path Delay: 0.531ns (logic 0.128ns (24.097%) route 0.403ns (75.903%)) Logic Levels: 0 Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.186ns Source Clock Delay (SCD): 1.866ns Clock Pessimism Removal (CPR): 0.291ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.481 0.481 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.440 0.921 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.051 0.972 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.363 1.335 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.270 1.605 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.261 1.866 hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/OutClk SLICE_X163Y139 FDPE r hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X163Y139 FDPE (Prop_fdpe_C_Q) 0.128 1.994 f hdmi_i/dvi2rgb_0/U0/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/Q net (fo=28, routed) 0.403 2.397 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/aRst SLICE_X159Y130 FDPE f hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg/PRE ------------------------------------------------------------------- ------------------- (clock dvi2rgb_0_PixelClk_1 rise edge) 0.000 0.000 r V4 0.000 0.000 r TMDS_IN_clk_p (IN) net (fo=0) 0.000 0.000 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/TMDS_Clk_p V4 IBUFDS (Prop_ibufds_I_O) 0.529 0.529 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/InputBuffer/O net (fo=1, routed) 0.480 1.009 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_IN_hdmi_clk MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) 0.054 1.063 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator/CLKOUT0 net (fo=2, routed) 0.402 1.465 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/CLK_OUT_5x_hdmi_clk BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.431 1.896 r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer/O net (fo=3237, routed) 0.290 2.186 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/PixelClk SLICE_X159Y130 FDPE r hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg/C clock pessimism -0.291 1.895 SLICE_X159Y130 FDPE (Remov_fdpe_C_PRE) -0.149 1.746 hdmi_i/dvi2rgb_0/U0/DataDecoders[1].DecoderX/pAlignRst_reg ------------------------------------------------------------------- required time -1.746 arrival time 2.397 ------------------------------------------------------------------- slack 0.651 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: hdmi_i/dvi2rgb_0/U0/RefClk To Clock: hdmi_i/dvi2rgb_0/U0/RefClk Setup : 0 Failing Endpoints, Worst Slack 2.813ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.384ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.813ns (required time - arrival time) Source: hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/RdyLostReset/SyncAsyncx/oSyncStages_reg[1]/C (rising edge-triggered cell FDPE clocked by hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/CLR (recovery check against rising-edge clock hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 5.000ns (hdmi_i/dvi2rgb_0/U0/RefClk rise@5.000ns - hdmi_i/dvi2rgb_0/U0/RefClk rise@0.000ns) Data Path Delay: 1.633ns (logic 0.478ns (29.271%) route 1.155ns (70.729%)) Logic Levels: 0 Clock Path Skew: 0.058ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.881ns = ( 6.881 - 5.000 ) Source Clock Delay (SCD): 1.830ns Clock Pessimism Removal (CPR): 0.007ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.830 1.830 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/RdyLostReset/SyncAsyncx/RefClk SLICE_X162Y112 FDPE r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/RdyLostReset/SyncAsyncx/oSyncStages_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X162Y112 FDPE (Prop_fdpe_C_Q) 0.478 2.308 f hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/RdyLostReset/SyncAsyncx/oSyncStages_reg[1]/Q net (fo=2, routed) 1.155 3.463 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/dbg_rRdyRst SLICE_X160Y94 FDCE f hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/CLR ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 5.000 5.000 r BUFGCTRL_X0Y17 BUFG 0.000 5.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.881 6.881 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/RefClk SLICE_X160Y94 FDCE r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg/C clock pessimism 0.007 6.888 clock uncertainty -0.035 6.853 SLICE_X160Y94 FDCE (Recov_fdce_C_CLR) -0.576 6.277 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/aLocked_reg ------------------------------------------------------------------- required time 6.277 arrival time -3.463 ------------------------------------------------------------------- slack 2.813 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.384ns (arrival time - required time) Source: hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C (rising edge-triggered cell FDPE clocked by hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/rMMCM_Reset_q_reg[0]/PRE (removal check against rising-edge clock hdmi_i/dvi2rgb_0/U0/RefClk {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (hdmi_i/dvi2rgb_0/U0/RefClk rise@0.000ns - hdmi_i/dvi2rgb_0/U0/RefClk rise@0.000ns) Data Path Delay: 0.584ns (logic 0.128ns (21.928%) route 0.456ns (78.072%)) Logic Levels: 0 Clock Path Skew: 0.349ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.994ns Source Clock Delay (SCD): 0.640ns Clock Pessimism Removal (CPR): 0.005ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 0.640 0.640 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/LockLostReset/SyncAsyncx/RefClk SLICE_X159Y120 FDPE r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X159Y120 FDPE (Prop_fdpe_C_Q) 0.128 0.768 f hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/LockLostReset/SyncAsyncx/oSyncStages_reg[1]/Q net (fo=8, routed) 0.456 1.223 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/rLockLostRst SLICE_X160Y99 FDPE f hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/rMMCM_Reset_q_reg[0]/PRE ------------------------------------------------------------------- ------------------- (clock hdmi_i/dvi2rgb_0/U0/RefClk rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 0.994 0.994 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/RefClk SLICE_X160Y99 FDPE r hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/rMMCM_Reset_q_reg[0]/C clock pessimism -0.005 0.989 SLICE_X160Y99 FDPE (Remov_fdpe_C_PRE) -0.149 0.840 hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/rMMCM_Reset_q_reg[0] ------------------------------------------------------------------- required time -0.840 arrival time 1.223 ------------------------------------------------------------------- slack 0.384 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: mmcm_clkout0 To Clock: mmcm_clkout0 Setup : 0 Failing Endpoints, Worst Slack 1.895ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.413ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.895ns (required time - arrival time) Source: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_wr_rst_reg[0]/C (rising edge-triggered cell FDRE clocked by mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Destination: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST (recovery check against rising-edge clock mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 6.250ns (mmcm_clkout0 rise@6.250ns - mmcm_clkout0 rise@0.000ns) Data Path Delay: 2.070ns (logic 0.580ns (28.016%) route 1.490ns (71.984%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.158ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.274ns = ( 11.524 - 6.250 ) Source Clock Delay (SCD): 5.323ns Clock Pessimism Removal (CPR): 0.206ns Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.133ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout0 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0 net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout0 BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_0/O net (fo=624, routed) 1.692 5.323 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/s_axis_s2mm_aclk SLICE_X139Y109 FDRE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_wr_rst_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y109 FDRE (Prop_fdre_C_Q) 0.456 5.779 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.power_on_wr_rst_reg[0]/Q net (fo=3, routed) 0.588 6.367 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/power_on_wr_rst[0] SLICE_X138Y111 LUT2 (Prop_lut2_I1_O) 0.124 6.491 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/gf36e1_inst.sngfifo36e1_i_2__3/O net (fo=3, routed) 0.902 7.393 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/RST RAMB36_X7Y19 FIFO36E1 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/RST ------------------------------------------------------------------- ------------------- (clock mmcm_clkout0 rise edge) 6.250 6.250 r R4 0.000 6.250 r sys_clk_i (IN) net (fo=0) 0.000 6.250 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 7.655 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 8.935 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 9.018 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.289 10.307 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.081 10.388 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.904 11.292 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.425 7.867 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0 net (fo=1, routed) 1.723 9.590 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout0 BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 9.681 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_0/O net (fo=624, routed) 1.843 11.524 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/s_axis_s2mm_aclk RAMB36_X7Y19 FIFO36E1 r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1/WRCLK clock pessimism 0.206 11.731 clock uncertainty -0.075 11.655 RAMB36_X7Y19 FIFO36E1 (Recov_fifo36e1_WRCLK_RST) -2.368 9.287 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/v7_bi_fifo.fblk/gextw[4].gnll_fifo.inst_extd/gonep.inst_prim/gf36e1_inst.sngfifo36e1 ------------------------------------------------------------------- required time 9.287 arrival time -7.393 ------------------------------------------------------------------- slack 1.895 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.413ns (arrival time - required time) Source: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_ON_SKID.I_S2MM_SKID_FLUSH_SOF/sig_reset_reg_reg/C (rising edge-triggered cell FDRE clocked by mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Destination: hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_reg1_reg/PRE (removal check against rising-edge clock mmcm_clkout0 {rise@0.000ns fall@3.125ns period=6.250ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns) Data Path Delay: 0.353ns (logic 0.164ns (46.495%) route 0.189ns (53.505%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.072ns Source Clock Delay (SCD): 1.543ns Clock Pessimism Removal (CPR): 0.518ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout0 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0 net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout0 BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_0/O net (fo=624, routed) 0.612 1.543 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_ON_SKID.I_S2MM_SKID_FLUSH_SOF/s_axis_s2mm_aclk SLICE_X146Y128 FDRE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_ON_SKID.I_S2MM_SKID_FLUSH_SOF/sig_reset_reg_reg/C ------------------------------------------------------------------- ------------------- SLICE_X146Y128 FDRE (Prop_fdre_C_Q) 0.164 1.707 f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.GEN_S2MM_DRE_ON_SKID.I_S2MM_SKID_FLUSH_SOF/sig_reset_reg_reg/Q net (fo=4, routed) 0.189 1.896 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/sig_reset_reg SLICE_X146Y126 FDPE f hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_reg1_reg/PRE ------------------------------------------------------------------- ------------------- (clock mmcm_clkout0 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.472 1.480 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.043 1.523 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.538 2.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.475 0.586 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT0 net (fo=1, routed) 0.579 1.164 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout0 BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 1.193 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_0/O net (fo=624, routed) 0.879 2.072 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/s_axis_s2mm_aclk SLICE_X146Y126 FDPE r hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_reg1_reg/C clock pessimism -0.518 1.554 SLICE_X146Y126 FDPE (Remov_fdpe_C_PRE) -0.071 1.483 hdmi_i/axi_vdma_0/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_ASYNC_FIFO_FLUSH_SOF.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.wr_rst_reg1_reg ------------------------------------------------------------------- required time -1.483 arrival time 1.896 ------------------------------------------------------------------- slack 0.413 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: mmcm_clkout1 To Clock: mmcm_clkout1 Setup : 0 Failing Endpoints, Worst Slack 1.636ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.360ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.636ns (required time - arrival time) Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/current_state_reg[3]/CLR (recovery check against rising-edge clock mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 5.000ns (mmcm_clkout1 rise@5.000ns - mmcm_clkout1 rise@0.000ns) Data Path Delay: 2.922ns (logic 0.456ns (15.607%) route 2.466ns (84.393%)) Logic Levels: 0 Clock Path Skew: -0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.152ns = ( 10.152 - 5.000 ) Source Clock Delay (SCD): 5.489ns Clock Pessimism Removal (CPR): 0.287ns Clock Uncertainty: 0.073ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.127ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.356 2.831 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.088 2.919 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.370 4.289 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.127 4.416 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.943 5.359 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -3.633 1.726 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 1.808 3.534 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 3.630 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.858 5.489 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk SLICE_X107Y95 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y95 FDRE (Prop_fdre_C_Q) 0.456 5.945 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q net (fo=168, routed) 2.466 8.410 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0] SLICE_X100Y91 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/current_state_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 5.000 5.000 r R4 0.000 5.000 r sys_clk_i (IN) net (fo=0) 0.000 5.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 1.405 6.405 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 1.280 7.685 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.083 7.768 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 1.289 9.057 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.081 9.138 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.904 10.042 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -3.425 6.617 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 1.723 8.340 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 1.721 10.152 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk SLICE_X100Y91 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/current_state_reg[3]/C clock pessimism 0.287 10.439 clock uncertainty -0.073 10.366 SLICE_X100Y91 FDCE (Recov_fdce_C_CLR) -0.319 10.047 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/current_state_reg[3] ------------------------------------------------------------------- required time 10.047 arrival time -8.410 ------------------------------------------------------------------- slack 1.636 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.360ns (arrival time - required time) Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C (rising edge-triggered cell FDPE clocked by mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE (removal check against rising-edge clock mmcm_clkout1 {rise@0.000ns fall@2.500ns period=5.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mmcm_clkout1 rise@0.000ns - mmcm_clkout1 rise@0.000ns) Data Path Delay: 0.281ns (logic 0.141ns (50.212%) route 0.140ns (49.788%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.123ns Source Clock Delay (SCD): 1.587ns Clock Pessimism Removal (CPR): 0.520ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.478 0.721 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.050 0.771 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.426 1.197 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.020 1.217 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.313 1.530 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -1.156 0.375 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 0.531 0.906 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.932 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 0.655 1.587 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk SLICE_X105Y88 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y88 FDPE (Prop_fdpe_C_Q) 0.141 1.728 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q net (fo=10, routed) 0.140 1.868 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/AR[0] SLICE_X107Y88 FDPE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/PRE ------------------------------------------------------------------- ------------------- (clock mmcm_clkout1 rise edge) 0.000 0.000 r R4 0.000 0.000 r sys_clk_i (IN) net (fo=0) 0.000 0.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/sys_clk_i R4 IBUF (Prop_ibuf_I_O) 0.431 0.431 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_clk_ibuf/se_input_clk.u_ibufg_sys_clk/O net (fo=1, routed) 0.524 0.955 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clk PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) 0.053 1.008 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 net (fo=1, routed) 0.472 1.480 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3_out BUFHCE_X1Y36 BUFH (Prop_bufh_I_O) 0.043 1.523 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O net (fo=1, routed) 0.538 2.061 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/pll_clk3 MMCME2_ADV_X1Y3 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) -1.475 0.586 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKOUT1 net (fo=1, routed) 0.579 1.164 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/mmcm_clkout1 BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 1.193 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.u_bufg_ui_addn_clk_1/O net (fo=4131, routed) 0.930 2.123 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/clk SLICE_X107Y88 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg/C clock pessimism -0.520 1.603 SLICE_X107Y88 FDPE (Remov_fdpe_C_PRE) -0.095 1.508 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i_reg ------------------------------------------------------------------- required time -1.508 arrival time 1.868 ------------------------------------------------------------------- slack 0.360 --------------------------------------------------------------------------------------------------- Path Group: **default** From Clock: clk_pll_i To Clock: Setup : 0 Failing Endpoints, Worst Slack 2.241ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.241ns (required time - arrival time) Source: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET Path Group: **default** Path Type: Max at Slow Process Corner Requirement: 5.000ns (MaxDelay Path 5.000ns) Data Path Delay: 2.759ns (logic 0.456ns (16.526%) route 2.303ns (83.474%)) Logic Levels: 0 Output Delay: 0.000ns Timing Exception: MaxDelay Path 5.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- SLICE_X151Y213 0.000 0.000 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C SLICE_X151Y213 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q net (fo=51, routed) 2.303 2.759 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rstdiv0_sync_r1_reg_rep PHY_CONTROL_X1Y3 PHY_CONTROL r hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET ------------------------------------------------------------------- ------------------- max delay 5.000 5.000 PHY_CONTROL_X1Y3 PHY_CONTROL 0.000 5.000 hdmi_i/mig_7series_0/u_hdmi_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i output delay -0.000 5.000 ------------------------------------------------------------------- required time 5.000 arrival time -2.759 ------------------------------------------------------------------- slack 2.241